[haiku-commits] r42961 - haiku/trunk/headers/os/drivers

  • From: superstippi@xxxxxx
  • To: haiku-commits@xxxxxxxxxxxxx
  • Date: Sat, 29 Oct 2011 17:51:05 +0200 (CEST)

Author: stippi
Date: 2011-10-29 17:51:04 +0200 (Sat, 29 Oct 2011)
New Revision: 42961
Changeset: https://dev.haiku-os.org/changeset/42961

Modified:
   haiku/trunk/headers/os/drivers/ISA.h
   haiku/trunk/headers/os/drivers/PCI.h
Log:
Reverted r42958 as it is broken and I completely forgot to compile before
I commited... need to get back into the habbit, sorry for the noise.


Modified: haiku/trunk/headers/os/drivers/ISA.h
===================================================================
--- haiku/trunk/headers/os/drivers/ISA.h        2011-10-29 15:47:21 UTC (rev 
42960)
+++ haiku/trunk/headers/os/drivers/ISA.h        2011-10-29 15:51:04 UTC (rev 
42961)
@@ -1,85 +1,83 @@
-/* 
- * Copyright 2010-2011, Haiku Inc. All Rights Reserved.
- * Distributed under the terms of the MIT License.
- */
+/*******************************************************************************
+/
+/      File:                   ISA.h
+/
+/      Description:    Interface to ISA module
+/
+/      Copyright 1998, Be Incorporated, All Rights Reserved.
+/
+*******************************************************************************/
+
 #ifndef _ISA_H
 #define _ISA_H
 
-
-#include <SupportDefs.h>
+//#include <SupportDefs.h>
 #include <bus_manager.h>
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/* ---
+       ISA scatter/gather dma support.
+--- */
 
-typedef struct isa_dma_entry {
-       uint32  address;
-       uint16  transfer_count;
-       uchar   reserved;
-       uchar   flag;
+typedef struct {
+       ulong   address;                                /* memory address 
(little endian!) 4 bytes */
+       ushort  transfer_count;                 /* # transfers minus one 
(little endian!) 2 bytes*/
+       uchar   reserved;                               /* filler, 1byte*/
+    uchar   flag;                                      /* end of link flag, 
1byte */
 } isa_dma_entry;
 
+#define        B_LAST_ISA_DMA_ENTRY    0x80    /* sets end of link flag in 
isa_dma_entry */
 
-#define        B_LAST_ISA_DMA_ENTRY    0x80
-
-
 enum {
        B_8_BIT_TRANSFER,
        B_16_BIT_TRANSFER
 };
 
-
 #define B_MAX_ISA_DMA_COUNT    0x10000
 
-
-typedef struct isa_module_info isa_module_info;
-struct isa_module_info {
+typedef struct isa_module_info {
        bus_manager_info        binfo;
 
-       uint8                           (*read_io_8) (int32 mapped_io_addr);
-       void                            (*write_io_8) (int32 mapped_io_addr, 
uint8 value);
-       uint16                          (*read_io_16) (int32 mapped_io_addr);
-       void                            (*write_io_16) (int32 mapped_io_addr, 
uint16 value);
-       uint32                          (*read_io_32) (int32 mapped_io_addr);
-       void                            (*write_io_32) (int32 mapped_io_addr, 
uint32 value);
+       uint8                   (*read_io_8) (int mapped_io_addr);
+       void                    (*write_io_8) (int mapped_io_addr, uint8 value);
+       uint16                  (*read_io_16) (int mapped_io_addr);
+       void                    (*write_io_16) (int mapped_io_addr, uint16 
value);
+       uint32                  (*read_io_32) (int mapped_io_addr);
+       void                    (*write_io_32) (int mapped_io_addr, uint32 
value);
 
-       void*                           (*ram_address) 
-                                                       (const void * 
physical_address_in_system_memory);
+       void *                  (*ram_address) (const void 
*physical_address_in_system_memory);
 
-       int32                           (*make_isa_dma_table) (
-                                                       const void              
*buffer,
-                                                       int32                   
buffer_size,
-                                                       uint32                  
num_bits,
-                                                       isa_dma_entry   *table,
-                                                       int32                   
num_entries
+       long                    (*make_isa_dma_table) (
+                                                       const void              
*buffer,                /* buffer to make a table for */
+                                                       long                    
buffer_size,    /* buffer size */
+                                                       ulong                   
num_bits,               /* dma transfer size that will be used */
+                                                       isa_dma_entry   *table, 
                /* -> caller-supplied scatter/gather table */
+                                                       long                    
num_entries             /* max # entries in table */
                                                );
-       int32                           (*start_isa_dma) (
-                                                       int32   channel,
-                                                       void    *buf,
-                                                       int32   transfer_count,
-                                                       uchar   mode,
-                                                       uchar   e_mode
+       long                    (*start_isa_dma) (
+                                                       long    channel,        
                        /* dma channel to use */
+                                                       void    *buf,           
                        /* buffer to transfer */
+                                                       long    transfer_count, 
                /* # transfers */
+                                                       uchar   mode,           
                        /* mode flags */
+                                                       uchar   e_mode          
                        /* extended mode flags */
                                                );
-       int32                           (*start_scattered_isa_dma) (
-                                                       int32                   
                channel,
-                                                       const isa_dma_entry*    
table,
-                                                       uchar                   
                mode,
-                                                       uchar                   
                emode
+       long                    (*start_scattered_isa_dma) (
+                                                       long                    
        channel,        /* channel # to use */
+                                                       const isa_dma_entry     
*table,         /* physical address of scatter/gather table */
+                                                       uchar                   
        mode,           /* mode flags */
+                                                       uchar                   
        emode           /* extended mode flags */
                                                );
-       int32                           (*lock_isa_dma_channel) (int32 channel);
-       int32                           (*unlock_isa_dma_channel) (int32 
channel);
-};
-
-
+       long                    (*lock_isa_dma_channel) (long channel);
+       long                    (*unlock_isa_dma_channel) (long channel);
+} isa_module_info;
+       
 #define        B_ISA_MODULE_NAME               "bus_managers/isa/v1"
 
-
 #ifdef __cplusplus
 }
 #endif
 
-
 #endif /* _ISA_H */

Modified: haiku/trunk/headers/os/drivers/PCI.h
===================================================================
--- haiku/trunk/headers/os/drivers/PCI.h        2011-10-29 15:47:21 UTC (rev 
42960)
+++ haiku/trunk/headers/os/drivers/PCI.h        2011-10-29 15:51:04 UTC (rev 
42961)
@@ -1,25 +1,35 @@
-/* 
- * Copyright 2010-2011, Haiku Inc. All Rights Reserved.
- * Distributed under the terms of the MIT License.
- */
+/*******************************************************************************
+/
+/      File:           PCI.h
+/
+/      Description:    Interface to the PCI bus.
+/      For more information, see "PCI Local Bus Specification, Revision 2.1",
+/      PCI Special Interest Group, 1995.
+/
+/      Copyright 1993-98, Be Incorporated, All Rights Reserved.
+/
+*******************************************************************************/
+
+
 #ifndef _PCI_H
 #define _PCI_H
 
-
-#include <SupportDefs.h>
+//#include <BeBuild.h>
+//#include <SupportDefs.h>
 #include <bus_manager.h>
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 
-/* pci device info */
-typedef struct pci_info pci_info;
+/* -----
+       pci device info
+----- */
+
 typedef struct pci_info {
-       uint16  vendor_id;                              /* vendor id */
-       uint16  device_id;                              /* device id */
+       ushort  vendor_id;                              /* vendor id */
+       ushort  device_id;                              /* device id */
        uchar   bus;                                    /* bus number */
        uchar   device;                                 /* device number on bus 
*/
        uchar   function;                               /* function number in 
device */
@@ -34,15 +44,15 @@
        uchar   reserved;                               /* filler, for 
alignment */
        union {
                struct {
-                       uint32  cardbus_cis;                    /* CardBus CIS 
pointer */
-                       uint16  subsystem_id;                   /* subsystem 
(add-in card) id */
-                       uint16  subsystem_vendor_id;    /* subsystem vendor id 
*/
-                       uint32  rom_base;                               /* rom 
base addr, view from host */
-                       uint32  rom_base_pci;                   /* rom base 
addr, viewed from pci */
-                       uint32  rom_size;                               /* rom 
size */
-                       uint32  base_registers[6];              /* base 
registers, view from host */
-                       uint32  base_registers_pci[6];  /* base registers, view 
from pci */
-                       uint32  base_register_sizes[6]; /* size of what base 
regs point */
+                       ulong   cardbus_cis;                    /* CardBus CIS 
pointer */
+                       ushort  subsystem_id;                   /* subsystem 
(add-in card) id */
+                       ushort  subsystem_vendor_id;    /* subsystem (add-in 
card) vendor id */
+                       ulong   rom_base;                               /* rom 
base address, viewed from host */
+                       ulong   rom_base_pci;                   /* rom base 
addr, viewed from pci */
+                       ulong   rom_size;                               /* rom 
size */
+                       ulong   base_registers[6];              /* base 
registers, viewed from host */
+                       ulong   base_registers_pci[6];  /* base registers, 
viewed from pci */
+                       ulong   base_register_sizes[6]; /* size of what base 
regs point to */
                        uchar   base_register_flags[6]; /* flags from base 
address fields */
                        uchar   interrupt_line;                 /* interrupt 
line */
                        uchar   interrupt_pin;                  /* interrupt 
pin */
@@ -50,9 +60,9 @@
                        uchar   max_latency;                    /* how often 
PCI access needed */
                } h0;
                struct {
-                       uint32  base_registers[2];              /* base 
registers, view from host */
-                       uint32  base_registers_pci[2];  /* base registers, view 
from pci */
-                       uint32  base_register_sizes[2]; /* size of what base 
regs point */
+                       ulong   base_registers[2];              /* base 
registers, viewed from host */
+                       ulong   base_registers_pci[2];  /* base registers, 
viewed from pci */
+                       ulong   base_register_sizes[2]; /* size of what base 
regs point to */
                        uchar   base_register_flags[2]; /* flags from base 
address fields */
                        uchar   primary_bus;
                        uchar   secondary_bus;
@@ -60,64 +70,65 @@
                        uchar   secondary_latency;
                        uchar   io_base;
                        uchar   io_limit;
-                       uint16  secondary_status;
-                       uint16  memory_base;
-                       uint16  memory_limit;
-                       uint16  prefetchable_memory_base;
-                       uint16  prefetchable_memory_limit;
-                       uint32  prefetchable_memory_base_upper32;
-                       uint32  prefetchable_memory_limit_upper32;
-                       uint16  io_base_upper16;
-                       uint16  io_limit_upper16;
-                       uint32  rom_base;                               /* rom 
base addr, view from host */
-                       uint32  rom_base_pci;                   /* rom base 
addr, view from pci */
+                       ushort  secondary_status;
+                       ushort  memory_base;
+                       ushort  memory_limit;
+                       ushort  prefetchable_memory_base;
+                       ushort  prefetchable_memory_limit;
+                       ulong   prefetchable_memory_base_upper32;
+                       ulong   prefetchable_memory_limit_upper32;
+                       ushort  io_base_upper16;
+                       ushort  io_limit_upper16;
+                       ulong   rom_base;                               /* rom 
base address, viewed from host */
+                       ulong   rom_base_pci;                   /* rom base 
addr, viewed from pci */
                        uchar   interrupt_line;                 /* interrupt 
line */
                        uchar   interrupt_pin;                  /* interrupt 
pin */
-                       uint16  bridge_control;
-                       uint16  subsystem_id;                   /* subsystem 
(add-in card) id */
-                       uint16  subsystem_vendor_id;    /* subsystem vendor id 
*/
+                       ushort  bridge_control;
+                       ushort  subsystem_id;                   /* subsystem 
(add-in card) id */
+                       ushort  subsystem_vendor_id;    /* subsystem (add-in 
card) vendor id */
                } h1;
                struct {
-                       uint16  subsystem_id;                   /* subsystem 
(add-in card) id */
-                       uint16  subsystem_vendor_id;    /* subsystem vendor id 
*/
+                       ushort  subsystem_id;                   /* subsystem 
(add-in card) id */
+                       ushort  subsystem_vendor_id;    /* subsystem (add-in 
card) vendor id */
 
 #ifdef __HAIKU_PCI_BUS_MANAGER_TESTING
                        // for testing only, not final (do not use!):
-                       uchar           primary_bus;
-                       uchar           secondary_bus;
-                       uchar           subordinate_bus;
-                       uchar           secondary_latency;
-                       uint16          reserved;
-                       uint32          memory_base;
-                       uint32          memory_limit;
-                       uint32          memory_base_upper32;
-                       uint32          memory_limit_upper32;
-                       uint32          io_base;
-                       uint32          io_limit;
-                       uint32          io_base_upper32;
-                       uint32          io_limit_upper32;
-                       uint16          secondary_status;
-                       uint16          bridge_control;
+                       uchar   primary_bus;
+                       uchar   secondary_bus;
+                       uchar   subordinate_bus;
+                       uchar   secondary_latency;
+                       ushort  reserved;
+                       ulong   memory_base;
+                       ulong   memory_limit;
+                       ulong   memory_base_upper32;
+                       ulong   memory_limit_upper32;
+                       ulong   io_base;
+                       ulong   io_limit;
+                       ulong   io_base_upper32;
+                       ulong   io_limit_upper32;
+                       ushort  secondary_status;
+                       ushort  bridge_control;
 #endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */
                } h2;
        } u;
-};
+} pci_info;
 
 
 typedef struct pci_module_info pci_module_info;
-typedef struct pci_module_info {
+
+struct pci_module_info {
        bus_manager_info        binfo;
 
-       uint8                   (*read_io_8) (int32 mapped_io_addr);
-       void                    (*write_io_8) (int32 mapped_io_addr, uint8 
value);
-       uint16                  (*read_io_16) (int32 mapped_io_addr);
-       void                    (*write_io_16) (int32 mapped_io_addr, uint16 
value);
-       uint32                  (*read_io_32) (int32 mapped_io_addr);
-       void                    (*write_io_32) (int32 mapped_io_addr, uint32 
value);
+       uint8                   (*read_io_8) (int mapped_io_addr);
+       void                    (*write_io_8) (int mapped_io_addr, uint8 value);
+       uint16                  (*read_io_16) (int mapped_io_addr);
+       void                    (*write_io_16) (int mapped_io_addr, uint16 
value);
+       uint32                  (*read_io_32) (int mapped_io_addr);
+       void                    (*write_io_32) (int mapped_io_addr, uint32 
value);
 
-       int32                   (*get_nth_pci_info) (
-                                               int32           index,  /* 
index into pci device table */
-                                               pci_info        *info   /* 
caller-supplied buf for info */
+       long                    (*get_nth_pci_info) (
+                                               long            index,  /* 
index into pci device table */
+                                               pci_info        *info   /* 
caller-supplied buffer for info */
                                        );
        uint32                  (*read_pci_config) (
                                                uchar   bus,            /* bus 
number */
@@ -135,8 +146,7 @@
                                                uint32  value           /* 
value to write */
                                        );
 
-       void*                   (*ram_address) 
-                                               (const void* 
physical_address_in_system_memory);
+       void *                  (*ram_address) (const void 
*physical_address_in_system_memory);
 
        status_t                (*find_pci_capability) (
                                                uchar   bus,
@@ -147,17 +157,17 @@
                                        );
 
        status_t                (*reserve_device) (
-                                               uchar           bus,
-                                               uchar           device,
-                                               uchar           function,
-                                               const char*     driver_name,
-                                               void*           cookie);
+                                               uchar bus,
+                                               uchar device,
+                                               uchar function,
+                                               const char *driver_name,
+                                               void *cookie);
        status_t                (*unreserve_device) (
-                                               uchar           bus,
-                                               uchar           device,
-                                               uchar           function,
-                                               const char*     driver_name,
-                                               void*           cookie);
+                                               uchar bus,
+                                               uchar device,
+                                               uchar function,
+                                               const char *driver_name,
+                                               void *cookie);
 
        status_t                (*update_interrupt_line) (
                                                uchar bus,
@@ -168,379 +178,517 @@
 
 #define        B_PCI_MODULE_NAME               "bus_managers/pci/v1"
 
+/* ---
+       offsets in PCI configuration space to the elements of the predefined
+       header common to all header types
+--- */
 
-/* offsets in PCI config space to the elements of the predefined header */
-/* offsets common to all header types */
-#define PCI_vendor_id                  0x00    /* vendor id */
-#define PCI_device_id                  0x02    /* device id */
-#define PCI_command                            0x04    /* command */
-#define PCI_status                             0x06    /* status */
-#define PCI_revision                   0x08    /* revision id */
-#define PCI_class_api                  0x09    /* specific register interface 
type */
-#define PCI_class_sub                  0x0A    /* specific device function */
-#define PCI_class_base                 0x0B    /* device type */
-#define PCI_line_size                  0x0C    /* cache line size in 32 bit 
words */
-#define PCI_latency                            0x0D    /* latency timer */
-#define PCI_header_type                        0x0E    /* header type */
-#define PCI_bist                               0x0F    /* built-in self-test */
+#define PCI_vendor_id                  0x00            /* (2 byte) vendor id */
+#define PCI_device_id                  0x02            /* (2 byte) device id */
+#define PCI_command                            0x04            /* (2 byte) 
command */
+#define PCI_status                             0x06            /* (2 byte) 
status */
+#define PCI_revision                   0x08            /* (1 byte) revision id 
*/
+#define PCI_class_api                  0x09            /* (1 byte) specific 
register interface type */
+#define PCI_class_sub                  0x0a            /* (1 byte) specific 
device function */
+#define PCI_class_base                 0x0b            /* (1 byte) device type 
(display vs network, etc) */
+#define PCI_line_size                  0x0c            /* (1 byte) cache line 
size in 32 bit words */
+#define PCI_latency                            0x0d            /* (1 byte) 
latency timer */
+#define PCI_header_type                        0x0e            /* (1 byte) 
header type */
+#define PCI_bist                               0x0f            /* (1 byte) 
built-in self-test */
 
-/* offsets common to header types 0x00 and 0x01 */
-#define PCI_base_registers             0x10    /* base registers */
-#define PCI_interrupt_line             0x3C    /* interrupt line */
-#define PCI_interrupt_pin              0x3D    /* interrupt pin */
 
-/* offsets common to header type 0x00 */
-#define PCI_cardbus_cis                        0x28    /* CardBus CIS pointer 
*/
-#define PCI_subsystem_vendor_id                0x2C    /* subsystem vendor id 
*/
-#define PCI_subsystem_id               0x2E    /* subsystem id */
-#define PCI_rom_base                   0x30    /* expansion rom base address */
-#define PCI_capabilities_ptr           0x34    /* point to start of cap list */
-#define PCI_min_grant                  0x3E    /* burst period @ 33 Mhz */
-#define PCI_max_latency                        0x3F    /* how often need PCI 
access */
 
-/* offsets common to the elements of header type 0x01 (PCI-to-PCI bridge) */
-#define PCI_primary_bus                                                        
        0x18
-#define PCI_secondary_bus                                                      
0x19
-#define PCI_subordinate_bus                                                    
0x1A
-#define PCI_secondary_latency                                          0x1B
-#define PCI_io_base                                                            
        0x1C
-#define PCI_io_limit                                                           
0x1D
-#define PCI_secondary_status                                           0x1E
-#define PCI_memory_base                                                        
        0x20
-#define PCI_memory_limit                                                       
0x22
-#define PCI_prefetchable_memory_base                           0x24
-#define PCI_prefetchable_memory_limit                          0x26
+/* ---
+       offsets in PCI configuration space to the elements of the predefined
+       header common to header types 0x00 and 0x01
+--- */
+#define PCI_base_registers             0x10            /* base registers (size 
varies) */
+#define PCI_interrupt_line             0x3c            /* (1 byte) interrupt 
line */
+#define PCI_interrupt_pin              0x3d            /* (1 byte) interrupt 
pin */
+
+
+
+/* ---
+       offsets in PCI configuration space to the elements of header type 0x00
+--- */
+
+#define PCI_cardbus_cis                        0x28            /* (4 bytes) 
CardBus CIS (Card Information Structure) pointer (see PCMCIA v2.10 Spec) */
+#define PCI_subsystem_vendor_id        0x2c            /* (2 bytes) subsystem 
(add-in card) vendor id */
+#define PCI_subsystem_id               0x2e            /* (2 bytes) subsystem 
(add-in card) id */
+#define PCI_rom_base                   0x30            /* (4 bytes) expansion 
rom base address */
+#define PCI_capabilities_ptr    0x34        /* (1 byte) pointer to the start 
of the capabilities list */
+#define PCI_min_grant                  0x3e            /* (1 byte) burst 
period @ 33 Mhz */
+#define PCI_max_latency                        0x3f            /* (1 byte) how 
often PCI access needed */
+
+
+/* ---
+       offsets in PCI configuration space to the elements of header type 0x01 
(PCI-to-PCI bridge)
+--- */
+
+#define PCI_primary_bus                                                        
        0x18 /* (1 byte) */
+#define PCI_secondary_bus                                                      
0x19 /* (1 byte) */
+#define PCI_subordinate_bus                                                    
0x1A /* (1 byte) */
+#define PCI_secondary_latency                                          0x1B /* 
(1 byte) latency of secondary bus */
+#define PCI_io_base                                                            
        0x1C /* (1 byte) io base address register for 2ndry bus*/
+#define PCI_io_limit                                                           
0x1D /* (1 byte) */
+#define PCI_secondary_status                                           0x1E /* 
(2 bytes) */
+#define PCI_memory_base                                                        
        0x20 /* (2 bytes) */
+#define PCI_memory_limit                                                       
0x22 /* (2 bytes) */
+#define PCI_prefetchable_memory_base                           0x24 /* (2 
bytes) */
+#define PCI_prefetchable_memory_limit                          0x26 /* (2 
bytes) */
 #define PCI_prefetchable_memory_base_upper32           0x28
 #define PCI_prefetchable_memory_limit_upper32          0x2C
-#define PCI_io_base_upper16                                                    
0x30
-#define PCI_io_limit_upper16                                           0x32
-#define PCI_sub_vendor_id_1                                                    
0x34
-#define PCI_sub_device_id_1                                                    
0x36
+#define PCI_io_base_upper16                                                    
0x30 /* (2 bytes) */
+#define PCI_io_limit_upper16                                           0x32 /* 
(2 bytes) */
+#define PCI_sub_vendor_id_1                         0x34 /* (2 bytes) */
+#define PCI_sub_device_id_1                         0x36 /* (2 bytes) */
 #define PCI_bridge_rom_base                                                    
0x38
-#define PCI_bridge_control                                                     
0x3E
+#define PCI_bridge_control                                                     
0x3E /* (2 bytes) */
 
+
 /* PCI type 2 header offsets */
-#define PCI_capabilities_ptr_2                                         0x14
-#define PCI_secondary_status_2                                         0x16
-#define PCI_primary_bus_2                                                      
0x18
-#define PCI_secondary_bus_2                                                    
0x19
-#define PCI_subordinate_bus_2                                          0x1A
-#define PCI_secondary_latency_2                                                
0x1B
-#define PCI_memory_base0_2                                                     
0x1C
-#define PCI_memory_limit0_2                                                    
0x20
-#define PCI_memory_base1_2                                                     
0x24
-#define PCI_memory_limit1_2                                                    
0x28
-#define PCI_io_base0_2                                                         
0x2C
-#define PCI_io_limit0_2                                                        
        0x30
-#define PCI_io_base1_2                                                         
0x34
-#define PCI_io_limit1_2                                                        
        0x38
-#define PCI_bridge_control_2                                           0x3E
-#define PCI_sub_vendor_id_2                                                    
0x40
-#define PCI_sub_device_id_2                                                    
0x42
-#define PCI_card_interface_2                                           0x44
+#define PCI_capabilities_ptr_2                      0x14 /* (1 byte) */
+#define PCI_secondary_status_2                      0x16 /* (2 bytes) */
+#define PCI_primary_bus_2                                                      
0x18 /* (1 byte) */
+#define PCI_secondary_bus_2                                                    
0x19 /* (1 byte) */
+#define PCI_subordinate_bus_2                                          0x1A /* 
(1 byte) */
+#define PCI_secondary_latency_2                     0x1B /* (1 byte) latency 
of secondary bus */
+#define PCI_memory_base0_2                          0x1C /* (4 bytes) */
+#define PCI_memory_limit0_2                         0x20 /* (4 bytes) */
+#define PCI_memory_base1_2                          0x24 /* (4 bytes) */
+#define PCI_memory_limit1_2                         0x28 /* (4 bytes) */
+#define PCI_io_base0_2                              0x2c /* (4 bytes) */
+#define PCI_io_limit0_2                             0x30 /* (4 bytes) */
+#define PCI_io_base1_2                              0x34 /* (4 bytes) */
+#define PCI_io_limit1_2                             0x38 /* (4 bytes) */
+#define PCI_bridge_control_2                        0x3E /* (2 bytes) */
 
+#define PCI_sub_vendor_id_2                         0x40 /* (2 bytes) */
+#define PCI_sub_device_id_2                         0x42 /* (2 bytes) */
 
-/* values for the class_base field in the common header */
-#define PCI_early                                              0x00
-#define PCI_mass_storage                               0x01
-#define PCI_network                                            0x02
-#define PCI_display                                            0x03
-#define PCI_multimedia                                 0x04
-#define PCI_memory                                             0x05
-#define PCI_bridge                                             0x06
-#define PCI_simple_communications              0x07
-#define PCI_base_peripheral                            0x08
-#define PCI_input                                              0x09
-#define PCI_docking_station                            0x0A
-#define PCI_processor                                  0x0B
-#define PCI_serial_bus                                 0x0C
-#define PCI_wireless                                   0x0D
-#define PCI_intelligent_io                             0x0E
-#define PCI_satellite_communications   0x0F
-#define PCI_encryption_decryption              0x10
-#define PCI_data_acquisition                   0x11
-#define PCI_undefined                                  0xFF
+#define PCI_card_interface_2                        0x44 /* ?? */
 
-/* values for the class_sub field for class_base = 0x00 (early) */
-#define PCI_early_not_vga              0x00
-#define PCI_early_vga                  0x01
+/* ---
+       values for the class_base field in the common header
+--- */
 
-/* values for the class_sub field for class_base = 0x01 (mass storage) */
-#define PCI_scsi                               0x00
-#define PCI_ide                                        0x01
-#define PCI_floppy                             0x02
-#define PCI_ipi                                        0x03
-#define PCI_raid                               0x04
-#define PCI_ata                                        0x05
-#define PCI_sata                               0x06
-#define PCI_sas                                        0x07
-#define PCI_mass_storage_other 0x80
+#define PCI_early                                      0x00    /* built before 
class codes defined */
+#define PCI_mass_storage                       0x01    /* mass 
storage_controller */
+#define PCI_network                                    0x02    /* network 
controller */
+#define PCI_display                                    0x03    /* display 
controller */
+#define PCI_multimedia                         0x04    /* multimedia device */
+#define PCI_memory                                     0x05    /* memory 
controller */
+#define PCI_bridge                                     0x06    /* bridge 
controller */
+#define PCI_simple_communications      0x07    /* simple communications 
controller */
+#define PCI_base_peripheral                    0x08    /* base system 
peripherals */
+#define PCI_input                                      0x09    /* input 
devices */
+#define PCI_docking_station                    0x0a    /* docking stations */
+#define PCI_processor                          0x0b    /* processors */
+#define PCI_serial_bus                         0x0c    /* serial bus 
controllers */
+#define PCI_wireless                           0x0d    /* wireless controllers 
*/
+#define PCI_intelligent_io                     0x0e
+#define PCI_satellite_communications 0x0f
+#define PCI_encryption_decryption      0x10
+#define PCI_data_acquisition           0x11
 
-/* values of the class_api field for class_base = 0x01, class_sub = 0x06 */
-#define PCI_sata_other                 0x00
-#define PCI_sata_ahci                  0x01
+#define PCI_undefined                          0xFF    /* not in any defined 
class */
 
-/* values for the class_sub field for class_base = 0x02 (network) */
-#define PCI_ethernet                   0x00
-#define PCI_token_ring                 0x01
-#define PCI_fddi                               0x02
-#define PCI_atm                                        0x03
-#define PCI_isdn                               0x04
-#define PCI_network_other              0x80
 
-/* values for the class_sub field for class_base = 0x03 (display) */
-#define PCI_vga                                        0x00
-#define PCI_xga                                        0x01
-#define PCI_3d                                 0x02
-#define PCI_display_other              0x80
+/* ---
+       values for the class_sub field for class_base = 0x00 (built before
+       class codes were defined)
+--- */
 
-/* values for the class_sub field for class_base = 0x04 (multimedia device) */
-#define PCI_video                              0x00
-#define PCI_audio                              0x01
-#define PCI_telephony                  0x02
-#define PCI_hd_audio                   0x03
-#define PCI_multimedia_other   0x80
+#define PCI_early_not_vga      0x00                    /* all except vga */
+#define PCI_early_vga          0x01                    /* vga devices */
 
-/* values for the class_sub field for class_base = 0x05 (memory) */
-#define PCI_ram                                        0x00
-#define PCI_flash                              0x01
-#define PCI_memory_other               0x80
 
-/* values for the class_sub field for class_base = 0x06 (bridge) */
-#define PCI_host                               0x00
-#define PCI_isa                                        0x01
-#define PCI_eisa                               0x02
-#define PCI_microchannel               0x03
-#define PCI_pci                                        0x04
-#define PCI_pcmcia                             0x05
-#define PCI_nubus                              0x06
-#define PCI_cardbus                            0x07
-#define PCI_raceway                            0x08
-#define PCI_bridge_transparent 0x09
-#define PCI_bridge_infiniband  0x0A
-#define PCI_bridge_other               0x80
+/* ---
+       values for the class_sub field for class_base = 0x01 (mass storage)
+--- */
 
-/* values for the class_sub field for class_base = 0x07 (simple        comm 
ctrlers) */
-#define PCI_serial                                             0x00
-#define PCI_parallel                                   0x01
-#define PCI_multiport_serial                   0x02
-#define PCI_modem                                              0x03
-#define PCI_simple_communications_other        0x80
+#define PCI_scsi                       0x00                    /* SCSI 
controller */
+#define PCI_ide                                0x01                    /* IDE 
controller */
+#define PCI_floppy                     0x02                    /* floppy disk 
controller */
+#define PCI_ipi                                0x03                    /* IPI 
bus controller */
+#define PCI_raid                       0x04                    /* RAID 
controller */
+#define PCI_ata                                0x05                    /* ATA 
controller with ADMA interface */
+#define PCI_sata                       0x06                    /* Serial ATA 
controller */
+#define PCI_sas                                0x07                    /* 
Serial Attached SCSI controller */
+#define PCI_mass_storage_other 0x80                    /* other mass storage 
controller */
 
-/* values of the class_api field for class_base = 0x07 and class_sub = 0x00 */
-#define PCI_serial_xt                  0x00
-#define PCI_serial_16450               0x01
-#define PCI_serial_16550               0x02
+/* ---
+       values of the class_api field for
+               class_base      = 0x01 (mass storage)
+               class_sub       = 0x06 (Serial ATA controller)
+--- */
 
-/* values of the class_api field for class_base = 0x07 and class_sub = 0x01 */
-#define PCI_parallel_simple                    0x00
-#define PCI_parallel_bidirectional     0x01
-#define PCI_parallel_ecp                       0x02
+#define PCI_sata_other                 0x00    /* vendor specific interface */
+#define PCI_sata_ahci                  0x01    /* AHCI interface */
 
 
-/* values for the class_sub field for class_base = 0x08 (system peripherals) */
-#define PCI_pic                                                0x00
-#define PCI_dma                                                0x01
-#define PCI_timer                                      0x02
-#define PCI_rtc                                                0x03
-#define PCI_generic_hot_plug           0x04
-#define PCI_system_peripheral_other    0x80
+/* ---
+       values for the class_sub field for class_base = 0x02 (network)
+--- */
 
-/* values of the class_api field for class_base = 0x08 and class_sub = 0x00 */
-#define PCI_pic_8259                   0x00
-#define PCI_pic_isa                            0x01
-#define PCI_pic_eisa                   0x02
+#define PCI_ethernet           0x00                    /* Ethernet controller 
*/
+#define PCI_token_ring         0x01                    /* Token Ring 
controller */
+#define PCI_fddi                       0x02                    /* FDDI 
controller */
+#define PCI_atm                                0x03                    /* ATM 
controller */
+#define PCI_isdn            0x04            /* ISDN controller */
+#define PCI_network_other      0x80                    /* other network 
controller */
 
-/* values of the class_api field for class_base = 0x08 and class_sub = 0x01 */
-#define PCI_dma_8237                   0x00
-#define PCI_dma_isa                            0x01
-#define PCI_dma_eisa                   0x02
 
-/* values of the class_api field for class_base = 0x08 and class_sub = 0x02 */
-#define PCI_timer_8254                 0x00
-#define PCI_timer_isa                  0x01
-#define PCI_timer_eisa                 0x02
+/* ---
+       values for the class_sub field for class_base = 0x03 (display)
+--- */
 
-/* values of the class_api field for class_base = 0x08 and class_sub = 0x03 */
-#define PCI_rtc_generic                        0x00
-#define PCI_rtc_isa                            0x01
+#define PCI_vga                                0x00                    /* VGA 
controller */
+#define PCI_xga                                0x01                    /* XGA 
controller */
+#define PCI_3d              0x02            /* 3d controller */
+#define PCI_display_other      0x80                    /* other display 
controller */
 
-/* values for the class_sub field for class_base = 0x09 (input devices) */
-#define PCI_keyboard                   0x00
-#define PCI_pen                                        0x01
-#define PCI_mouse                              0x02
-#define PCI_scanner                            0x03
-#define PCI_gameport                   0x04
-#define PCI_input_other                        0x80
 
-/* values for the class_sub field for class_base = 0x0A (docking stations) */
-#define PCI_docking_generic            0x00
-#define PCI_docking_other              0x80
+/* ---
+       values for the class_sub field for class_base = 0x04 (multimedia device)
+--- */
 
-/* values for the class_sub field for class_base = 0x0B (processor) */
-#define PCI_386                                0x00
-#define PCI_486                                0x01
-#define PCI_pentium                    0x02
-#define PCI_alpha                      0x10
-#define PCI_PowerPC                    0x20
-#define PCI_mips                       0x30
-#define PCI_coprocessor                0x40
+#define PCI_video                              0x00            /* video */
+#define PCI_audio                              0x01            /* audio */
+#define PCI_telephony                  0x02            /* computer telephony 
device */
+#define PCI_hd_audio                   0x03            /* HD audio */
+#define PCI_multimedia_other   0x80            /* other multimedia device */
 
-/* values for the class_sub field for class_base = 0x0C (serial bus ctrlr) */
-#define PCI_firewire           0x00
-#define PCI_access                     0x01
-#define PCI_ssa                                0x02
-#define PCI_usb                                0x03
-#define PCI_fibre_channel      0x04
+
+/* ---
+       values for the class_sub field for class_base = 0x05 (memory)
+--- */
+
+#define PCI_ram                                0x00                    /* RAM 
*/
+#define PCI_flash                      0x01                    /* flash */
+#define PCI_memory_other       0x80                    /* other memory 
controller */
+
+
+/* ---
+       values for the class_sub field for class_base = 0x06 (bridge)
+--- */
+
+#define PCI_host                       0x00                    /* host bridge 
*/
+#define PCI_isa                                0x01                    /* ISA 
bridge */
+#define PCI_eisa                       0x02                    /* EISA bridge 
*/
+#define PCI_microchannel       0x03                    /* MicroChannel bridge 
*/
+#define PCI_pci                                0x04                    /* 
PCI-to-PCI bridge */
+#define PCI_pcmcia                     0x05                    /* PCMCIA 
bridge */
+#define PCI_nubus                      0x06                    /* NuBus bridge 
*/
+#define PCI_cardbus                    0x07                    /* CardBus 
bridge */
+#define PCI_raceway                    0x08                    /* RACEway 
bridge */
+#define PCI_bridge_transparent         0x09                    /* PCI 
transparent */
+#define PCI_bridge_infiniband          0x0a                    /* Infiniband */
+#define PCI_bridge_other               0x80                    /* other bridge 
device */
+
+
+/* ---
+       values for the class_sub field for class_base = 0x07 (simple
+       communications controllers)
+--- */
+
+#define PCI_serial                                             0x00    /* 
serial port controller */
+#define PCI_parallel                                   0x01    /* parallel 
port */
+#define PCI_multiport_serial            0x02    /* multiport serial controller 
*/
+#define PCI_modem                       0x03    /* modem */
+#define PCI_simple_communications_other        0x80    /* other communications 
device */
+
+/* ---
+       values of the class_api field for
+               class_base      = 0x07 (simple communications), and
+               class_sub       = 0x00 (serial port controller)
+--- */
+
+#define PCI_serial_xt          0x00                    /* XT-compatible serial 
controller */
+#define PCI_serial_16450       0x01                    /* 16450-compatible 
serial controller */
+#define PCI_serial_16550       0x02                    /* 16550-compatible 
serial controller */
+
+
+/* ---
+       values of the class_api field for
+               class_base      = 0x07 (simple communications), and
+               class_sub       = 0x01 (parallel port)
+--- */
+
+#define PCI_parallel_simple                    0x00    /* simple (output-only) 
parallel port */
+#define PCI_parallel_bidirectional     0x01    /* bidirectional parallel port 
*/
+#define PCI_parallel_ecp                       0x02    /* ECP 1.x compliant 
parallel port */
+
+
+/* ---
+       values for the class_sub field for class_base = 0x08 (generic
+       system peripherals)
+--- */
+
+#define PCI_pic                                                0x00    /* 
peripheral interrupt controller */
+#define PCI_dma                                                0x01    /* dma 
controller */
+#define PCI_timer                                      0x02    /* timers */
+#define PCI_rtc                                                0x03    /* real 
time clock */
+#define PCI_generic_hot_plug        0x04    /* generic PCI hot-plug controller 
*/
+#define PCI_system_peripheral_other    0x80    /* other generic system 
peripheral */
+
+/* ---
+       values of the class_api field for
+               class_base      = 0x08 (generic system peripherals)
+               class_sub       = 0x00 (peripheral interrupt controller)
+--- */
+
+#define PCI_pic_8259                   0x00    /* generic 8259 */
+#define PCI_pic_isa                            0x01    /* ISA pic */
+#define PCI_pic_eisa                   0x02    /* EISA pic */
+
+/* ---
+       values of the class_api field for
+               class_base      = 0x08 (generic system peripherals)
+               class_sub       = 0x01 (dma controller)
+--- */
+
+#define PCI_dma_8237                   0x00    /* generic 8237 */
+#define PCI_dma_isa                            0x01    /* ISA dma */
+#define PCI_dma_eisa                   0x02    /* EISA dma */
+
+/* ---
+       values of the class_api field for
+               class_base      = 0x08 (generic system peripherals)
+               class_sub       = 0x02 (timer)
+--- */
+
+#define PCI_timer_8254                 0x00    /* generic 8254 */
+#define PCI_timer_isa                  0x01    /* ISA timer */
+#define PCI_timer_eisa                 0x02    /* EISA timers (2 timers) */
+
+
+/* ---
+       values of the class_api field for
+               class_base      = 0x08 (generic system peripherals)
+               class_sub       = 0x03 (real time clock
+--- */
+
+#define PCI_rtc_generic                        0x00    /* generic real time 
clock */
+#define PCI_rtc_isa                            0x01    /* ISA real time clock 
*/
+
+
+/* ---
+       values for the class_sub field for class_base = 0x09 (input devices)
+--- */
+
+#define PCI_keyboard                   0x00    /* keyboard controller */
+#define PCI_pen                                        0x01    /* pen */
+#define PCI_mouse                              0x02    /* mouse controller */
+#define PCI_scanner             0x03    /* scanner controller */
+#define PCI_gameport            0x04    /* gameport controller */
+#define PCI_input_other                        0x80    /* other input 
controller */
+
+
+/* ---
+       values for the class_sub field for class_base = 0x0a (docking stations)
+--- */
+
+#define PCI_docking_generic            0x00    /* generic docking station */
+#define PCI_docking_other              0x80    /* other docking stations */
+
+/* ---
+       values for the class_sub field for class_base = 0x0b (processor)
+--- */
+
+#define PCI_386                                        0x00    /* 386 */
+#define PCI_486                                        0x01    /* 486 */
+#define PCI_pentium                            0x02    /* Pentium */
+#define PCI_alpha                              0x10    /* Alpha */
+#define PCI_PowerPC                            0x20    /* PowerPC */
+#define PCI_mips                0x30    /* MIPS */
+#define PCI_coprocessor                        0x40    /* co-processor */
+
+/* ---
+       values for the class_sub field for class_base = 0x0c (serial bus
+       controller)
+--- */
+
+#define PCI_firewire                   0x00    /* FireWire (IEEE 1394) */
+#define PCI_access                             0x01    /* ACCESS bus */
+#define PCI_ssa                                        0x02    /* SSA */
+#define PCI_usb                                        0x03    /* Universal 
Serial Bus */
+#define PCI_fibre_channel              0x04    /* Fibre channel */
 #define PCI_smbus                      0x05
-#define PCI_infiniband         0x06
+#define PCI_infiniband                 0x06
 #define PCI_ipmi                       0x07
 #define PCI_sercos                     0x08
 #define PCI_canbus                     0x09
 
-/* values of the class_api field for class_base = 0x0C and class_sub = 0x03 */
-#define PCI_usb_uhci           0x00
-#define PCI_usb_ohci           0x10
-#define PCI_usb_ehci           0x20
-#define PCI_usb_xhci           0x30    /* Extensible Host Controller Interface 
*/
+/* ---
+       values of the class_api field for
+               class_base      = 0x0c ( serial bus controller )
+               class_sub       = 0x03 ( Universal Serial Bus  )
+--- */
 
-/* values for the class_sub field for class_base = 0x0d (wireless controller) 
*/
+#define PCI_usb_uhci                   0x00    /* Universal Host Controller 
Interface */
+#define PCI_usb_ohci                   0x10    /* Open Host Controller 
Interface */
+#define PCI_usb_ehci                   0x20    /* Enhanced Host Controller 
Interface */
+#define PCI_usb_xhci                   0x30    /* Extensible Host Controller 
Interface */
+
+/* ---
+       values for the class_sub field for class_base = 0x0d (wireless 
controller)
+--- */
 #define PCI_wireless_irda                      0x00
-#define PCI_wireless_consumer_ir       0x01
+#define PCI_wireless_consumer_ir               0x01
 #define PCI_wireless_rf                                0x02
-#define PCI_wireless_bluetooth         0x03
-#define PCI_wireless_broadband         0x04
+#define PCI_wireless_bluetooth                 0x03
+#define PCI_wireless_broadband                 0x04
 #define PCI_wireless_80211A                    0x10
 #define PCI_wireless_80211B                    0x20
 #define PCI_wireless_other                     0x80
 
+/* ---
+       masks for command register bits
+--- */
 
-/* masks for command register bits */
-#define PCI_command_io                         0x001
-#define PCI_command_memory                     0x002
-#define PCI_command_master                     0x004
-#define PCI_command_special                    0x008
-#define PCI_command_mwi                                0x010
-#define PCI_command_vga_snoop          0x020
-#define PCI_command_parity                     0x040
-#define PCI_command_address_step       0x080
-#define PCI_command_serr                       0x100
-#define PCI_command_fastback           0x200
-#define PCI_command_int_disable                0x400
+#define PCI_command_io                         0x001           /* 1/0 i/o 
space en/disabled */
+#define PCI_command_memory                     0x002           /* 1/0 memory 
space en/disabled */
+#define PCI_command_master                     0x004           /* 1/0 pci 
master en/disabled */
+#define PCI_command_special                    0x008           /* 1/0 pci 
special cycles en/disabled */
+#define PCI_command_mwi                                0x010           /* 1/0 
memory write & invalidate en/disabled */
+#define PCI_command_vga_snoop          0x020           /* 1/0 vga pallette 
snoop en/disabled */
+#define PCI_command_parity                     0x040           /* 1/0 parity 
check en/disabled */
+#define PCI_command_address_step       0x080           /* 1/0 address stepping 
en/disabled */
+#define PCI_command_serr                       0x100           /* 1/0 SERR# 
en/disabled */
+#define PCI_command_fastback           0x200           /* 1/0 fast 
back-to-back en/disabled */
+#define PCI_command_int_disable                0x400           /* 1/0 
interrupt generation dis/enabled */
 
 
-/* masks for status register bits */
-#define PCI_status_capabilities                                0x0010
-#define PCI_status_66_MHz_capable                      0x0020
-#define PCI_status_udf_supported                       0x0040
-#define PCI_status_fastback                                    0x0080
-#define PCI_status_parity_signalled                    0x0100
-#define PCI_status_devsel                                      0x0600
-#define PCI_status_target_abort_signalled      0x0800
-#define PCI_status_target_abort_received       0x1000
-#define PCI_status_master_abort_received       0x2000
-#define PCI_status_serr_signalled                      0x4000
-#define PCI_status_parity_error_detected       0x8000
+/* ---
+       masks for status register bits
+--- */
 
+#define PCI_status_capabilities             0x0010  /* capabilities list */
+#define PCI_status_66_MHz_capable                      0x0020  /* 66 Mhz 
capable */
+#define PCI_status_udf_supported                       0x0040  /* 
user-definable-features (udf) supported */
+#define PCI_status_fastback                                    0x0080  /* fast 
back-to-back capable */
+#define PCI_status_parity_signalled                0x0100      /* parity error 
signalled */
+#define PCI_status_devsel                                      0x0600  /* 
devsel timing (see below) */
+#define PCI_status_target_abort_signalled      0x0800  /* signaled a target 
abort */
+#define PCI_status_target_abort_received       0x1000  /* received a target 
abort */
+#define PCI_status_master_abort_received       0x2000  /* received a master 
abort */

[... truncated: 214 lines follow ...]

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