[haiku-commits] r41411 - in haiku/trunk: build/jam headers/private/graphics/radeon_hd src/add-ons/accelerants/radeon_hd src/add-ons/kernel/drivers/graphics/radeon_hd

  • From: kallisti5@xxxxxxxxxxx
  • To: haiku-commits@xxxxxxxxxxxxx
  • Date: Tue, 10 May 2011 04:02:41 +0200 (CEST)

Author: kallisti5
Date: 2011-05-10 04:02:41 +0200 (Tue, 10 May 2011)
New Revision: 41411
Changeset: https://dev.haiku-os.org/changeset/41411

Added:
   haiku/trunk/headers/private/graphics/radeon_hd/r600_reg.h
   haiku/trunk/headers/private/graphics/radeon_hd/r600_reg_auto_r6xx.h
   haiku/trunk/headers/private/graphics/radeon_hd/r600_reg_r6xx.h
   haiku/trunk/headers/private/graphics/radeon_hd/r600_reg_r7xx.h
   haiku/trunk/headers/private/graphics/radeon_hd/rhd_regs.h
Modified:
   haiku/trunk/build/jam/HaikuImage
   haiku/trunk/headers/private/graphics/radeon_hd/radeon_hd.h
   haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
   haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.h
   haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
Log:
* add commented out radeon_hd driver/accel to HaikuImage
* add boot item support to radeon hd driver
* add edid storage to shared info
* add pull of active monitor VESA EDID to radeon hd driver (until AtomBios 
complete)
* EDID pulled in driver now passed to create_display_modes
* move registers to external stock xorg radeon hd register headers (lic. allows 
it)


Modified: haiku/trunk/build/jam/HaikuImage
===================================================================
--- haiku/trunk/build/jam/HaikuImage    2011-05-09 23:08:35 UTC (rev 41410)
+++ haiku/trunk/build/jam/HaikuImage    2011-05-10 02:02:41 UTC (rev 41411)
@@ -118,6 +118,7 @@
        $(X86_ONLY)s3.accelerant $(X86_ONLY)vesa.accelerant
        $(X86_ONLY)ati.accelerant
        $(X86_ONLY)3dfx.accelerant
+       #$(X86_ONLY)radeon_hd.accelerant
        #$(X86_ONLY)via.accelerant
        #$(X86_ONLY)vmware.accelerant
 ;
@@ -162,7 +163,7 @@
 SYSTEM_ADD_ONS_DRIVERS_GRAPHICS = $(X86_ONLY)radeon $(X86_ONLY)nvidia
        $(X86_ONLY)neomagic $(X86_ONLY)matrox $(X86_ONLY)intel_extreme
        $(X86_ONLY)s3 $(X86_ONLY)vesa #$(X86_ONLY)via #$(X86_ONLY)vmware
-       $(X86_ONLY)ati $(X86_ONLY)3dfx
+       $(X86_ONLY)ati $(X86_ONLY)3dfx #$(X86_ONLY)radeon_hd
 ;
 SYSTEM_ADD_ONS_DRIVERS_MIDI = emuxki usb_midi ;
 SYSTEM_ADD_ONS_DRIVERS_NET = $(X86_ONLY)3com $(X86_ONLY)atheros813x

Added: haiku/trunk/headers/private/graphics/radeon_hd/r600_reg.h
===================================================================
--- haiku/trunk/headers/private/graphics/radeon_hd/r600_reg.h                   
        (rev 0)
+++ haiku/trunk/headers/private/graphics/radeon_hd/r600_reg.h   2011-05-10 
02:02:41 UTC (rev 41411)
@@ -0,0 +1,132 @@
+/*
+ * RadeonHD R6xx, R7xx Register documentation
+ *
+ * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2009  Matthias Hopf
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _R600_REG_H_
+#define _R600_REG_H_
+
+/*
+ * Register definitions
+ */
+
+#include "r600_reg_auto_r6xx.h"
+#include "r600_reg_r6xx.h"
+#include "r600_reg_r7xx.h"
+
+
+/* SET_*_REG offsets + ends */
+enum {
+    SET_CONFIG_REG_offset          = 0x00008000,
+    SET_CONFIG_REG_end             = 0x0000ac00,
+    SET_CONTEXT_REG_offset         = 0x00028000,
+    SET_CONTEXT_REG_end            = 0x00029000,
+    SET_ALU_CONST_offset           = 0x00030000,
+    SET_ALU_CONST_end              = 0x00032000,
+    SET_RESOURCE_offset            = 0x00038000,
+    SET_RESOURCE_end               = 0x0003c000,
+    SET_SAMPLER_offset             = 0x0003c000,
+    SET_SAMPLER_end                = 0x0003cff0,
+    SET_CTL_CONST_offset           = 0x0003cff0,
+    SET_CTL_CONST_end              = 0x0003e200,
+    SET_LOOP_CONST_offset          = 0x0003e200,
+    SET_LOOP_CONST_end             = 0x0003e380,
+    SET_BOOL_CONST_offset          = 0x0003e380,
+    SET_BOOL_CONST_end             = 0x0003e38c
+};
+
+/* packet3 IT_SURFACE_BASE_UPDATE bits */
+enum {
+       DEPTH_BASE    = (1 << 0),
+       COLOR0_BASE   = (1 << 1),
+       COLOR1_BASE   = (1 << 2),
+       COLOR2_BASE   = (1 << 3),
+       COLOR3_BASE   = (1 << 4),
+       COLOR4_BASE   = (1 << 5),
+       COLOR5_BASE   = (1 << 6),
+       COLOR6_BASE   = (1 << 7),
+       COLOR7_BASE   = (1 << 8),
+       STRMOUT_BASE0 = (1 << 9),
+       STRMOUT_BASE1 = (1 << 10),
+       STRMOUT_BASE2 = (1 << 11),
+       STRMOUT_BASE3 = (1 << 12),
+       COHER_BASE0   = (1 << 13),
+       COHER_BASE1   = (1 << 14)
+};
+
+/* packet3 IT_WAIT_REG_MEM operation encoding */
+enum {
+       WAIT_ALWAYS = (0<<0),
+       WAIT_LT     = (1<<0),
+       WAIT_LE     = (2<<0),
+       WAIT_EQ     = (3<<0),
+       WAIT_NE     = (4<<0),
+       WAIT_GE     = (5<<0),
+       WAIT_GT     = (6<<0),
+
+       WAIT_REG    = (0<<4),
+       WAIT_MEM    = (1<<4)
+};
+
+/* Packet3 commands */
+enum {
+    IT_NOP                               = 0x10,
+    IT_INDIRECT_BUFFER_END               = 0x17,
+    IT_SET_PREDICATION                   = 0x20,
+    IT_REG_RMW                           = 0x21,
+    IT_COND_EXEC                         = 0x22,
+    IT_PRED_EXEC                         = 0x23,
+    IT_START_3D_CMDBUF                   = 0x24,
+    IT_DRAW_INDEX_2                      = 0x27,
+    IT_CONTEXT_CONTROL                   = 0x28,
+    IT_DRAW_INDEX_IMMD_BE                = 0x29,
+    IT_INDEX_TYPE                        = 0x2A,
+    IT_DRAW_INDEX                        = 0x2B,
+    IT_DRAW_INDEX_AUTO                   = 0x2D,
+    IT_DRAW_INDEX_IMMD                   = 0x2E,
+    IT_NUM_INSTANCES                     = 0x2F,
+    IT_STRMOUT_BUFFER_UPDATE             = 0x34,
+    IT_INDIRECT_BUFFER_MP                = 0x38,
+    IT_MEM_SEMAPHORE                     = 0x39,
+    IT_MPEG_INDEX                        = 0x3A,
+    IT_WAIT_REG_MEM                      = 0x3C,
+    IT_MEM_WRITE                         = 0x3D,
+    IT_INDIRECT_BUFFER                   = 0x32,
+    IT_CP_INTERRUPT                      = 0x40,
+    IT_SURFACE_SYNC                      = 0x43,
+    IT_ME_INITIALIZE                     = 0x44,
+    IT_COND_WRITE                        = 0x45,
+    IT_EVENT_WRITE                       = 0x46,
+    IT_EVENT_WRITE_EOP                   = 0x47,
+    IT_ONE_REG_WRITE                     = 0x57,
+    IT_SET_CONFIG_REG                    = 0x68,
+    IT_SET_CONTEXT_REG                   = 0x69,
+    IT_SET_ALU_CONST                     = 0x6A,
+    IT_SET_BOOL_CONST                    = 0x6B,
+    IT_SET_LOOP_CONST                    = 0x6C,
+    IT_SET_RESOURCE                      = 0x6D,
+    IT_SET_SAMPLER                       = 0x6E,
+    IT_SET_CTL_CONST                     = 0x6F,
+    IT_SURFACE_BASE_UPDATE               = 0x73
+};
+
+#endif

Added: haiku/trunk/headers/private/graphics/radeon_hd/r600_reg_auto_r6xx.h
===================================================================
--- haiku/trunk/headers/private/graphics/radeon_hd/r600_reg_auto_r6xx.h         
                (rev 0)
+++ haiku/trunk/headers/private/graphics/radeon_hd/r600_reg_auto_r6xx.h 
2011-05-10 02:02:41 UTC (rev 41411)
@@ -0,0 +1,3087 @@
+/*
+ * RadeonHD R6xx, R7xx Register documentation
+ *
+ * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2009  Matthias Hopf
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _AUTOREGS
+#define _AUTOREGS
+
+enum {
+
+    VGT_VTX_VECT_EJECT_REG                                = 0x000088b0,
+       PRIM_COUNT_mask                                   = 0x3ff << 0,
+       PRIM_COUNT_shift                                  = 0,
+    VGT_LAST_COPY_STATE                                   = 0x000088c0,
+       SRC_STATE_ID_mask                                 = 0x07 << 0,
+       SRC_STATE_ID_shift                                = 0,
+       DST_STATE_ID_mask                                 = 0x07 << 16,
+       DST_STATE_ID_shift                                = 16,
+    VGT_CACHE_INVALIDATION                                = 0x000088c4,
+       CACHE_INVALIDATION_mask                           = 0x03 << 0,
+       CACHE_INVALIDATION_shift                          = 0,
+           VC_ONLY                                       = 0x00,
+           TC_ONLY                                       = 0x01,
+           VC_AND_TC                                     = 0x02,
+       VS_NO_EXTRA_BUFFER_bit                            = 1 << 5,
+    VGT_GS_PER_ES                                         = 0x000088c8,
+    VGT_ES_PER_GS                                         = 0x000088cc,
+    VGT_GS_VERTEX_REUSE                                   = 0x000088d4,
+       VERT_REUSE_mask                                   = 0x1f << 0,
+       VERT_REUSE_shift                                  = 0,
+    VGT_MC_LAT_CNTL                                       = 0x000088d8,
+       MC_TIME_STAMP_RES_mask                            = 0x03 << 0,
+       MC_TIME_STAMP_RES_shift                           = 0,
+           X_0_992_MAX_LATENCY                           = 0x00,
+           X_0_496_MAX_LATENCY                           = 0x01,
+           X_0_248_MAX_LATENCY                           = 0x02,
+           X_0_124_MAX_LATENCY                           = 0x03,
+    VGT_GS_PER_VS                                         = 0x000088e8,
+       GS_PER_VS_mask                                    = 0x0f << 0,
+       GS_PER_VS_shift                                   = 0,
+    VGT_CNTL_STATUS                                       = 0x000088f0,
+       VGT_OUT_INDX_BUSY_bit                             = 1 << 0,
+       VGT_OUT_BUSY_bit                                  = 1 << 1,
+       VGT_PT_BUSY_bit                                   = 1 << 2,
+       VGT_TE_BUSY_bit                                   = 1 << 3,
+       VGT_VR_BUSY_bit                                   = 1 << 4,
+       VGT_GRP_BUSY_bit                                  = 1 << 5,
+       VGT_DMA_REQ_BUSY_bit                              = 1 << 6,
+       VGT_DMA_BUSY_bit                                  = 1 << 7,
+       VGT_GS_BUSY_bit                                   = 1 << 8,
+       VGT_BUSY_bit                                      = 1 << 9,
+    VGT_PRIMITIVE_TYPE                                    = 0x00008958,
+       VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask                = 0x3f << 0,
+       VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift               = 0,
+           DI_PT_NONE                                    = 0x00,
+           DI_PT_POINTLIST                               = 0x01,
+           DI_PT_LINELIST                                = 0x02,
+           DI_PT_LINESTRIP                               = 0x03,
+           DI_PT_TRILIST                                 = 0x04,
+           DI_PT_TRIFAN                                  = 0x05,
+           DI_PT_TRISTRIP                                = 0x06,
+           DI_PT_UNUSED_0                                = 0x07,
+           DI_PT_UNUSED_1                                = 0x08,
+           DI_PT_UNUSED_2                                = 0x09,
+           DI_PT_LINELIST_ADJ                            = 0x0a,
+           DI_PT_LINESTRIP_ADJ                           = 0x0b,
+           DI_PT_TRILIST_ADJ                             = 0x0c,
+           DI_PT_TRISTRIP_ADJ                            = 0x0d,
+           DI_PT_UNUSED_3                                = 0x0e,
+           DI_PT_UNUSED_4                                = 0x0f,
+           DI_PT_TRI_WITH_WFLAGS                         = 0x10,
+           DI_PT_RECTLIST                                = 0x11,
+           DI_PT_LINELOOP                                = 0x12,
+           DI_PT_QUADLIST                                = 0x13,
+           DI_PT_QUADSTRIP                               = 0x14,
+           DI_PT_POLYGON                                 = 0x15,
+           DI_PT_2D_COPY_RECT_LIST_V0                    = 0x16,
+           DI_PT_2D_COPY_RECT_LIST_V1                    = 0x17,
+           DI_PT_2D_COPY_RECT_LIST_V2                    = 0x18,
+           DI_PT_2D_COPY_RECT_LIST_V3                    = 0x19,
+           DI_PT_2D_FILL_RECT_LIST                       = 0x1a,
+           DI_PT_2D_LINE_STRIP                           = 0x1b,
+           DI_PT_2D_TRI_STRIP                            = 0x1c,
+    VGT_INDEX_TYPE                                        = 0x0000895c,
+       INDEX_TYPE_mask                                   = 0x03 << 0,
+       INDEX_TYPE_shift                                  = 0,
+           DI_INDEX_SIZE_16_BIT                          = 0x00,
+           DI_INDEX_SIZE_32_BIT                          = 0x01,
+    VGT_STRMOUT_BUFFER_FILLED_SIZE_0                      = 0x00008960,
+    VGT_STRMOUT_BUFFER_FILLED_SIZE_1                      = 0x00008964,
+    VGT_STRMOUT_BUFFER_FILLED_SIZE_2                      = 0x00008968,
+    VGT_STRMOUT_BUFFER_FILLED_SIZE_3                      = 0x0000896c,
+    VGT_NUM_INDICES                                       = 0x00008970,
+    VGT_NUM_INSTANCES                                     = 0x00008974,
+    PA_CL_CNTL_STATUS                                     = 0x00008a10,
+       CL_BUSY_bit                                       = 1 << 31,
+    PA_CL_ENHANCE                                         = 0x00008a14,
+       CLIP_VTX_REORDER_ENA_bit                          = 1 << 0,
+       NUM_CLIP_SEQ_mask                                 = 0x03 << 1,
+       NUM_CLIP_SEQ_shift                                = 1,
+       CLIPPED_PRIM_SEQ_STALL_bit                        = 1 << 3,
+       VE_NAN_PROC_DISABLE_bit                           = 1 << 4,
+    PA_SU_CNTL_STATUS                                     = 0x00008a50,
+       SU_BUSY_bit                                       = 1 << 31,
+    PA_SC_LINE_STIPPLE_STATE                              = 0x00008b10,
+       CURRENT_PTR_mask                                  = 0x0f << 0,
+       CURRENT_PTR_shift                                 = 0,
+       CURRENT_COUNT_mask                                = 0xff << 8,
+       CURRENT_COUNT_shift                               = 8,
+    PA_SC_MULTI_CHIP_CNTL                                 = 0x00008b20,
+       LOG2_NUM_CHIPS_mask                               = 0x07 << 0,
+       LOG2_NUM_CHIPS_shift                              = 0,
+       MULTI_CHIP_TILE_SIZE_mask                         = 0x03 << 3,
+       MULTI_CHIP_TILE_SIZE_shift                        = 3,
+           X_16_X_16_PIXEL_TILE_PER_CHIP                 = 0x00,
+           X_32_X_32_PIXEL_TILE_PER_CHIP                 = 0x01,
+           X_64_X_64_PIXEL_TILE_PER_CHIP                 = 0x02,
+           X_128X128_PIXEL_TILE_PER_CHIP                 = 0x03,
+       CHIP_TILE_X_LOC_mask                              = 0x07 << 5,
+       CHIP_TILE_X_LOC_shift                             = 5,
+       CHIP_TILE_Y_LOC_mask                              = 0x07 << 8,
+       CHIP_TILE_Y_LOC_shift                             = 8,
+       CHIP_SUPER_TILE_B_bit                             = 1 << 11,
+    PA_SC_AA_SAMPLE_LOCS_2S                               = 0x00008b40,
+       S0_X_mask                                         = 0x0f << 0,
+       S0_X_shift                                        = 0,
+       S0_Y_mask                                         = 0x0f << 4,
+       S0_Y_shift                                        = 4,
+       S1_X_mask                                         = 0x0f << 8,
+       S1_X_shift                                        = 8,
+       S1_Y_mask                                         = 0x0f << 12,
+       S1_Y_shift                                        = 12,
+    PA_SC_AA_SAMPLE_LOCS_4S                               = 0x00008b44,
+/*     S0_X_mask                                         = 0x0f << 0, */
+/*     S0_X_shift                                        = 0, */
+/*     S0_Y_mask                                         = 0x0f << 4, */
+/*     S0_Y_shift                                        = 4, */
+/*     S1_X_mask                                         = 0x0f << 8, */
+/*     S1_X_shift                                        = 8, */
+/*     S1_Y_mask                                         = 0x0f << 12, */
+/*     S1_Y_shift                                        = 12, */
+       S2_X_mask                                         = 0x0f << 16,
+       S2_X_shift                                        = 16,
+       S2_Y_mask                                         = 0x0f << 20,
+       S2_Y_shift                                        = 20,
+       S3_X_mask                                         = 0x0f << 24,
+       S3_X_shift                                        = 24,
+       S3_Y_mask                                         = 0x0f << 28,
+       S3_Y_shift                                        = 28,
+    PA_SC_AA_SAMPLE_LOCS_8S_WD0                           = 0x00008b48,
+/*     S0_X_mask                                         = 0x0f << 0, */
+/*     S0_X_shift                                        = 0, */
+/*     S0_Y_mask                                         = 0x0f << 4, */
+/*     S0_Y_shift                                        = 4, */
+/*     S1_X_mask                                         = 0x0f << 8, */
+/*     S1_X_shift                                        = 8, */
+/*     S1_Y_mask                                         = 0x0f << 12, */
+/*     S1_Y_shift                                        = 12, */
+/*     S2_X_mask                                         = 0x0f << 16, */
+/*     S2_X_shift                                        = 16, */
+/*     S2_Y_mask                                         = 0x0f << 20, */
+/*     S2_Y_shift                                        = 20, */
+/*     S3_X_mask                                         = 0x0f << 24, */
+/*     S3_X_shift                                        = 24, */
+/*     S3_Y_mask                                         = 0x0f << 28, */
+/*     S3_Y_shift                                        = 28, */
+    PA_SC_AA_SAMPLE_LOCS_8S_WD1                           = 0x00008b4c,
+       S4_X_mask                                         = 0x0f << 0,
+       S4_X_shift                                        = 0,
+       S4_Y_mask                                         = 0x0f << 4,
+       S4_Y_shift                                        = 4,
+       S5_X_mask                                         = 0x0f << 8,
+       S5_X_shift                                        = 8,
+       S5_Y_mask                                         = 0x0f << 12,
+       S5_Y_shift                                        = 12,
+       S6_X_mask                                         = 0x0f << 16,
+       S6_X_shift                                        = 16,
+       S6_Y_mask                                         = 0x0f << 20,
+       S6_Y_shift                                        = 20,
+       S7_X_mask                                         = 0x0f << 24,
+       S7_X_shift                                        = 24,
+       S7_Y_mask                                         = 0x0f << 28,
+       S7_Y_shift                                        = 28,
+    PA_SC_CNTL_STATUS                                     = 0x00008be0,
+       MPASS_OVERFLOW_bit                                = 1 << 30,
+    PA_SC_ENHANCE                                         = 0x00008bf0,
+       FORCE_EOV_MAX_CLK_CNT_mask                        = 0xfff << 0,
+       FORCE_EOV_MAX_CLK_CNT_shift                       = 0,
+       FORCE_EOV_MAX_TILE_CNT_mask                       = 0xfff << 12,
+       FORCE_EOV_MAX_TILE_CNT_shift                      = 12,
+    SQ_CONFIG                                             = 0x00008c00,
+       VC_ENABLE_bit                                     = 1 << 0,
+       EXPORT_SRC_C_bit                                  = 1 << 1,
+       DX9_CONSTS_bit                                    = 1 << 2,
+       ALU_INST_PREFER_VECTOR_bit                        = 1 << 3,
+       SQ_CONFIG__DX10_CLAMP_bit                         = 1 << 4,
+       ALU_PREFER_ONE_WATERFALL_bit                      = 1 << 5,
+       ALU_MAX_ONE_WATERFALL_bit                         = 1 << 6,
+       CLAUSE_SEQ_PRIO_mask                              = 0x03 << 8,
+       CLAUSE_SEQ_PRIO_shift                             = 8,
+           SQ_CL_PRIO_RND_ROBIN                          = 0x00,
+           SQ_CL_PRIO_MACRO_SEQ                          = 0x01,
+           SQ_CL_PRIO_NONE                               = 0x02,
+       PS_PRIO_mask                                      = 0x03 << 24,
+       PS_PRIO_shift                                     = 24,
+       VS_PRIO_mask                                      = 0x03 << 26,
+       VS_PRIO_shift                                     = 26,
+       GS_PRIO_mask                                      = 0x03 << 28,
+       GS_PRIO_shift                                     = 28,
+       ES_PRIO_mask                                      = 0x03 << 30,
+       ES_PRIO_shift                                     = 30,
+    SQ_GPR_RESOURCE_MGMT_1                                = 0x00008c04,
+       NUM_PS_GPRS_mask                                  = 0xff << 0,
+       NUM_PS_GPRS_shift                                 = 0,
+       NUM_VS_GPRS_mask                                  = 0xff << 16,
+       NUM_VS_GPRS_shift                                 = 16,
+       NUM_CLAUSE_TEMP_GPRS_mask                         = 0x0f << 28,
+       NUM_CLAUSE_TEMP_GPRS_shift                        = 28,
+    SQ_GPR_RESOURCE_MGMT_2                                = 0x00008c08,
+       NUM_GS_GPRS_mask                                  = 0xff << 0,
+       NUM_GS_GPRS_shift                                 = 0,
+       NUM_ES_GPRS_mask                                  = 0xff << 16,
+       NUM_ES_GPRS_shift                                 = 16,
+    SQ_THREAD_RESOURCE_MGMT                               = 0x00008c0c,
+       NUM_PS_THREADS_mask                               = 0xff << 0,
+       NUM_PS_THREADS_shift                              = 0,
+       NUM_VS_THREADS_mask                               = 0xff << 8,
+       NUM_VS_THREADS_shift                              = 8,
+       NUM_GS_THREADS_mask                               = 0xff << 16,
+       NUM_GS_THREADS_shift                              = 16,
+       NUM_ES_THREADS_mask                               = 0xff << 24,
+       NUM_ES_THREADS_shift                              = 24,
+    SQ_STACK_RESOURCE_MGMT_1                              = 0x00008c10,
+       NUM_PS_STACK_ENTRIES_mask                         = 0xfff << 0,
+       NUM_PS_STACK_ENTRIES_shift                        = 0,
+       NUM_VS_STACK_ENTRIES_mask                         = 0xfff << 16,
+       NUM_VS_STACK_ENTRIES_shift                        = 16,
+    SQ_STACK_RESOURCE_MGMT_2                              = 0x00008c14,
+       NUM_GS_STACK_ENTRIES_mask                         = 0xfff << 0,
+       NUM_GS_STACK_ENTRIES_shift                        = 0,
+       NUM_ES_STACK_ENTRIES_mask                         = 0xfff << 16,
+       NUM_ES_STACK_ENTRIES_shift                        = 16,
+    SQ_ESGS_RING_BASE                                     = 0x00008c40,
+    SQ_ESGS_RING_SIZE                                     = 0x00008c44,
+    SQ_GSVS_RING_BASE                                     = 0x00008c48,
+    SQ_GSVS_RING_SIZE                                     = 0x00008c4c,
+    SQ_ESTMP_RING_BASE                                    = 0x00008c50,
+    SQ_ESTMP_RING_SIZE                                    = 0x00008c54,
+    SQ_GSTMP_RING_BASE                                    = 0x00008c58,
+    SQ_GSTMP_RING_SIZE                                    = 0x00008c5c,
+    SQ_VSTMP_RING_BASE                                    = 0x00008c60,
+    SQ_VSTMP_RING_SIZE                                    = 0x00008c64,
+    SQ_PSTMP_RING_BASE                                    = 0x00008c68,
+    SQ_PSTMP_RING_SIZE                                    = 0x00008c6c,
+    SQ_FBUF_RING_BASE                                     = 0x00008c70,
+    SQ_FBUF_RING_SIZE                                     = 0x00008c74,
+    SQ_REDUC_RING_BASE                                    = 0x00008c78,
+    SQ_REDUC_RING_SIZE                                    = 0x00008c7c,
+    SQ_ALU_WORD1_OP3                                      = 0x00008dfc,
+       SRC2_SEL_mask                                     = 0x1ff << 0,
+       SRC2_SEL_shift                                    = 0,
+           SQ_ALU_SRC_0                                  = 0xf8,
+           SQ_ALU_SRC_1                                  = 0xf9,
+           SQ_ALU_SRC_1_INT                              = 0xfa,
+           SQ_ALU_SRC_M_1_INT                            = 0xfb,
+           SQ_ALU_SRC_0_5                                = 0xfc,
+           SQ_ALU_SRC_LITERAL                            = 0xfd,
+           SQ_ALU_SRC_PV                                 = 0xfe,
+           SQ_ALU_SRC_PS                                 = 0xff,
+       SRC2_REL_bit                                      = 1 << 9,
+       SRC2_CHAN_mask                                    = 0x03 << 10,
+       SRC2_CHAN_shift                                   = 10,
+           SQ_CHAN_X                                     = 0x00,
+           SQ_CHAN_Y                                     = 0x01,
+           SQ_CHAN_Z                                     = 0x02,
+           SQ_CHAN_W                                     = 0x03,
+       SRC2_NEG_bit                                      = 1 << 12,
+       SQ_ALU_WORD1_OP3__ALU_INST_mask                   = 0x1f << 13,
+       SQ_ALU_WORD1_OP3__ALU_INST_shift                  = 13,
+           SQ_OP3_INST_MUL_LIT                           = 0x0c,
+           SQ_OP3_INST_MUL_LIT_M2                        = 0x0d,
+           SQ_OP3_INST_MUL_LIT_M4                        = 0x0e,
+           SQ_OP3_INST_MUL_LIT_D2                        = 0x0f,
+           SQ_OP3_INST_MULADD                            = 0x10,
+           SQ_OP3_INST_MULADD_M2                         = 0x11,
+           SQ_OP3_INST_MULADD_M4                         = 0x12,
+           SQ_OP3_INST_MULADD_D2                         = 0x13,
+           SQ_OP3_INST_MULADD_IEEE                       = 0x14,
+           SQ_OP3_INST_MULADD_IEEE_M2                    = 0x15,
+           SQ_OP3_INST_MULADD_IEEE_M4                    = 0x16,
+           SQ_OP3_INST_MULADD_IEEE_D2                    = 0x17,
+           SQ_OP3_INST_CNDE                              = 0x18,
+           SQ_OP3_INST_CNDGT                             = 0x19,
+           SQ_OP3_INST_CNDGE                             = 0x1a,
+           SQ_OP3_INST_CNDE_INT                          = 0x1c,
+           SQ_OP3_INST_CNDGT_INT                         = 0x1d,
+           SQ_OP3_INST_CNDGE_INT                         = 0x1e,
+    SQ_TEX_WORD2                                          = 0x00008dfc,
+       OFFSET_X_mask                                     = 0x1f << 0,
+       OFFSET_X_shift                                    = 0,
+       OFFSET_Y_mask                                     = 0x1f << 5,
+       OFFSET_Y_shift                                    = 5,
+       OFFSET_Z_mask                                     = 0x1f << 10,
+       OFFSET_Z_shift                                    = 10,
+       SAMPLER_ID_mask                                   = 0x1f << 15,
+       SAMPLER_ID_shift                                  = 15,
+       SQ_TEX_WORD2__SRC_SEL_X_mask                      = 0x07 << 20,
+       SQ_TEX_WORD2__SRC_SEL_X_shift                     = 20,
+           SQ_SEL_X                                      = 0x00,
+           SQ_SEL_Y                                      = 0x01,
+           SQ_SEL_Z                                      = 0x02,
+           SQ_SEL_W                                      = 0x03,
+           SQ_SEL_0                                      = 0x04,
+           SQ_SEL_1                                      = 0x05,
+       SRC_SEL_Y_mask                                    = 0x07 << 23,
+       SRC_SEL_Y_shift                                   = 23,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+       SRC_SEL_Z_mask                                    = 0x07 << 26,
+       SRC_SEL_Z_shift                                   = 26,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+       SRC_SEL_W_mask                                    = 0x07 << 29,
+       SRC_SEL_W_shift                                   = 29,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+    SQ_CF_ALLOC_EXPORT_WORD1                              = 0x00008dfc,
+       BURST_COUNT_mask                                  = 0x0f << 17,
+       BURST_COUNT_shift                                 = 17,
+       END_OF_PROGRAM_bit                                = 1 << 21,
+       VALID_PIXEL_MODE_bit                              = 1 << 22,
+       SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask            = 0x7f << 23,
+       SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift           = 23,
+           SQ_CF_INST_MEM_STREAM0                        = 0x20,
+           SQ_CF_INST_MEM_STREAM1                        = 0x21,
+           SQ_CF_INST_MEM_STREAM2                        = 0x22,
+           SQ_CF_INST_MEM_STREAM3                        = 0x23,
+           SQ_CF_INST_MEM_SCRATCH                        = 0x24,
+           SQ_CF_INST_MEM_REDUCTION                      = 0x25,
+           SQ_CF_INST_MEM_RING                           = 0x26,
+           SQ_CF_INST_EXPORT                             = 0x27,
+           SQ_CF_INST_EXPORT_DONE                        = 0x28,
+       WHOLE_QUAD_MODE_bit                               = 1 << 30,
+       BARRIER_bit                                       = 1 << 31,
+    SQ_CF_ALU_WORD1                                       = 0x00008dfc,
+       KCACHE_MODE1_mask                                 = 0x03 << 0,
+       KCACHE_MODE1_shift                                = 0,
+           SQ_CF_KCACHE_NOP                              = 0x00,
+           SQ_CF_KCACHE_LOCK_1                           = 0x01,
+           SQ_CF_KCACHE_LOCK_2                           = 0x02,
+           SQ_CF_KCACHE_LOCK_LOOP_INDEX                  = 0x03,
+       KCACHE_ADDR0_mask                                 = 0xff << 2,
+       KCACHE_ADDR0_shift                                = 2,
+       KCACHE_ADDR1_mask                                 = 0xff << 10,
+       KCACHE_ADDR1_shift                                = 10,
+       SQ_CF_ALU_WORD1__COUNT_mask                       = 0x7f << 18,
+       SQ_CF_ALU_WORD1__COUNT_shift                      = 18,
+       SQ_CF_ALU_WORD1__ALT_CONST_bit                    = 1 << 25,
+       SQ_CF_ALU_WORD1__CF_INST_mask                     = 0x0f << 26,
+       SQ_CF_ALU_WORD1__CF_INST_shift                    = 26,
+           SQ_CF_INST_ALU                                = 0x08,
+           SQ_CF_INST_ALU_PUSH_BEFORE                    = 0x09,
+           SQ_CF_INST_ALU_POP_AFTER                      = 0x0a,
+           SQ_CF_INST_ALU_POP2_AFTER                     = 0x0b,
+           SQ_CF_INST_ALU_CONTINUE                       = 0x0d,
+           SQ_CF_INST_ALU_BREAK                          = 0x0e,
+           SQ_CF_INST_ALU_ELSE_AFTER                     = 0x0f,
+/*     WHOLE_QUAD_MODE_bit                               = 1 << 30, */
+/*     BARRIER_bit                                       = 1 << 31, */
+    SQ_TEX_WORD1                                          = 0x00008dfc,
+       SQ_TEX_WORD1__DST_GPR_mask                        = 0x7f << 0,
+       SQ_TEX_WORD1__DST_GPR_shift                       = 0,
+       SQ_TEX_WORD1__DST_REL_bit                         = 1 << 7,
+       SQ_TEX_WORD1__DST_SEL_X_mask                      = 0x07 << 9,
+       SQ_TEX_WORD1__DST_SEL_X_shift                     = 9,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+           SQ_SEL_MASK                                   = 0x07,
+       SQ_TEX_WORD1__DST_SEL_Y_mask                      = 0x07 << 12,
+       SQ_TEX_WORD1__DST_SEL_Y_shift                     = 12,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SQ_TEX_WORD1__DST_SEL_Z_mask                      = 0x07 << 15,
+       SQ_TEX_WORD1__DST_SEL_Z_shift                     = 15,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SQ_TEX_WORD1__DST_SEL_W_mask                      = 0x07 << 18,
+       SQ_TEX_WORD1__DST_SEL_W_shift                     = 18,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SQ_TEX_WORD1__LOD_BIAS_mask                       = 0x7f << 21,
+       SQ_TEX_WORD1__LOD_BIAS_shift                      = 21,
+       COORD_TYPE_X_bit                                  = 1 << 28,
+       COORD_TYPE_Y_bit                                  = 1 << 29,
+       COORD_TYPE_Z_bit                                  = 1 << 30,
+       COORD_TYPE_W_bit                                  = 1 << 31,
+    SQ_VTX_WORD0                                          = 0x00008dfc,
+       VTX_INST_mask                                     = 0x1f << 0,
+       VTX_INST_shift                                    = 0,
+           SQ_VTX_INST_FETCH                             = 0x00,
+           SQ_VTX_INST_SEMANTIC                          = 0x01,
+       FETCH_TYPE_mask                                   = 0x03 << 5,
+       FETCH_TYPE_shift                                  = 5,
+           SQ_VTX_FETCH_VERTEX_DATA                      = 0x00,
+           SQ_VTX_FETCH_INSTANCE_DATA                    = 0x01,
+           SQ_VTX_FETCH_NO_INDEX_OFFSET                  = 0x02,
+       FETCH_WHOLE_QUAD_bit                              = 1 << 7,
+       BUFFER_ID_mask                                    = 0xff << 8,
+       BUFFER_ID_shift                                   = 8,
+       SRC_GPR_mask                                      = 0x7f << 16,
+       SRC_GPR_shift                                     = 16,
+       SRC_REL_bit                                       = 1 << 23,
+       SQ_VTX_WORD0__SRC_SEL_X_mask                      = 0x03 << 24,
+       SQ_VTX_WORD0__SRC_SEL_X_shift                     = 24,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+       MEGA_FETCH_COUNT_mask                             = 0x3f << 26,
+       MEGA_FETCH_COUNT_shift                            = 26,
+    SQ_CF_ALLOC_EXPORT_WORD1_SWIZ                         = 0x00008dfc,
+       SEL_X_mask                                        = 0x07 << 0,
+       SEL_X_shift                                       = 0,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SEL_Y_mask                                        = 0x07 << 3,
+       SEL_Y_shift                                       = 3,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SEL_Z_mask                                        = 0x07 << 6,
+       SEL_Z_shift                                       = 6,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SEL_W_mask                                        = 0x07 << 9,
+       SEL_W_shift                                       = 9,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+    SQ_ALU_WORD1                                          = 0x00008dfc,
+       ENCODING_mask                                     = 0x07 << 15,
+       ENCODING_shift                                    = 15,
+       BANK_SWIZZLE_mask                                 = 0x07 << 18,
+       BANK_SWIZZLE_shift                                = 18,
+           SQ_ALU_VEC_012                                = 0x00,
+           SQ_ALU_VEC_021                                = 0x01,
+           SQ_ALU_VEC_120                                = 0x02,
+           SQ_ALU_VEC_102                                = 0x03,
+           SQ_ALU_VEC_201                                = 0x04,
+           SQ_ALU_VEC_210                                = 0x05,
+       SQ_ALU_WORD1__DST_GPR_mask                        = 0x7f << 21,
+       SQ_ALU_WORD1__DST_GPR_shift                       = 21,
+       SQ_ALU_WORD1__DST_REL_bit                         = 1 << 28,
+       DST_CHAN_mask                                     = 0x03 << 29,
+       DST_CHAN_shift                                    = 29,
+           CHAN_X                                        = 0x00,
+           CHAN_Y                                        = 0x01,
+           CHAN_Z                                        = 0x02,
+           CHAN_W                                        = 0x03,
+       SQ_ALU_WORD1__CLAMP_bit                           = 1 << 31,
+    SQ_CF_ALU_WORD0                                       = 0x00008dfc,
+       SQ_CF_ALU_WORD0__ADDR_mask                        = 0x3fffff << 0,
+       SQ_CF_ALU_WORD0__ADDR_shift                       = 0,
+       KCACHE_BANK0_mask                                 = 0x0f << 22,
+       KCACHE_BANK0_shift                                = 22,
+       KCACHE_BANK1_mask                                 = 0x0f << 26,
+       KCACHE_BANK1_shift                                = 26,
+       KCACHE_MODE0_mask                                 = 0x03 << 30,
+       KCACHE_MODE0_shift                                = 30,
+/*         SQ_CF_KCACHE_NOP                              = 0x00, */
+/*         SQ_CF_KCACHE_LOCK_1                           = 0x01, */
+/*         SQ_CF_KCACHE_LOCK_2                           = 0x02, */
+/*         SQ_CF_KCACHE_LOCK_LOOP_INDEX                  = 0x03, */
+    SQ_VTX_WORD2                                          = 0x00008dfc,
+       SQ_VTX_WORD2__OFFSET_mask                         = 0xffff << 0,
+       SQ_VTX_WORD2__OFFSET_shift                        = 0,
+       SQ_VTX_WORD2__ENDIAN_SWAP_mask                    = 0x03 << 16,
+       SQ_VTX_WORD2__ENDIAN_SWAP_shift                   = 16,
+           SQ_ENDIAN_NONE                                = 0x00,
+           SQ_ENDIAN_8IN16                               = 0x01,
+           SQ_ENDIAN_8IN32                               = 0x02,
+       CONST_BUF_NO_STRIDE_bit                           = 1 << 18,
+       MEGA_FETCH_bit                                    = 1 << 19,
+       SQ_VTX_WORD2__ALT_CONST_bit                       = 1 << 20,
+    SQ_ALU_WORD1_OP2_V2                                   = 0x00008dfc,
+       SRC0_ABS_bit                                      = 1 << 0,
+       SRC1_ABS_bit                                      = 1 << 1,
+       UPDATE_EXECUTE_MASK_bit                           = 1 << 2,
+       UPDATE_PRED_bit                                   = 1 << 3,
+       WRITE_MASK_bit                                    = 1 << 4,
+       SQ_ALU_WORD1_OP2_V2__OMOD_mask                    = 0x03 << 5,
+       SQ_ALU_WORD1_OP2_V2__OMOD_shift                   = 5,
+           SQ_ALU_OMOD_OFF                               = 0x00,
+           SQ_ALU_OMOD_M2                                = 0x01,
+           SQ_ALU_OMOD_M4                                = 0x02,
+           SQ_ALU_OMOD_D2                                = 0x03,
+       SQ_ALU_WORD1_OP2_V2__ALU_INST_mask                = 0x7ff << 7,
+       SQ_ALU_WORD1_OP2_V2__ALU_INST_shift               = 7,
+           SQ_OP2_INST_ADD                               = 0x00,
+           SQ_OP2_INST_MUL                               = 0x01,
+           SQ_OP2_INST_MUL_IEEE                          = 0x02,
+           SQ_OP2_INST_MAX                               = 0x03,
+           SQ_OP2_INST_MIN                               = 0x04,
+           SQ_OP2_INST_MAX_DX10                          = 0x05,
+           SQ_OP2_INST_MIN_DX10                          = 0x06,
+           SQ_OP2_INST_SETE                              = 0x08,
+           SQ_OP2_INST_SETGT                             = 0x09,
+           SQ_OP2_INST_SETGE                             = 0x0a,
+           SQ_OP2_INST_SETNE                             = 0x0b,
+           SQ_OP2_INST_SETE_DX10                         = 0x0c,
+           SQ_OP2_INST_SETGT_DX10                        = 0x0d,
+           SQ_OP2_INST_SETGE_DX10                        = 0x0e,
+           SQ_OP2_INST_SETNE_DX10                        = 0x0f,
+           SQ_OP2_INST_FRACT                             = 0x10,
+           SQ_OP2_INST_TRUNC                             = 0x11,
+           SQ_OP2_INST_CEIL                              = 0x12,
+           SQ_OP2_INST_RNDNE                             = 0x13,
+           SQ_OP2_INST_FLOOR                             = 0x14,
+           SQ_OP2_INST_MOVA                              = 0x15,
+           SQ_OP2_INST_MOVA_FLOOR                        = 0x16,
+           SQ_OP2_INST_MOVA_INT                          = 0x18,
+           SQ_OP2_INST_MOV                               = 0x19,
+           SQ_OP2_INST_NOP                               = 0x1a,
+           SQ_OP2_INST_PRED_SETGT_UINT                   = 0x1e,
+           SQ_OP2_INST_PRED_SETGE_UINT                   = 0x1f,
+           SQ_OP2_INST_PRED_SETE                         = 0x20,
+           SQ_OP2_INST_PRED_SETGT                        = 0x21,
+           SQ_OP2_INST_PRED_SETGE                        = 0x22,
+           SQ_OP2_INST_PRED_SETNE                        = 0x23,
+           SQ_OP2_INST_PRED_SET_INV                      = 0x24,
+           SQ_OP2_INST_PRED_SET_POP                      = 0x25,
+           SQ_OP2_INST_PRED_SET_CLR                      = 0x26,
+           SQ_OP2_INST_PRED_SET_RESTORE                  = 0x27,
+           SQ_OP2_INST_PRED_SETE_PUSH                    = 0x28,
+           SQ_OP2_INST_PRED_SETGT_PUSH                   = 0x29,
+           SQ_OP2_INST_PRED_SETGE_PUSH                   = 0x2a,
+           SQ_OP2_INST_PRED_SETNE_PUSH                   = 0x2b,
+           SQ_OP2_INST_KILLE                             = 0x2c,
+           SQ_OP2_INST_KILLGT                            = 0x2d,
+           SQ_OP2_INST_KILLGE                            = 0x2e,
+           SQ_OP2_INST_KILLNE                            = 0x2f,
+           SQ_OP2_INST_AND_INT                           = 0x30,
+           SQ_OP2_INST_OR_INT                            = 0x31,
+           SQ_OP2_INST_XOR_INT                           = 0x32,
+           SQ_OP2_INST_NOT_INT                           = 0x33,
+           SQ_OP2_INST_ADD_INT                           = 0x34,
+           SQ_OP2_INST_SUB_INT                           = 0x35,
+           SQ_OP2_INST_MAX_INT                           = 0x36,
+           SQ_OP2_INST_MIN_INT                           = 0x37,
+           SQ_OP2_INST_MAX_UINT                          = 0x38,
+           SQ_OP2_INST_MIN_UINT                          = 0x39,
+           SQ_OP2_INST_SETE_INT                          = 0x3a,
+           SQ_OP2_INST_SETGT_INT                         = 0x3b,
+           SQ_OP2_INST_SETGE_INT                         = 0x3c,
+           SQ_OP2_INST_SETNE_INT                         = 0x3d,
+           SQ_OP2_INST_SETGT_UINT                        = 0x3e,
+           SQ_OP2_INST_SETGE_UINT                        = 0x3f,
+           SQ_OP2_INST_KILLGT_UINT                       = 0x40,
+           SQ_OP2_INST_KILLGE_UINT                       = 0x41,
+           SQ_OP2_INST_PRED_SETE_INT                     = 0x42,
+           SQ_OP2_INST_PRED_SETGT_INT                    = 0x43,
+           SQ_OP2_INST_PRED_SETGE_INT                    = 0x44,
+           SQ_OP2_INST_PRED_SETNE_INT                    = 0x45,
+           SQ_OP2_INST_KILLE_INT                         = 0x46,
+           SQ_OP2_INST_KILLGT_INT                        = 0x47,
+           SQ_OP2_INST_KILLGE_INT                        = 0x48,
+           SQ_OP2_INST_KILLNE_INT                        = 0x49,
+           SQ_OP2_INST_PRED_SETE_PUSH_INT                = 0x4a,
+           SQ_OP2_INST_PRED_SETGT_PUSH_INT               = 0x4b,
+           SQ_OP2_INST_PRED_SETGE_PUSH_INT               = 0x4c,
+           SQ_OP2_INST_PRED_SETNE_PUSH_INT               = 0x4d,
+           SQ_OP2_INST_PRED_SETLT_PUSH_INT               = 0x4e,
+           SQ_OP2_INST_PRED_SETLE_PUSH_INT               = 0x4f,
+           SQ_OP2_INST_DOT4                              = 0x50,
+           SQ_OP2_INST_DOT4_IEEE                         = 0x51,
+           SQ_OP2_INST_CUBE                              = 0x52,
+           SQ_OP2_INST_MAX4                              = 0x53,
+           SQ_OP2_INST_MOVA_GPR_INT                      = 0x60,
+           SQ_OP2_INST_EXP_IEEE                          = 0x61,
+           SQ_OP2_INST_LOG_CLAMPED                       = 0x62,
+           SQ_OP2_INST_LOG_IEEE                          = 0x63,
+           SQ_OP2_INST_RECIP_CLAMPED                     = 0x64,
+           SQ_OP2_INST_RECIP_FF                          = 0x65,
+           SQ_OP2_INST_RECIP_IEEE                        = 0x66,
+           SQ_OP2_INST_RECIPSQRT_CLAMPED                 = 0x67,
+           SQ_OP2_INST_RECIPSQRT_FF                      = 0x68,
+           SQ_OP2_INST_RECIPSQRT_IEEE                    = 0x69,
+           SQ_OP2_INST_SQRT_IEEE                         = 0x6a,
+           SQ_OP2_INST_FLT_TO_INT                        = 0x6b,
+           SQ_OP2_INST_INT_TO_FLT                        = 0x6c,
+           SQ_OP2_INST_UINT_TO_FLT                       = 0x6d,
+           SQ_OP2_INST_SIN                               = 0x6e,
+           SQ_OP2_INST_COS                               = 0x6f,
+           SQ_OP2_INST_ASHR_INT                          = 0x70,
+           SQ_OP2_INST_LSHR_INT                          = 0x71,
+           SQ_OP2_INST_LSHL_INT                          = 0x72,
+           SQ_OP2_INST_MULLO_INT                         = 0x73,
+           SQ_OP2_INST_MULHI_INT                         = 0x74,
+           SQ_OP2_INST_MULLO_UINT                        = 0x75,
+           SQ_OP2_INST_MULHI_UINT                        = 0x76,
+           SQ_OP2_INST_RECIP_INT                         = 0x77,
+           SQ_OP2_INST_RECIP_UINT                        = 0x78,
+           SQ_OP2_INST_FLT_TO_UINT                       = 0x79,
+    SQ_CF_ALLOC_EXPORT_WORD1_BUF                          = 0x00008dfc,
+       ARRAY_SIZE_mask                                   = 0xfff << 0,
+       ARRAY_SIZE_shift                                  = 0,
+       COMP_MASK_mask                                    = 0x0f << 12,
+       COMP_MASK_shift                                   = 12,
+    SQ_CF_WORD0                                           = 0x00008dfc,
+    SQ_CF_ALLOC_EXPORT_WORD0                              = 0x00008dfc,
+       ARRAY_BASE_mask                                   = 0x1fff << 0,
+       ARRAY_BASE_shift                                  = 0,
+       SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask               = 0x03 << 13,
+       SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift              = 13,
+           SQ_EXPORT_PIXEL                               = 0x00,
+           SQ_EXPORT_POS                                 = 0x01,
+           SQ_EXPORT_PARAM                               = 0x02,
+           X_UNUSED_FOR_SX_EXPORTS                       = 0x03,
+       RW_GPR_mask                                       = 0x7f << 15,
+       RW_GPR_shift                                      = 15,
+       RW_REL_bit                                        = 1 << 22,
+       INDEX_GPR_mask                                    = 0x7f << 23,
+       INDEX_GPR_shift                                   = 23,
+       ELEM_SIZE_mask                                    = 0x03 << 30,
+       ELEM_SIZE_shift                                   = 30,
+    SQ_VTX_WORD1                                          = 0x00008dfc,
+       SQ_VTX_WORD1__DST_SEL_X_mask                      = 0x07 << 9,
+       SQ_VTX_WORD1__DST_SEL_X_shift                     = 9,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SQ_VTX_WORD1__DST_SEL_Y_mask                      = 0x07 << 12,
+       SQ_VTX_WORD1__DST_SEL_Y_shift                     = 12,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SQ_VTX_WORD1__DST_SEL_Z_mask                      = 0x07 << 15,
+       SQ_VTX_WORD1__DST_SEL_Z_shift                     = 15,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       SQ_VTX_WORD1__DST_SEL_W_mask                      = 0x07 << 18,
+       SQ_VTX_WORD1__DST_SEL_W_shift                     = 18,
+/*         SQ_SEL_X                                      = 0x00, */
+/*         SQ_SEL_Y                                      = 0x01, */
+/*         SQ_SEL_Z                                      = 0x02, */
+/*         SQ_SEL_W                                      = 0x03, */
+/*         SQ_SEL_0                                      = 0x04, */
+/*         SQ_SEL_1                                      = 0x05, */
+/*         SQ_SEL_MASK                                   = 0x07, */
+       USE_CONST_FIELDS_bit                              = 1 << 21,
+       SQ_VTX_WORD1__DATA_FORMAT_mask                    = 0x3f << 22,
+       SQ_VTX_WORD1__DATA_FORMAT_shift                   = 22,
+       SQ_VTX_WORD1__NUM_FORMAT_ALL_mask                 = 0x03 << 28,
+       SQ_VTX_WORD1__NUM_FORMAT_ALL_shift                = 28,
+           SQ_NUM_FORMAT_NORM                            = 0x00,
+           SQ_NUM_FORMAT_INT                             = 0x01,
+           SQ_NUM_FORMAT_SCALED                          = 0x02,
+       SQ_VTX_WORD1__FORMAT_COMP_ALL_bit                 = 1 << 30,
+       SQ_VTX_WORD1__SRF_MODE_ALL_bit                    = 1 << 31,
+    SQ_ALU_WORD1_OP2                                      = 0x00008dfc,
+/*     SRC0_ABS_bit                                      = 1 << 0, */
+/*     SRC1_ABS_bit                                      = 1 << 1, */
+/*     UPDATE_EXECUTE_MASK_bit                           = 1 << 2, */
+/*     UPDATE_PRED_bit                                   = 1 << 3, */
+/*     WRITE_MASK_bit                                    = 1 << 4, */
+       FOG_MERGE_bit                                     = 1 << 5,
+       SQ_ALU_WORD1_OP2__OMOD_mask                       = 0x03 << 6,
+       SQ_ALU_WORD1_OP2__OMOD_shift                      = 6,
+/*         SQ_ALU_OMOD_OFF                               = 0x00, */
+/*         SQ_ALU_OMOD_M2                                = 0x01, */
+/*         SQ_ALU_OMOD_M4                                = 0x02, */
+/*         SQ_ALU_OMOD_D2                                = 0x03, */
+       SQ_ALU_WORD1_OP2__ALU_INST_mask                   = 0x3ff << 8,
+       SQ_ALU_WORD1_OP2__ALU_INST_shift                  = 8,
+/*         SQ_OP2_INST_ADD                               = 0x00, */
+/*         SQ_OP2_INST_MUL                               = 0x01, */
+/*         SQ_OP2_INST_MUL_IEEE                          = 0x02, */
+/*         SQ_OP2_INST_MAX                               = 0x03, */
+/*         SQ_OP2_INST_MIN                               = 0x04, */
+/*         SQ_OP2_INST_MAX_DX10                          = 0x05, */
+/*         SQ_OP2_INST_MIN_DX10                          = 0x06, */
+/*         SQ_OP2_INST_SETE                              = 0x08, */
+/*         SQ_OP2_INST_SETGT                             = 0x09, */
+/*         SQ_OP2_INST_SETGE                             = 0x0a, */
+/*         SQ_OP2_INST_SETNE                             = 0x0b, */
+/*         SQ_OP2_INST_SETE_DX10                         = 0x0c, */
+/*         SQ_OP2_INST_SETGT_DX10                        = 0x0d, */
+/*         SQ_OP2_INST_SETGE_DX10                        = 0x0e, */
+/*         SQ_OP2_INST_SETNE_DX10                        = 0x0f, */
+/*         SQ_OP2_INST_FRACT                             = 0x10, */
+/*         SQ_OP2_INST_TRUNC                             = 0x11, */
+/*         SQ_OP2_INST_CEIL                              = 0x12, */
+/*         SQ_OP2_INST_RNDNE                             = 0x13, */
+/*         SQ_OP2_INST_FLOOR                             = 0x14, */
+/*         SQ_OP2_INST_MOVA                              = 0x15, */
+/*         SQ_OP2_INST_MOVA_FLOOR                        = 0x16, */
+/*         SQ_OP2_INST_MOVA_INT                          = 0x18, */
+/*         SQ_OP2_INST_MOV                               = 0x19, */
+/*         SQ_OP2_INST_NOP                               = 0x1a, */
+/*         SQ_OP2_INST_PRED_SETGT_UINT                   = 0x1e, */
+/*         SQ_OP2_INST_PRED_SETGE_UINT                   = 0x1f, */
+/*         SQ_OP2_INST_PRED_SETE                         = 0x20, */
+/*         SQ_OP2_INST_PRED_SETGT                        = 0x21, */
+/*         SQ_OP2_INST_PRED_SETGE                        = 0x22, */
+/*         SQ_OP2_INST_PRED_SETNE                        = 0x23, */
+/*         SQ_OP2_INST_PRED_SET_INV                      = 0x24, */
+/*         SQ_OP2_INST_PRED_SET_POP                      = 0x25, */
+/*         SQ_OP2_INST_PRED_SET_CLR                      = 0x26, */
+/*         SQ_OP2_INST_PRED_SET_RESTORE                  = 0x27, */
+/*         SQ_OP2_INST_PRED_SETE_PUSH                    = 0x28, */
+/*         SQ_OP2_INST_PRED_SETGT_PUSH                   = 0x29, */
+/*         SQ_OP2_INST_PRED_SETGE_PUSH                   = 0x2a, */
+/*         SQ_OP2_INST_PRED_SETNE_PUSH                   = 0x2b, */
+/*         SQ_OP2_INST_KILLE                             = 0x2c, */
+/*         SQ_OP2_INST_KILLGT                            = 0x2d, */
+/*         SQ_OP2_INST_KILLGE                            = 0x2e, */
+/*         SQ_OP2_INST_KILLNE                            = 0x2f, */
+/*         SQ_OP2_INST_AND_INT                           = 0x30, */
+/*         SQ_OP2_INST_OR_INT                            = 0x31, */
+/*         SQ_OP2_INST_XOR_INT                           = 0x32, */
+/*         SQ_OP2_INST_NOT_INT                           = 0x33, */
+/*         SQ_OP2_INST_ADD_INT                           = 0x34, */
+/*         SQ_OP2_INST_SUB_INT                           = 0x35, */
+/*         SQ_OP2_INST_MAX_INT                           = 0x36, */
+/*         SQ_OP2_INST_MIN_INT                           = 0x37, */
+/*         SQ_OP2_INST_MAX_UINT                          = 0x38, */
+/*         SQ_OP2_INST_MIN_UINT                          = 0x39, */
+/*         SQ_OP2_INST_SETE_INT                          = 0x3a, */
+/*         SQ_OP2_INST_SETGT_INT                         = 0x3b, */
+/*         SQ_OP2_INST_SETGE_INT                         = 0x3c, */
+/*         SQ_OP2_INST_SETNE_INT                         = 0x3d, */
+/*         SQ_OP2_INST_SETGT_UINT                        = 0x3e, */
+/*         SQ_OP2_INST_SETGE_UINT                        = 0x3f, */
+/*         SQ_OP2_INST_KILLGT_UINT                       = 0x40, */
+/*         SQ_OP2_INST_KILLGE_UINT                       = 0x41, */
+/*         SQ_OP2_INST_PRED_SETE_INT                     = 0x42, */
+/*         SQ_OP2_INST_PRED_SETGT_INT                    = 0x43, */
+/*         SQ_OP2_INST_PRED_SETGE_INT                    = 0x44, */
+/*         SQ_OP2_INST_PRED_SETNE_INT                    = 0x45, */
+/*         SQ_OP2_INST_KILLE_INT                         = 0x46, */
+/*         SQ_OP2_INST_KILLGT_INT                        = 0x47, */
+/*         SQ_OP2_INST_KILLGE_INT                        = 0x48, */
+/*         SQ_OP2_INST_KILLNE_INT                        = 0x49, */
+/*         SQ_OP2_INST_PRED_SETE_PUSH_INT                = 0x4a, */
+/*         SQ_OP2_INST_PRED_SETGT_PUSH_INT               = 0x4b, */
+/*         SQ_OP2_INST_PRED_SETGE_PUSH_INT               = 0x4c, */
+/*         SQ_OP2_INST_PRED_SETNE_PUSH_INT               = 0x4d, */
+/*         SQ_OP2_INST_PRED_SETLT_PUSH_INT               = 0x4e, */
+/*         SQ_OP2_INST_PRED_SETLE_PUSH_INT               = 0x4f, */
+/*         SQ_OP2_INST_DOT4                              = 0x50, */
+/*         SQ_OP2_INST_DOT4_IEEE                         = 0x51, */
+/*         SQ_OP2_INST_CUBE                              = 0x52, */
+/*         SQ_OP2_INST_MAX4                              = 0x53, */
+/*         SQ_OP2_INST_MOVA_GPR_INT                      = 0x60, */

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