[haiku-commits] r40850 - haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx

  • From: kallisti5@xxxxxxxxxxx
  • To: haiku-commits@xxxxxxxxxxxxx
  • Date: Sun, 6 Mar 2011 19:26:19 +0100 (CET)

Author: kallisti5
Date: 2011-03-06 19:26:19 +0100 (Sun, 06 Mar 2011)
New Revision: 40850
Changeset: http://dev.haiku-os.org/changeset/40850

Modified:
   
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.cpp
   
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.h
   
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.cpp
   
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.h
Log:
fix a few missed style corrections in BeceemCPU; style cleanup in BeceemDDR; no 
functional change

Modified: 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.cpp
===================================================================
--- 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.cpp
    2011-03-06 16:57:59 UTC (rev 40849)
+++ 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.cpp
    2011-03-06 18:26:19 UTC (rev 40850)
@@ -43,11 +43,10 @@
        }
 
        // Adjust clock register contents to start cpu
-       if (fWmxDevice->CPUFlashBoot) {
-               clockRegister &= (~(1<<30));
-       } else {
-               clockRegister |= (1<<30);
-       }
+       if (fWmxDevice->CPUFlashBoot)
+               clockRegister &= ~(1 << 30);
+       else
+               clockRegister |= (1 << 30);
 
        // Write new clock register contents
        if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
@@ -66,14 +65,13 @@
        unsigned int value = 0;
        unsigned int uiResetValue = 0;
 
-       if (fWmxDevice->deviceChipID >= T3LPB)
-       {
+       if (fWmxDevice->deviceChipID >= T3LPB) {
                BizarroReadRegister(SYS_CFG, sizeof(value), &value);
                BizarroReadRegister(SYS_CFG, sizeof(value), &value);
                        // SYS_CFG register is write protected hence for 
modifying
                        // this reg value, it should be read twice before 
writing.
 
-               value = value | (fWmxDevice->syscfgBefFw & 0x00000060) ;
+               value = value | (fWmxDevice->syscfgBefFw & 0x00000060);
                        // making bit[6...5] same as was before f/w download. 
this
                        // setting forces the h/w to re-populated the SP RAM 
area
                        // with the string descriptor .
@@ -85,23 +83,20 @@
        }
 
        /* Reset the UMA-B Device */
-       if (fWmxDevice->deviceChipID >= T3LPB)
-       {
+       if (fWmxDevice->deviceChipID >= T3LPB) {
                // Reset UMA-B
                // TODO : USB reset needs implimented
                /*
-               if (usb_reset_device(psIntfAdapter->udev) != B_OK)
-               {
+               if (usb_reset_device(psIntfAdapter->udev) != B_OK) {
                        TRACE_ALWAYS("Error: USB Reset failed\n");
                        retrun B_ERROR;
                }
                */
 
-               if (fWmxDevice->deviceChipID == BCS220_2 ||
-                       fWmxDevice->deviceChipID == BCS220_2BC ||
-                       fWmxDevice->deviceChipID == BCS250_BC ||
-                       fWmxDevice->deviceChipID == BCS220_3)
-               {
+               if (fWmxDevice->deviceChipID == BCS220_2
+                       || fWmxDevice->deviceChipID == BCS220_2BC
+                       || fWmxDevice->deviceChipID == BCS250_BC
+                       || fWmxDevice->deviceChipID == BCS220_3) {
                        if (BizarroReadRegister(HPM_CONFIG_LDO145,
                                sizeof(value), &value) != B_OK) {
                                TRACE_ALWAYS("Error: USB read failed during 
reset\n");
@@ -120,8 +115,7 @@
        }
        // TODO : ELSE OLDER CHIP ID's < T3LP see Misc.c:1048
 
-       if (fWmxDevice->CPUFlashBoot)
-       {
+       if (fWmxDevice->CPUFlashBoot) {
                // In flash boot mode MIPS state register has reverse polarity.
                // So just or with setting bit 30.
                // Make the MIPS in Reset state.
@@ -131,7 +125,7 @@
                        return B_ERROR;
                }
                // set 30th bit
-               uiResetValue |=(1<<30);
+               uiResetValue |= (1 << 30);
 
                if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
                        sizeof(uiResetValue), &uiResetValue) != B_OK) {
@@ -140,17 +134,15 @@
                }
        }
 
-       if (fWmxDevice->deviceChipID >= T3LPB)
-       {
+       if (fWmxDevice->deviceChipID >= T3LPB) {
                uiResetValue = 0;
                        // WA for SYSConfig Issue.
                BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), 
&uiResetValue);
-               if (uiResetValue & (1<<4))
-               {
+               if (uiResetValue & (1 << 4)) {
                        uiResetValue = 0;
                        BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), 
&uiResetValue);
                                // Read SYSCFG Twice to make it writable.
-                       uiResetValue &= (~(1<<4));
+                       uiResetValue &= ~(1 << 4);
 
                        if (BizarroWriteRegister(SYS_CFG,
                                sizeof(uiResetValue), &uiResetValue) != B_OK) {

Modified: 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.h
===================================================================
--- 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.h  
    2011-03-06 16:57:59 UTC (rev 40849)
+++ 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.h  
    2011-03-06 18:26:19 UTC (rev 40850)
@@ -16,9 +16,7 @@
 #define CLOCK_RESET_CNTRL_REG_1 0x0F00000C
 
 
-class BeceemCPU
-{
-
+class BeceemCPU {
 public:
                                                                BeceemCPU();
                        status_t                        CPUInit(WIMAX_DEVICE* 
swmxdevice);

Modified: 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.cpp
===================================================================
--- 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.cpp
    2011-03-06 16:57:59 UTC (rev 40849)
+++ 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.cpp
    2011-03-06 18:26:19 UTC (rev 40850)
@@ -2,100 +2,90 @@
  *     Beceem WiMax USB Driver.
  *     Copyright (c) 2010 Alexander von Gluck <kallisti5@xxxxxxxxxxx>
  *     Distributed under the terms of the GNU General Public License.
- *     
+ *
  *     Based on GPL code developed by: Beceem Communications Pvt. Ltd
- *     
+ *
  *     Description: Wrangle Beceem volatile DDR memory.
  */
 
 
-#include "Settings.h"
 #include "BeceemDDR.h"
+#include "Settings.h"
 
 
 BeceemDDR::BeceemDDR()
 {
-  TRACE("Debug: Load DDR handler\n");
+       TRACE("Debug: Load DDR handler\n");
 }
 
 
 status_t
 BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
 {
-       pwmxdevice = swmxdevice;
-       PDDR_SETTING psDDRSetting=NULL;
+       fWmxDevice = swmxdevice;
+       PDDR_SETTING psDDRSetting = NULL;
 
-       unsigned int HostDrvrConfig6 = pwmxdevice->vendorcfg.HostDrvrConfig6;
-       unsigned int uiHostDrvrCfg6 = 0;
-       unsigned int ChipID = pwmxdevice->deviceChipID;
+       unsigned int chipID = fWmxDevice->deviceChipID;
 
-       unsigned long RegCount=0;
+       unsigned long registerCount = 0;
        unsigned long value = 0;
        unsigned int uiResetValue = 0;
        unsigned int uiClockSetting = 0;
        int retval = B_OK;
 
-       unsigned int    DDRSetting = 0;
-       bool                    PmuMode = 0;
-       bool                    MipsConfig = 0;
-       bool                    PLLConfig = 0;
+       // Grab the Config6 metric from the vendor config and convert endianness
+       unsigned int vendorConfig6raw = fWmxDevice->vendorcfg.HostDrvrConfig6;
+       vendorConfig6raw &= ~(htonl(1 << 15));
+       unsigned int vendorConfig6 = ntohl(vendorConfig6raw);
 
-       HostDrvrConfig6 &= ~(htonl(1 << 15));
-       uiHostDrvrCfg6 = ntohl(HostDrvrConfig6);
+       // Read our vendor provided Config6 metric and populate memory settings
+       unsigned int vendorDDRSetting = (ntohl(vendorConfig6raw) >> 8) & 0x0F;
+       bool vendorPmuMode = (vendorConfig6 >> 24) & 0x03;
+       bool vendorMipsConfig = (vendorConfig6 >> 20) & 0x01;
+       bool vendorPLLConfig = (vendorConfig6 >> 19) & 0x01;
 
-       DDRSetting =    (ntohl(HostDrvrConfig6) >>8)&0x0F ;
-       PmuMode =               (uiHostDrvrCfg6>>24)&0x03;
-       MipsConfig =    (uiHostDrvrCfg6>>20)&0x01;
-       PLLConfig =     (uiHostDrvrCfg6>>19)&0x01;
+       switch (chipID) {
+               case 0xbece3200:
+                       switch (vendorDDRSetting) {
+                               case DDR_80_MHZ:
+                                       psDDRSetting = asT3LP_DDRSetting80MHz;
+                                       registerCount = 
sizeof(asT3LP_DDRSetting80MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               case DDR_100_MHZ:
+                                       psDDRSetting = asT3LP_DDRSetting100MHz;
+                                       registerCount = 
sizeof(asT3LP_DDRSetting100MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               case DDR_133_MHZ:
+                                       psDDRSetting = asT3LP_DDRSetting133MHz;
+                                       registerCount = 
sizeof(asT3LP_DDRSetting133MHz)
+                                               / sizeof(DDR_SETTING);
 
-    switch (ChipID)
-       {
-       case 0xbece3200:
-           switch (DDRSetting)
-           {
-               case DDR_80_MHZ:
-                               psDDRSetting=asT3LP_DDRSetting80MHz;
-                           RegCount=(sizeof(asT3LP_DDRSetting80MHz)/
-                               sizeof(DDR_SETTING));
-                           break;
-                   case DDR_100_MHZ:
-                               psDDRSetting=asT3LP_DDRSetting100MHz;
-                           RegCount=(sizeof(asT3LP_DDRSetting100MHz)/
-                               sizeof(DDR_SETTING));
-                           break;
-                   case DDR_133_MHZ:
-                               psDDRSetting=asT3LP_DDRSetting133MHz;
-                           RegCount=(sizeof(asT3LP_DDRSetting133MHz)/
-                                       sizeof(DDR_SETTING));
-                               if(MipsConfig == MIPS_200_MHZ)
-                               {
-                                       uiClockSetting = 0x03F13652;
-                               }
-                               else
-                               {
-                                       uiClockSetting = 0x03F1365B;
-                               }
-                               break;
-                   default:
-                           return -EINVAL;
-        }
+                                       if (vendorMipsConfig == MIPS_200_MHZ)
+                                               uiClockSetting = 0x03F13652;
+                                       else
+                                               uiClockSetting = 0x03F1365B;
+                                       break;
+                               default:
+                                       return -EINVAL;
+                       }
+                       break;
 
-               break;
-       case T3LPB:
-       case BCS220_2:
-       case BCS220_2BC:
-       case BCS250_BC:
-       case BCS220_3 :
-               // We need to check current value and additionally set bit 2 and
-               // bit 6 to 1 for BBIC 2mA drive
-               if( (ChipID != BCS220_2) &&
-                       (ChipID != BCS220_2BC) &&
-                       (ChipID != BCS220_3) )
-               {
-                               retval= BizarroReadRegister((unsigned 
int)0x0f000830,
+               case T3LPB:
+               case BCS220_2:
+               case BCS220_2BC:
+               case BCS250_BC:
+               case BCS220_3 :
+                       // We need to check current value and additionally set 
bit 2 and
+                       // bit 6 to 1 for BBIC 2mA drive
+                       if ((chipID != BCS220_2)
+                               && (chipID != BCS220_2BC)
+                               && (chipID != BCS220_3)) {
+                               retval = BizarroReadRegister((unsigned 
int)0x0f000830,
                                        sizeof(uiResetValue), &uiResetValue);
 
-                               if(retval < 0) {
+                               if (retval < 0) {
                                        TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                                __FUNCTION__, __LINE__);
                                        return retval;
@@ -103,172 +93,155 @@
                                uiResetValue |= 0x44;
                                retval = BizarroWriteRegister((unsigned 
int)0x0f000830,
                                        sizeof(uiResetValue), &uiResetValue);
-                               if(retval < 0) {
+                               if (retval < 0) {
                                        TRACE_ALWAYS("%s:%d 
BizarroWriteRegister failed\n",
                                                __FUNCTION__, __LINE__);
                                        return retval;
                                }
-               }
-               switch(DDRSetting)
-               {
-                       case DDR_80_MHZ:
-                               TRACE("Debug: DDR 80MHz\n");
-                               psDDRSetting = asT3LPB_DDRSetting80MHz;
-                       RegCount=(sizeof(asT3B_DDRSetting80MHz)/
-                                 sizeof(DDR_SETTING));
-                       break;
-            case DDR_100_MHZ:
-                               TRACE("Debug: DDR 100MHz\n");
-                               psDDRSetting=asT3LPB_DDRSetting100MHz;
-                       RegCount=(sizeof(asT3B_DDRSetting100MHz)/
-                                sizeof(DDR_SETTING));
-                       break;
-            case DDR_133_MHZ:
-                               TRACE("Debug: DDR 133MHz\n");
-                               psDDRSetting = asT3LPB_DDRSetting133MHz;
-                               RegCount=(sizeof(asT3B_DDRSetting133MHz)/
-                                                sizeof(DDR_SETTING));
+                       }
 
-                               if(MipsConfig == MIPS_200_MHZ)
-                               {
-                                       uiClockSetting = 0x03F13652;
-                               }
-                               else
-                               {
-                                       uiClockSetting = 0x03F1365B;
-                               }
-                       break;
+                       switch(vendorDDRSetting) {
+                               case DDR_80_MHZ:
+                                       TRACE("Debug: DDR 80MHz\n");
+                                       psDDRSetting = asT3LPB_DDRSetting80MHz;
+                                       registerCount = 
sizeof(asT3B_DDRSetting80MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               case DDR_100_MHZ:
+                                       TRACE("Debug: DDR 100MHz\n");
+                                       psDDRSetting = asT3LPB_DDRSetting100MHz;
+                                       registerCount = 
sizeof(asT3B_DDRSetting100MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               case DDR_133_MHZ:
+                                       TRACE("Debug: DDR 133MHz\n");
+                                       psDDRSetting = asT3LPB_DDRSetting133MHz;
+                                       registerCount = 
sizeof(asT3B_DDRSetting133MHz)
+                                               / sizeof(DDR_SETTING);
 
-                       case DDR_160_MHZ:
-                               TRACE("Debug: DDR 160MHz\n");
-                               psDDRSetting = asT3LPB_DDRSetting160MHz;
-                               RegCount = 
sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SETTING);
+                                       if (vendorMipsConfig == MIPS_200_MHZ)
+                                               uiClockSetting = 0x03F13652;
+                                       else
+                                               uiClockSetting = 0x03F1365B;
+                                       break;
 
-                               if(MipsConfig == MIPS_200_MHZ)
-                               {
-                                       TRACE("Debug: MIPS 200Mhz\n");
-                                       uiClockSetting = 0x03F137D2;
-                               }
-                               else
-                               {
-                                       uiClockSetting = 0x03F137DB;
-                               }
+                               case DDR_160_MHZ:
+                                       TRACE("Debug: DDR 160MHz\n");
+                                       psDDRSetting = asT3LPB_DDRSetting160MHz;
+                                       registerCount = 
sizeof(asT3LPB_DDRSetting160MHz)
+                                               / sizeof(DDR_SETTING);
+
+                                       if (vendorMipsConfig == MIPS_200_MHZ) {
+                                               TRACE("Debug: MIPS 200Mhz\n");
+                                               uiClockSetting = 0x03F137D2;
+                                       } else {
+                                               uiClockSetting = 0x03F137DB;
+                                       }
                        }
                        break;
 
-       case 0xbece0110:
-       case 0xbece0120:
-       case 0xbece0121:
-       case 0xbece0130:
-       case 0xbece0300:
-           switch (DDRSetting)
-           {
-               case DDR_80_MHZ:
-                               psDDRSetting = asT3_DDRSetting80MHz;
-                           RegCount = (sizeof(asT3_DDRSetting80MHz)/
-                               sizeof(DDR_SETTING));
-                           break;
-                   case DDR_100_MHZ:
-                               psDDRSetting = asT3_DDRSetting100MHz;
-                           RegCount = (sizeof(asT3_DDRSetting100MHz)/
-                               sizeof(DDR_SETTING));
-                           break;
-                   case DDR_133_MHZ:
-                               psDDRSetting = asT3_DDRSetting133MHz;
-                           RegCount = (sizeof(asT3_DDRSetting133MHz)/
-                               sizeof(DDR_SETTING));
-                               break;
-                   default:
-                           return -EINVAL;
-        }
-       case 0xbece0310:
-       {
-           switch (DDRSetting)
-           {
-               case DDR_80_MHZ:
-                               psDDRSetting = asT3B_DDRSetting80MHz;
-                       RegCount=(sizeof(asT3B_DDRSetting80MHz)/
-                                 sizeof(DDR_SETTING));
-                   break;
-            case DDR_100_MHZ:
-                               psDDRSetting=asT3B_DDRSetting100MHz;
-                       RegCount=(sizeof(asT3B_DDRSetting100MHz)/
-                                sizeof(DDR_SETTING));
-                       break;
-            case DDR_133_MHZ:
+               case 0xbece0110:
+               case 0xbece0120:
+               case 0xbece0121:
+               case 0xbece0130:
+               case 0xbece0300:
+                       switch (vendorDDRSetting) {
+                               case DDR_80_MHZ:
+                                       psDDRSetting = asT3_DDRSetting80MHz;
+                                       registerCount = 
sizeof(asT3_DDRSetting80MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               case DDR_100_MHZ:
+                                       psDDRSetting = asT3_DDRSetting100MHz;
+                                       registerCount = 
sizeof(asT3_DDRSetting100MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               case DDR_133_MHZ:
+                                       psDDRSetting = asT3_DDRSetting133MHz;
+                                       registerCount = 
sizeof(asT3_DDRSetting133MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               default:
+                                       return -EINVAL;
+                       }
+               case 0xbece0310:
+               {
+                       switch (vendorDDRSetting) {
+                               case DDR_80_MHZ:
+                                       psDDRSetting = asT3B_DDRSetting80MHz;
+                                       registerCount = 
sizeof(asT3B_DDRSetting80MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               case DDR_100_MHZ:
+                                       psDDRSetting = asT3B_DDRSetting100MHz;
+                                       registerCount = 
sizeof(asT3B_DDRSetting100MHz)
+                                               / sizeof(DDR_SETTING);
+                                       break;
+                               case DDR_133_MHZ:
 
-                               if(PLLConfig == PLL_266_MHZ)//266Mhz PLL 
selected.
-                               {
-                                       memcpy(asT3B_DDRSetting133MHz, 
asDPLL_266MHZ,
-                                                                        
sizeof(asDPLL_266MHZ));
-                                       psDDRSetting = asT3B_DDRSetting133MHz;
-                                       
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
-                                                                       
sizeof(DDR_SETTING));
-                               }
-                               else
-                               {
-                                       psDDRSetting = asT3B_DDRSetting133MHz;
-                                       
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
-                                                                       
sizeof(DDR_SETTING));
-                                       if(MipsConfig == MIPS_200_MHZ)
-                                       {
-                                               uiClockSetting = 0x07F13652;
+                                       if (vendorPLLConfig == PLL_266_MHZ) {
+                                               // 266Mhz PLL selected.
+                                               memcpy(asT3B_DDRSetting133MHz, 
asDPLL_266MHZ,
+                                                       sizeof(asDPLL_266MHZ));
+                                               psDDRSetting = 
asT3B_DDRSetting133MHz;
+                                               registerCount = 
sizeof(asT3B_DDRSetting133MHz)
+                                                       / sizeof(DDR_SETTING);
+
+                                       } else {
+                                               psDDRSetting = 
asT3B_DDRSetting133MHz;
+                                               registerCount = 
sizeof(asT3B_DDRSetting133MHz)
+                                                       / sizeof(DDR_SETTING);
+
+                                               if (vendorMipsConfig == 
MIPS_200_MHZ)
+                                                       uiClockSetting = 
0x07F13652;
+                                               else
+                                                       uiClockSetting = 
0x07F1365B;
                                        }
-                                       else
-                                       {
-                                               uiClockSetting = 0x07F1365B;
-                                       }
-                               }
-                               break;
-                   default:
-                           return -EINVAL;
+                                       break;
+                               default:
+                                       return -EINVAL;
+                       }
+                       break;
                }
-               break;
 
+               default:
+                       return -EINVAL;
        }
-       default:
-               return -EINVAL;
-       }
 
-       value=0;
-       TRACE("Debug: Register count is %lu\n", RegCount);
-       while(RegCount && !retval)
-       {
-               if(uiClockSetting && psDDRSetting->ulRegAddress == 
MIPS_CLOCK_REG)
-               {
+       value = 0;
+       TRACE("Debug: Register count is %lu\n", registerCount);
+       while (registerCount && !retval) {
+               if (uiClockSetting && psDDRSetting->ulRegAddress == 
MIPS_CLOCK_REG)
                        value = uiClockSetting;
-               }
                else
-               {
                        value = psDDRSetting->ulRegValue;
-               }
+
                retval = BizarroWriteRegister(psDDRSetting->ulRegAddress,
                        sizeof(value), (unsigned int*)&value);
 
-               if(B_OK != retval) {
+               if (B_OK != retval) {
                        TRACE_ALWAYS(
                                "%s:%d BizarroWriteRegister failed at 0x%x on 
Register #%d.\n",
-                                __FUNCTION__, __LINE__, 
psDDRSetting->ulRegAddress, RegCount);
+                               __FUNCTION__, __LINE__, 
psDDRSetting->ulRegAddress,
+                               registerCount);
                        break;
                }
 
-               RegCount--;
+               registerCount--;
                psDDRSetting++;
        }
 
-       if(ChipID >= 0xbece3300  )
-       {
+       if (chipID >= 0xbece3300) {
                snooze(3);
-               if( (ChipID != BCS220_2)&&
-                       (ChipID != BCS220_2BC)&&
-                       (ChipID != BCS220_3))
-               {
+               if ((chipID != BCS220_2)
+                       && (chipID != BCS220_2BC)
+                       && (chipID != BCS220_3)) {
                        /* drive MDDR to half in case of UMA-B: */
                        uiResetValue = 0x01010001;
                        retval = BizarroWriteRegister((unsigned int)0x0F007018,
                                sizeof(uiResetValue), &uiResetValue);
 
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroWriteRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
@@ -277,7 +250,7 @@
                        retval = BizarroWriteRegister((unsigned int)0x0F007094,
                                sizeof(uiResetValue), &uiResetValue);
 
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroWriteRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
@@ -286,7 +259,7 @@
                        retval = BizarroWriteRegister((unsigned int)0x0F00701c,
                                sizeof(uiResetValue), &uiResetValue);
 
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroWriteRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
@@ -295,7 +268,7 @@
                        retval = BizarroWriteRegister((unsigned int)0x0F007018,
                                sizeof(uiResetValue), &uiResetValue);
 
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroWriteRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
@@ -310,20 +283,19 @@
                 * UMA-B chip id. we will change this when we will have an
                 * internal PMU.
             */
-               if(PmuMode == HYBRID_MODE_7C)
-               {
+               if (vendorPmuMode == HYBRID_MODE_7C) {
                        TRACE("Debug: Hybrid Power Mode 7C\n");
                        retval = BizarroReadRegister((unsigned int)0x0f000c00,
                                sizeof(uiResetValue), &uiResetValue);
 
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
                        }
                        retval = BizarroReadRegister((unsigned int)0x0f000c00,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
@@ -331,21 +303,21 @@
                        uiResetValue = 0x1322a8;
                        retval = BizarroWriteRegister((unsigned int)0x0f000d1c,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroWriteRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
                        }
                        retval = BizarroReadRegister((unsigned int)0x0f000c00,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
                        }
                        retval = BizarroReadRegister((unsigned int)0x0f000c00,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
@@ -353,25 +325,24 @@
                        uiResetValue = 0x132296;
                        retval = BizarroWriteRegister((unsigned int)0x0f000d14,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroWriteRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
                        }
-               }
-               else if(PmuMode == HYBRID_MODE_6 )
-               {
+               } else if (vendorPmuMode == HYBRID_MODE_6) {
+
                        TRACE("Debug: Hybrid Power Mode 6\n");
                        retval = BizarroReadRegister((unsigned int)0x0f000c00,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
                        }
                        retval = BizarroReadRegister((unsigned int)0x0f000c00,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
@@ -379,21 +350,21 @@
                        uiResetValue = 0x6003229a;
                        retval = BizarroWriteRegister((unsigned int)0x0f000d14,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroWriteRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
                        }
                        retval = BizarroReadRegister((unsigned int)0x0f000c00,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
                        }
                        retval = BizarroReadRegister((unsigned int)0x0f000c00,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroReadRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;
@@ -401,7 +372,7 @@
                        uiResetValue = 0x1322a8;
                        retval = BizarroWriteRegister((unsigned int)0x0f000d1c,
                                sizeof(uiResetValue), &uiResetValue);
-                       if(retval < 0) {
+                       if (retval < 0) {
                                TRACE_ALWAYS("%s:%d BizarroWriteRegister 
failed\n",
                                        __FUNCTION__, __LINE__);
                                return retval;

Modified: 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.h
===================================================================
--- 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.h  
    2011-03-06 16:57:59 UTC (rev 40849)
+++ 
haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.h  
    2011-03-06 18:26:19 UTC (rev 40850)
@@ -2,50 +2,55 @@
  *     Beceem WiMax USB Driver.
  *     Copyright (c) 2010 Alexander von Gluck <kallisti5@xxxxxxxxxxx>
  *     Distributed under the terms of the GNU General Public License.
- *     
+ *
  *     Based on GPL code developed by: Beceem Communications Pvt. Ltd
- *     
+ *
  *     Description: Wrangle Beceem volatile DDR memory.
  */
-
 #ifndef _USB_BECEEM_DDR_H_
 #define _USB_BECEEM_DDR_H_
 
+
 #include <ByteOrder.h>
-
 #include "DeviceStruct.h"
 
-#define DDR_DUMP_INTERNAL_DEVICE_MEMORY                0xBFC02B00
-#define MIPS_CLOCK_REG                                         0x0f000820
 
-#define MIPS_200_MHZ   0
-#define MIPS_160_MHZ   1
-#define PLL_800_MHZ            0
-#define PLL_266_MHZ            1
+#define DDR_DUMP_INTERNAL_DEVICE_MEMORY        0xBFC02B00
+#define MIPS_CLOCK_REG 0x0f000820
 
-#define DDR_80_MHZ      0
-#define DDR_100_MHZ     1
-#define DDR_120_MHZ     2 //  Additional Frequency for T3LP
-#define DDR_133_MHZ     3
-#define DDR_140_MHZ     4 //  Not Used (Reserved for future)
-#define DDR_160_MHZ     5 //  Additional Frequency for T3LP
-#define DDR_180_MHZ     6 //  Not Used (Reserved for future)
-#define DDR_200_MHZ     7 //  Not Used (Reserved for future)
+#define MIPS_200_MHZ 0
+#define MIPS_160_MHZ 1
+#define PLL_800_MHZ    0
+#define PLL_266_MHZ    1
 
-class BeceemDDR
-{
+#define DDR_80_MHZ 0
+#define DDR_100_MHZ 1
+#define DDR_120_MHZ 2 //  Additional Frequency for T3LP
+#define DDR_133_MHZ 3
+#define DDR_140_MHZ 4 //  Not Used (Reserved for future)
+#define DDR_160_MHZ 5 //  Additional Frequency for T3LP
+#define DDR_180_MHZ 6 //  Not Used (Reserved for future)
+#define DDR_200_MHZ 7 //  Not Used (Reserved for future)
 
+
+class BeceemDDR {
 public:
-               WIMAX_DEVICE*   pwmxdevice;
+                                                               BeceemDDR();
+                       status_t                        DDRInit(WIMAX_DEVICE* 
swmxdevice);
 
-                                               BeceemDDR();
-               status_t                DDRInit(WIMAX_DEVICE* swmxdevice);
+                       WIMAX_DEVICE*           fWmxDevice;
 
-// yuck.  These are in a child class class
-virtual status_t    ReadRegister(unsigned int reg, size_t size, uint32_t* 
buffer){ return NULL; };
-virtual status_t    WriteRegister(unsigned int reg, size_t size, uint32_t* 
buffer){ return NULL; };
-virtual status_t    BizarroReadRegister(unsigned int reg, size_t size, 
uint32_t* buffer){ return NULL; };
-virtual status_t    BizarroWriteRegister(unsigned int reg, size_t size, 
uint32_t* buffer){ return NULL; };
+       // yuck.  These are in a child class class
+       virtual status_t                        ReadRegister(unsigned int reg, 
size_t size,
+                                                                       
uint32_t* buffer) { return NULL; };
+       virtual status_t                        WriteRegister(unsigned int reg, 
size_t size,
+                                                                       
uint32_t* buffer) { return NULL; };
+       virtual status_t                        BizarroReadRegister(unsigned 
int reg,
+                                                                       size_t 
size, uint32_t* buffer)
+                                                                               
{ return NULL; };
+       virtual status_t                        BizarroWriteRegister(unsigned 
int reg,
+                                                                       size_t 
size, uint32_t* buffer)
+                                                                               
{ return NULL; };
 
 };
 
@@ -60,793 +65,807 @@
        HYBRID_MODE_6   = 2
 }PMU_MODE;
 
+
 /*
  * DDR Init maps, taken from Beceem GPL Linux Driver
  */
-
 typedef struct _DDR_SETTING
 {
-       unsigned long   ulRegAddress;
-    unsigned long      ulRegValue;
-}DDR_SETTING, *PDDR_SETTING;
+       unsigned long ulRegAddress;
+       unsigned long ulRegValue;
+} DDR_SETTING, *PDDR_SETTING;
+
+
 typedef DDR_SETTING DDR_SET_NODE, *PDDR_SET_NODE;
 
-//DDR INIT-133Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12  //index for 0x0F007000
-static DDR_SET_NODE asT3_DDRSetting133MHz[]= {//      # DPLL Clock Setting
-                                        {0x0F000800,0x00007212},
-                                        {0x0f000820,0x07F13FFF},
-                                        {0x0f000810,0x00000F95},
-                                        {0x0f000860,0x00000000},
-                                        {0x0f000880,0x000003DD},
-                                        // Changed source for X-bar and MIPS 
clock to APLL
-                                        {0x0f000840,0x0FFF1B00},
-                                        {0x0f000870,0x00000002},
-                                        {0x0F00a044,0x1fffffff},
-                                        {0x0F00a040,0x1f000000},
-                                        {0x0F00a084,0x1Cffffff},
-                                        {0x0F00a080,0x1C000000},
-                                        {0x0F00a04C,0x0000000C},
-                                        //Memcontroller Default values
-                                        {0x0F007000,0x00010001},
-                                        {0x0F007004,0x01010100},
-                                        {0x0F007008,0x01000001},
-                                        {0x0F00700c,0x00000000},
-                                        {0x0F007010,0x01000000},
-                                        {0x0F007014,0x01000100},
-                                        {0x0F007018,0x01000000},
-                                        {0x0F00701c,0x01020001},// POP - 
0x00020001 Normal 0x01020001
-                                        {0x0F007020,0x04030107}, //Normal - 
0x04030107 POP - 0x05030107
-                                        {0x0F007024,0x02000007},
-                                        {0x0F007028,0x02020202},
-                                        {0x0F00702c,0x0206060a},//ROB- 
0x0205050a,//0x0206060a
-                                        {0x0F007030,0x05000000},
-                                        {0x0F007034,0x00000003},
-                                        {0x0F007038,0x110a0200},//ROB - 
0x110a0200,//0x180a0200,// 0x1f0a0200
-                                        {0x0F00703C,0x02101010},//ROB - 
0x02101010,//0x02101018},
-                                        {0x0F007040,0x45751200},//ROB - 
0x45751200,//0x450f1200},
-                                        {0x0F007044,0x110a0d00},//ROB - 
0x110a0d00//0x111f0d00
-                                        {0x0F007048,0x081b0306},
-                                        {0x0F00704c,0x00000000},
-                                        {0x0F007050,0x0000001c},
-                                        {0x0F007054,0x00000000},
-                                        {0x0F007058,0x00000000},
-                                        {0x0F00705c,0x00000000},
-                                        {0x0F007060,0x0010246c},
-                                        {0x0F007064,0x00000010},
-                                        {0x0F007068,0x00000000},
-                                        {0x0F00706c,0x00000001},
-                                        {0x0F007070,0x00007000},
-                                        {0x0F007074,0x00000000},
-                                        {0x0F007078,0x00000000},
-                                        {0x0F00707C,0x00000000},
-                                        {0x0F007080,0x00000000},
-                                        {0x0F007084,0x00000000},
-                                        //# Enable BW improvement within 
memory controller
-                                        {0x0F007094,0x00000104},
-                                        //# Enable 2 ports within X-bar
-                                        {0x0F00A000,0x00000016},
-                                        //# Enable start bit within memory 
controller
-                                        {0x0F007018,0x01010000}
-                                        };
-//80Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10  //index for 0x0F007000
-static DDR_SET_NODE asT3_DDRSetting80MHz[]= {//   # DPLL Clock Setting
-                                        {0x0f000810,0x00000F95},
-                                        {0x0f000820,0x07f1ffff},
-                                        {0x0f000860,0x00000000},
-                                        {0x0f000880,0x000003DD},
-                                        {0x0F00a044,0x1fffffff},
-                                        {0x0F00a040,0x1f000000},
-                                        {0x0F00a084,0x1Cffffff},
-                                        {0x0F00a080,0x1C000000},
-                                        {0x0F00a000,0x00000016},
-                                        {0x0F00a04C,0x0000000C},
-                                //Memcontroller Default values
-                                        {0x0F007000,0x00010001},
-                                        {0x0F007004,0x01000000},
-                                        {0x0F007008,0x01000001},
-                                        {0x0F00700c,0x00000000},
-                                        {0x0F007010,0x01000000},
-                                        {0x0F007014,0x01000100},
-                                        {0x0F007018,0x01000000},
-                                        {0x0F00701c,0x01020000},
-                                        {0x0F007020,0x04020107},
-                                        {0x0F007024,0x00000007},
-                                        {0x0F007028,0x02020201},
-                                        {0x0F00702c,0x0204040a},
-                                        {0x0F007030,0x04000000},
-                                        {0x0F007034,0x00000002},
-                                        {0x0F007038,0x1F060200},
-                                        {0x0F00703C,0x1C22221F},
-                                        {0x0F007040,0x8A006600},
-                                        {0x0F007044,0x221a0800},
-                                        {0x0F007048,0x02690204},
-                                        {0x0F00704c,0x00000000},
-                                        {0x0F007050,0x0000001c},
-                                        {0x0F007054,0x00000000},
-                                        {0x0F007058,0x00000000},
-                                        {0x0F00705c,0x00000000},
-                                        {0x0F007060,0x000A15D6},
-                                        {0x0F007064,0x0000000A},
-                                        {0x0F007068,0x00000000},
-                                        {0x0F00706c,0x00000001},
-                                        {0x0F007070,0x00004000},
-                                        {0x0F007074,0x00000000},
-                                        {0x0F007078,0x00000000},
-                                        {0x0F00707C,0x00000000},
-                                        {0x0F007080,0x00000000},
-                                        {0x0F007084,0x00000000},
-                                        {0x0F007094,0x00000104},
-                                        //# Enable start bit within memory 
controller
-                                                                               
{0x0F007018,0x01010000}
-                                };
-//100Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13  //index for 0x0F007000
-static DDR_SET_NODE asT3_DDRSetting100MHz[]= {//  # DPLL Clock Setting
-                                        {0x0F000800,0x00007008},
-                                        {0x0f000810,0x00000F95},
-                                        {0x0f000820,0x07F13E3F},
-                                        {0x0f000860,0x00000000},
-                                        {0x0f000880,0x000003DD},
-                                // Changed source for X-bar and MIPS clock to 
APLL
-                                //0x0f000840,0x0FFF1800,
-                                        {0x0f000840,0x0FFF1B00},
-                                        {0x0f000870,0x00000002},
-                                        {0x0F00a044,0x1fffffff},
-                                        {0x0F00a040,0x1f000000},
-                                        {0x0F00a084,0x1Cffffff},
-                                        {0x0F00a080,0x1C000000},
-                                        {0x0F00a04C,0x0000000C},
-                                //# Enable 2 ports within X-bar
-                                        {0x0F00A000,0x00000016},
-                                //Memcontroller Default values
-                                        {0x0F007000,0x00010001},
-                                        {0x0F007004,0x01010100},
-                                        {0x0F007008,0x01000001},
-                                        {0x0F00700c,0x00000000},
-                                        {0x0F007010,0x01000000},
-                                        {0x0F007014,0x01000100},
-                                        {0x0F007018,0x01000000},
-                                        {0x0F00701c,0x01020001}, // POP - 
0x00020000 Normal 0x01020000
-                                        {0x0F007020,0x04020107},//Normal - 
0x04030107 POP - 0x05030107
-                                        {0x0F007024,0x00000007},
-                                        {0x0F007028,0x01020201},
-                                        {0x0F00702c,0x0204040A},
-                                        {0x0F007030,0x06000000},
-                                        {0x0F007034,0x00000004},
-                                        {0x0F007038,0x20080200},
-                                        {0x0F00703C,0x02030320},
-                                        {0x0F007040,0x6E7F1200},
-                                        {0x0F007044,0x01190A00},
-                                        {0x0F007048,0x06120305},//0x02690204 
// 0x06120305
-                                        {0x0F00704c,0x00000000},
-                                        {0x0F007050,0x0000001C},
-                                        {0x0F007054,0x00000000},
-                                        {0x0F007058,0x00000000},
-                                        {0x0F00705c,0x00000000},
-                                        {0x0F007060,0x00082ED6},
-                                        {0x0F007064,0x0000000A},
-                                        {0x0F007068,0x00000000},
-                                        {0x0F00706c,0x00000001},
-                                        {0x0F007070,0x00005000},
-                                        {0x0F007074,0x00000000},
-                                        {0x0F007078,0x00000000},
-                                        {0x0F00707C,0x00000000},
-                                        {0x0F007080,0x00000000},
-                                        {0x0F007084,0x00000000},
-                                //# Enable BW improvement within memory 
controller
-                                        {0x0F007094,0x00000104},
-                                //# Enable start bit within memory controller
-                                        {0x0F007018,0x01010000}
-                                };
 
-//Net T3B DDR Settings
-//DDR INIT-133Mhz
+// DDR INIT 133Mhz
+#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12  // index for 0x0F007000
+static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// DPLL Clock Setting
+       {0x0F000800, 0x00007212},
+       {0x0f000820, 0x07F13FFF},
+       {0x0f000810, 0x00000F95},
+       {0x0f000860, 0x00000000},

[... truncated: 1358 lines follow ...]

Other related posts:

  • » [haiku-commits] r40850 - haiku/trunk/src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx - kallisti5