[haiku-commits] r37038 - haiku/vendor/freebsd/current/dev/re
- From: korli@xxxxxxxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Sun, 6 Jun 2010 19:21:29 +0200 (CEST)
Author: korli
Date: 2010-06-06 19:21:29 +0200 (Sun, 06 Jun 2010)
New Revision: 37038
Changeset: http://dev.haiku-os.org/changeset/37038/haiku
Added:
haiku/vendor/freebsd/current/dev/re/if_re.c
haiku/vendor/freebsd/current/dev/re/if_rlreg.h
Log:
adding current revisions of if_re from FreeBSD
Added: haiku/vendor/freebsd/current/dev/re/if_re.c
===================================================================
--- haiku/vendor/freebsd/current/dev/re/if_re.c (rev 0)
+++ haiku/vendor/freebsd/current/dev/re/if_re.c 2010-06-06 17:21:29 UTC (rev
37038)
@@ -0,0 +1,3048 @@
+/*-
+ * Copyright (c) 1997, 1998-2003
+ * Bill Paul <wpaul@xxxxxxxxxxxxx>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.95.2.36 2008/09/19 03:36:53
yongari Exp $");
+
+/*
+ * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
+ *
+ * Written by Bill Paul <wpaul@xxxxxxxxxxxxx>
+ * Senior Networking Software Engineer
+ * Wind River Systems
+ */
+
+/*
+ * This driver is designed to support RealTek's next generation of
+ * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
+ * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
+ * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
+ *
+ * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
+ * with the older 8139 family, however it also supports a special
+ * C+ mode of operation that provides several new performance enhancing
+ * features. These include:
+ *
+ * o Descriptor based DMA mechanism. Each descriptor represents
+ * a single packet fragment. Data buffers may be aligned on
+ * any byte boundary.
+ *
+ * o 64-bit DMA
+ *
+ * o TCP/IP checksum offload for both RX and TX
+ *
+ * o High and normal priority transmit DMA rings
+ *
+ * o VLAN tag insertion and extraction
+ *
+ * o TCP large send (segmentation offload)
+ *
+ * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
+ * programming API is fairly straightforward. The RX filtering, EEPROM
+ * access and PHY access is the same as it is on the older 8139 series
+ * chips.
+ *
+ * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
+ * same programming API and feature set as the 8139C+ with the following
+ * differences and additions:
+ *
+ * o 1000Mbps mode
+ *
+ * o Jumbo frames
+ *
+ * o GMII and TBI ports/registers for interfacing with copper
+ * or fiber PHYs
+ *
+ * o RX and TX DMA rings can have up to 1024 descriptors
+ * (the 8139C+ allows a maximum of 64)
+ *
+ * o Slight differences in register layout from the 8139C+
+ *
+ * The TX start and timer interrupt registers are at different locations
+ * on the 8169 than they are on the 8139C+. Also, the status word in the
+ * RX descriptor has a slightly different bit layout. The 8169 does not
+ * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
+ * copper gigE PHY.
+ *
+ * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
+ * (the 'S' stands for 'single-chip'). These devices have the same
+ * programming API as the older 8169, but also have some vendor-specific
+ * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
+ * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
+ *
+ * This driver takes advantage of the RX and TX checksum offload and
+ * VLAN tag insertion/extraction features. It also implements TX
+ * interrupt moderation using the timer interrupt registers, which
+ * significantly reduces TX interrupt load. There is also support
+ * for jumbo frames, however the 8169/8169S/8110S can not transmit
+ * jumbo frames larger than 7440, so the max MTU possible with this
+ * driver is 7422 bytes.
+ */
+
+#ifdef HAVE_KERNEL_OPTION_HEADERS
+#include "opt_device_polling.h"
+#endif
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/taskqueue.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
+
+#include <net/bpf.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <pci/if_rlreg.h>
+
+MODULE_DEPEND(re, pci, 1, 1, 1);
+MODULE_DEPEND(re, ether, 1, 1, 1);
+MODULE_DEPEND(re, miibus, 1, 1, 1);
+
+/* "device miibus" required. See GENERIC if you get errors here. */
+#include "miibus_if.h"
+
+/* Tunables. */
+static int msi_disable = 1;
+TUNABLE_INT("hw.re.msi_disable", &msi_disable);
+
+#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
+
+/*
+ * Various supported device vendors/types and their names.
+ */
+static struct rl_type re_devs[] = {
+ { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
+ "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
+ { RT_VENDORID, RT_DEVICEID_8139, 0,
+ "RealTek 8139C+ 10/100BaseTX" },
+ { RT_VENDORID, RT_DEVICEID_8101E, 0,
+ "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" },
+ { RT_VENDORID, RT_DEVICEID_8168, 0,
+ "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe "
+ "Gigabit Ethernet" },
+ { RT_VENDORID, RT_DEVICEID_8169, 0,
+ "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
+ { RT_VENDORID, RT_DEVICEID_8169SC, 0,
+ "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
+ { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
+ "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
+ { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
+ "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
+ { USR_VENDORID, USR_DEVICEID_997902, 0,
+ "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
+};
+
+static struct rl_hwrev re_hwrevs[] = {
+ { RL_HWREV_8139, RL_8139, "" },
+ { RL_HWREV_8139A, RL_8139, "A" },
+ { RL_HWREV_8139AG, RL_8139, "A-G" },
+ { RL_HWREV_8139B, RL_8139, "B" },
+ { RL_HWREV_8130, RL_8139, "8130" },
+ { RL_HWREV_8139C, RL_8139, "C" },
+ { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
+ { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
+ { RL_HWREV_8168_SPIN1, RL_8169, "8168"},
+ { RL_HWREV_8169, RL_8169, "8169"},
+ { RL_HWREV_8169S, RL_8169, "8169S"},
+ { RL_HWREV_8110S, RL_8169, "8110S"},
+ { RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
+ { RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
+ { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"},
+ { RL_HWREV_8100, RL_8139, "8100"},
+ { RL_HWREV_8101, RL_8139, "8101"},
+ { RL_HWREV_8100E, RL_8169, "8100E"},
+ { RL_HWREV_8101E, RL_8169, "8101E"},
+ { RL_HWREV_8102E, RL_8169, "8102E"},
+ { RL_HWREV_8102EL, RL_8169, "8102EL"},
+ { RL_HWREV_8168_SPIN2, RL_8169, "8168"},
+ { RL_HWREV_8168_SPIN3, RL_8169, "8168"},
+ { RL_HWREV_8168C, RL_8169, "8168C/8111C"},
+ { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"},
+ { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"},
+ { 0, 0, NULL }
+};
+
+static int re_probe (device_t);
+static int re_attach (device_t);
+static int re_detach (device_t);
+
+static int re_encap (struct rl_softc *, struct mbuf **);
+
+static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
+static int re_allocmem (device_t, struct rl_softc *);
+static __inline void re_discard_rxbuf
+ (struct rl_softc *, int);
+static int re_newbuf (struct rl_softc *, int);
+static int re_rx_list_init (struct rl_softc *);
+static int re_tx_list_init (struct rl_softc *);
+#ifdef RE_FIXUP_RX
+static __inline void re_fixup_rx
+ (struct mbuf *);
+#endif
+static int re_rxeof (struct rl_softc *);
+static void re_txeof (struct rl_softc *);
+#ifdef DEVICE_POLLING
+static void re_poll (struct ifnet *, enum poll_cmd, int);
+static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
+#endif
+static int re_intr (void *);
+static void re_tick (void *);
+static void re_tx_task (void *, int);
+static void re_int_task (void *, int);
+static void re_start (struct ifnet *);
+static int re_ioctl (struct ifnet *, u_long, caddr_t);
+static void re_init (void *);
+static void re_init_locked (struct rl_softc *);
+static void re_stop (struct rl_softc *);
+static void re_watchdog (struct rl_softc *);
+static int re_suspend (device_t);
+static int re_resume (device_t);
+static int re_shutdown (device_t);
+static int re_ifmedia_upd (struct ifnet *);
+static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
+
+static void re_eeprom_putbyte (struct rl_softc *, int);
+static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
+static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
+static int re_gmii_readreg (device_t, int, int);
+static int re_gmii_writereg (device_t, int, int, int);
+
+static int re_miibus_readreg (device_t, int, int);
+static int re_miibus_writereg (device_t, int, int, int);
+static void re_miibus_statchg (device_t);
+
+static void re_setmulti (struct rl_softc *);
+static void re_reset (struct rl_softc *);
+static void re_setwol (struct rl_softc *);
+static void re_clrwol (struct rl_softc *);
+
+#ifdef RE_DIAG
+static int re_diag (struct rl_softc *);
+#endif
+
+static device_method_t re_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, re_probe),
+ DEVMETHOD(device_attach, re_attach),
+ DEVMETHOD(device_detach, re_detach),
+ DEVMETHOD(device_suspend, re_suspend),
+ DEVMETHOD(device_resume, re_resume),
+ DEVMETHOD(device_shutdown, re_shutdown),
+
+ /* bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, re_miibus_readreg),
+ DEVMETHOD(miibus_writereg, re_miibus_writereg),
+ DEVMETHOD(miibus_statchg, re_miibus_statchg),
+
+ { 0, 0 }
+};
+
+static driver_t re_driver = {
+ "re",
+ re_methods,
+ sizeof(struct rl_softc)
+};
+
+static devclass_t re_devclass;
+
+DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
+DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
+DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
+
+#define EE_SET(x) \
+ CSR_WRITE_1(sc, RL_EECMD, \
+ CSR_READ_1(sc, RL_EECMD) | x)
+
+#define EE_CLR(x) \
+ CSR_WRITE_1(sc, RL_EECMD, \
+ CSR_READ_1(sc, RL_EECMD) & ~x)
+
+/*
+ * Send a read command and address to the EEPROM, check for ACK.
+ */
+static void
+re_eeprom_putbyte(struct rl_softc *sc, int addr)
+{
+ int d, i;
+
+ d = addr | (RL_9346_READ << sc->rl_eewidth);
+
+ /*
+ * Feed in each bit and strobe the clock.
+ */
+
+ for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
+ if (d & i) {
+ EE_SET(RL_EE_DATAIN);
+ } else {
+ EE_CLR(RL_EE_DATAIN);
+ }
+ DELAY(100);
+ EE_SET(RL_EE_CLK);
+ DELAY(150);
+ EE_CLR(RL_EE_CLK);
+ DELAY(100);
+ }
+}
+
+/*
+ * Read a word of data stored in the EEPROM at address 'addr.'
+ */
+static void
+re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
+{
+ int i;
+ u_int16_t word = 0;
+
+ /*
+ * Send address of word we want to read.
+ */
+ re_eeprom_putbyte(sc, addr);
+
+ /*
+ * Start reading bits from EEPROM.
+ */
+ for (i = 0x8000; i; i >>= 1) {
+ EE_SET(RL_EE_CLK);
+ DELAY(100);
+ if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
+ word |= i;
+ EE_CLR(RL_EE_CLK);
+ DELAY(100);
+ }
+
+ *dest = word;
+}
+
+/*
+ * Read a sequence of words from the EEPROM.
+ */
+static void
+re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
+{
+ int i;
+ u_int16_t word = 0, *ptr;
+
+ CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
+
+ DELAY(100);
+
+ for (i = 0; i < cnt; i++) {
+ CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
+ re_eeprom_getword(sc, off + i, &word);
+ CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
+ ptr = (u_int16_t *)(dest + (i * 2));
+ *ptr = word;
+ }
+
+ CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
+}
+
+static int
+re_gmii_readreg(device_t dev, int phy, int reg)
+{
+ struct rl_softc *sc;
+ u_int32_t rval;
+ int i;
+
+ if (phy != 1)
+ return (0);
+
+ sc = device_get_softc(dev);
+
+ /* Let the rgephy driver read the GMEDIASTAT register */
+
+ if (reg == RL_GMEDIASTAT) {
+ rval = CSR_READ_1(sc, RL_GMEDIASTAT);
+ return (rval);
+ }
+
+ CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
+ DELAY(1000);
+
+ for (i = 0; i < RL_TIMEOUT; i++) {
+ rval = CSR_READ_4(sc, RL_PHYAR);
+ if (rval & RL_PHYAR_BUSY)
+ break;
+ DELAY(100);
+ }
+
+ if (i == RL_TIMEOUT) {
+ device_printf(sc->rl_dev, "PHY read failed\n");
+ return (0);
+ }
+
+ return (rval & RL_PHYAR_PHYDATA);
+}
+
+static int
+re_gmii_writereg(device_t dev, int phy, int reg, int data)
+{
+ struct rl_softc *sc;
+ u_int32_t rval;
+ int i;
+
+ sc = device_get_softc(dev);
+
+ CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
+ (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
+ DELAY(1000);
+
+ for (i = 0; i < RL_TIMEOUT; i++) {
+ rval = CSR_READ_4(sc, RL_PHYAR);
+ if (!(rval & RL_PHYAR_BUSY))
+ break;
+ DELAY(100);
+ }
+
+ if (i == RL_TIMEOUT) {
+ device_printf(sc->rl_dev, "PHY write failed\n");
+ return (0);
+ }
+
+ return (0);
+}
+
+static int
+re_miibus_readreg(device_t dev, int phy, int reg)
+{
+ struct rl_softc *sc;
+ u_int16_t rval = 0;
+ u_int16_t re8139_reg = 0;
+
+ sc = device_get_softc(dev);
+
+ if (sc->rl_type == RL_8169) {
+ rval = re_gmii_readreg(dev, phy, reg);
+ return (rval);
+ }
+
+ /* Pretend the internal PHY is only at address 0 */
+ if (phy) {
+ return (0);
+ }
+ switch (reg) {
+ case MII_BMCR:
+ re8139_reg = RL_BMCR;
+ break;
+ case MII_BMSR:
+ re8139_reg = RL_BMSR;
+ break;
+ case MII_ANAR:
+ re8139_reg = RL_ANAR;
+ break;
+ case MII_ANER:
+ re8139_reg = RL_ANER;
+ break;
+ case MII_ANLPAR:
+ re8139_reg = RL_LPAR;
+ break;
+ case MII_PHYIDR1:
+ case MII_PHYIDR2:
+ return (0);
+ /*
+ * Allow the rlphy driver to read the media status
+ * register. If we have a link partner which does not
+ * support NWAY, this is the register which will tell
+ * us the results of parallel detection.
+ */
+ case RL_MEDIASTAT:
+ rval = CSR_READ_1(sc, RL_MEDIASTAT);
+ return (rval);
+ default:
+ device_printf(sc->rl_dev, "bad phy register\n");
+ return (0);
+ }
+ rval = CSR_READ_2(sc, re8139_reg);
+ if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
+ /* 8139C+ has different bit layout. */
+ rval &= ~(BMCR_LOOP | BMCR_ISO);
+ }
+ return (rval);
+}
+
+static int
+re_miibus_writereg(device_t dev, int phy, int reg, int data)
+{
+ struct rl_softc *sc;
+ u_int16_t re8139_reg = 0;
+ int rval = 0;
+
+ sc = device_get_softc(dev);
+
+ if (sc->rl_type == RL_8169) {
+ rval = re_gmii_writereg(dev, phy, reg, data);
+ return (rval);
+ }
+
+ /* Pretend the internal PHY is only at address 0 */
+ if (phy)
+ return (0);
+
+ switch (reg) {
+ case MII_BMCR:
+ re8139_reg = RL_BMCR;
+ if (sc->rl_type == RL_8139CPLUS) {
+ /* 8139C+ has different bit layout. */
+ data &= ~(BMCR_LOOP | BMCR_ISO);
+ }
+ break;
+ case MII_BMSR:
+ re8139_reg = RL_BMSR;
+ break;
+ case MII_ANAR:
+ re8139_reg = RL_ANAR;
+ break;
+ case MII_ANER:
+ re8139_reg = RL_ANER;
+ break;
+ case MII_ANLPAR:
+ re8139_reg = RL_LPAR;
+ break;
+ case MII_PHYIDR1:
+ case MII_PHYIDR2:
+ return (0);
+ break;
+ default:
+ device_printf(sc->rl_dev, "bad phy register\n");
+ return (0);
+ }
+ CSR_WRITE_2(sc, re8139_reg, data);
+ return (0);
+}
+
+static void
+re_miibus_statchg(device_t dev)
+{
+
+}
+
+/*
+ * Program the 64-bit multicast hash filter.
+ */
+static void
+re_setmulti(struct rl_softc *sc)
+{
+ struct ifnet *ifp;
+ int h = 0;
+ u_int32_t hashes[2] = { 0, 0 };
+ struct ifmultiaddr *ifma;
+ u_int32_t rxfilt;
+ int mcnt = 0;
+
+ RL_LOCK_ASSERT(sc);
+
+ ifp = sc->rl_ifp;
+
+
+ rxfilt = CSR_READ_4(sc, RL_RXCFG);
+ rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI);
+ if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
+ if (ifp->if_flags & IFF_PROMISC)
+ rxfilt |= RL_RXCFG_RX_ALLPHYS;
+ /*
+ * Unlike other hardwares, we have to explicitly set
+ * RL_RXCFG_RX_MULTI to receive multicast frames in
+ * promiscuous mode.
+ */
+ rxfilt |= RL_RXCFG_RX_MULTI;
+ CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
+ CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
+ CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
+ return;
+ }
+
+ /* first, zot all the existing hash bits */
+ CSR_WRITE_4(sc, RL_MAR0, 0);
+ CSR_WRITE_4(sc, RL_MAR4, 0);
+
+ /* now program new ones */
+ IF_ADDR_LOCK(ifp);
+ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+ h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
+ ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
+ if (h < 32)
+ hashes[0] |= (1 << h);
+ else
+ hashes[1] |= (1 << (h - 32));
+ mcnt++;
+ }
+ IF_ADDR_UNLOCK(ifp);
+
+ if (mcnt)
+ rxfilt |= RL_RXCFG_RX_MULTI;
+ else
+ rxfilt &= ~RL_RXCFG_RX_MULTI;
+
+ CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
+
+ /*
+ * For some unfathomable reason, RealTek decided to reverse
+ * the order of the multicast hash registers in the PCI Express
+ * parts. This means we have to write the hash pattern in reverse
+ * order for those devices.
+ */
+
+ if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) {
+ CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1]));
+ CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0]));
+ } else {
+ CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
+ CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
+ }
+}
+
+static void
+re_reset(struct rl_softc *sc)
+{
+ int i;
+
+ RL_LOCK_ASSERT(sc);
+
+ CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
+
+ for (i = 0; i < RL_TIMEOUT; i++) {
+ DELAY(10);
+ if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
+ break;
+ }
+ if (i == RL_TIMEOUT)
+ device_printf(sc->rl_dev, "reset never completed!\n");
+
+ CSR_WRITE_1(sc, 0x82, 1);
+}
+
+#ifdef RE_DIAG
+
+/*
+ * The following routine is designed to test for a defect on some
+ * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
+ * lines connected to the bus, however for a 32-bit only card, they
+ * should be pulled high. The result of this defect is that the
+ * NIC will not work right if you plug it into a 64-bit slot: DMA
+ * operations will be done with 64-bit transfers, which will fail
+ * because the 64-bit data lines aren't connected.
+ *
+ * There's no way to work around this (short of talking a soldering
+ * iron to the board), however we can detect it. The method we use
+ * here is to put the NIC into digital loopback mode, set the receiver
+ * to promiscuous mode, and then try to send a frame. We then compare
+ * the frame data we sent to what was received. If the data matches,
+ * then the NIC is working correctly, otherwise we know the user has
+ * a defective NIC which has been mistakenly plugged into a 64-bit PCI
+ * slot. In the latter case, there's no way the NIC can work correctly,
+ * so we print out a message on the console and abort the device attach.
+ */
+
+static int
+re_diag(struct rl_softc *sc)
+{
+ struct ifnet *ifp = sc->rl_ifp;
+ struct mbuf *m0;
+ struct ether_header *eh;
+ struct rl_desc *cur_rx;
+ u_int16_t status;
+ u_int32_t rxstat;
+ int total_len, i, error = 0, phyaddr;
+ u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
+ u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
+
+ /* Allocate a single mbuf */
+ MGETHDR(m0, M_DONTWAIT, MT_DATA);
+ if (m0 == NULL)
+ return (ENOBUFS);
+
+ RL_LOCK(sc);
+
+ /*
+ * Initialize the NIC in test mode. This sets the chip up
+ * so that it can send and receive frames, but performs the
+ * following special functions:
+ * - Puts receiver in promiscuous mode
+ * - Enables digital loopback mode
+ * - Leaves interrupts turned off
+ */
+
+ ifp->if_flags |= IFF_PROMISC;
+ sc->rl_testmode = 1;
+ re_reset(sc);
+ re_init_locked(sc);
+ sc->rl_flags |= RL_FLAG_LINK;
+ if (sc->rl_type == RL_8169)
+ phyaddr = 1;
+ else
+ phyaddr = 0;
+
+ re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
+ for (i = 0; i < RL_TIMEOUT; i++) {
+ status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
+ if (!(status & BMCR_RESET))
+ break;
+ }
+
+ re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
+ CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
+
+ DELAY(100000);
+
+ /* Put some data in the mbuf */
+
+ eh = mtod(m0, struct ether_header *);
+ bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
+ bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
+ eh->ether_type = htons(ETHERTYPE_IP);
+ m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
+
+ /*
+ * Queue the packet, start transmission.
+ * Note: IF_HANDOFF() ultimately calls re_start() for us.
+ */
+
+ CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
+ RL_UNLOCK(sc);
+ /* XXX: re_diag must not be called when in ALTQ mode */
+ IF_HANDOFF(&ifp->if_snd, m0, ifp);
+ RL_LOCK(sc);
+ m0 = NULL;
+
+ /* Wait for it to propagate through the chip */
+
+ DELAY(100000);
+ for (i = 0; i < RL_TIMEOUT; i++) {
+ status = CSR_READ_2(sc, RL_ISR);
+ CSR_WRITE_2(sc, RL_ISR, status);
+ if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
+ (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
+ break;
+ DELAY(10);
+ }
+
+ if (i == RL_TIMEOUT) {
+ device_printf(sc->rl_dev,
+ "diagnostic failed, failed to receive packet in"
+ " loopback mode\n");
+ error = EIO;
+ goto done;
+ }
+
+ /*
+ * The packet should have been dumped into the first
+ * entry in the RX DMA ring. Grab it from there.
+ */
+
+ bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
+ sc->rl_ldata.rl_rx_list_map,
+ BUS_DMASYNC_POSTREAD);
+ bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
+ sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
+ BUS_DMASYNC_POSTREAD);
+ bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
+ sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
+
+ m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
+ sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
+ eh = mtod(m0, struct ether_header *);
+
+ cur_rx = &sc->rl_ldata.rl_rx_list[0];
+ total_len = RL_RXBYTES(cur_rx);
+ rxstat = le32toh(cur_rx->rl_cmdstat);
+
+ if (total_len != ETHER_MIN_LEN) {
+ device_printf(sc->rl_dev,
+ "diagnostic failed, received short packet\n");
+ error = EIO;
+ goto done;
+ }
+
+ /* Test that the received packet data matches what we sent. */
+
+ if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
+ bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
+ ntohs(eh->ether_type) != ETHERTYPE_IP) {
+ device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
+ device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
+ dst, ":", src, ":", ETHERTYPE_IP);
+ device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
+ eh->ether_dhost, ":", eh->ether_shost, ":",
+ ntohs(eh->ether_type));
+ device_printf(sc->rl_dev, "You may have a defective 32-bit "
+ "NIC plugged into a 64-bit PCI slot.\n");
+ device_printf(sc->rl_dev, "Please re-install the NIC in a "
+ "32-bit slot for proper operation.\n");
+ device_printf(sc->rl_dev, "Read the re(4) man page for more "
+ "details.\n");
+ error = EIO;
+ }
+
+done:
+ /* Turn interface off, release resources */
+
+ sc->rl_testmode = 0;
+ sc->rl_flags &= ~RL_FLAG_LINK;
+ ifp->if_flags &= ~IFF_PROMISC;
+ re_stop(sc);
+ if (m0 != NULL)
+ m_freem(m0);
+
+ RL_UNLOCK(sc);
+
+ return (error);
+}
+
+#endif
+
+/*
+ * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
+ * IDs against our list and return a device name if we find a match.
+ */
+static int
+re_probe(device_t dev)
+{
+ struct rl_type *t;
+ uint16_t devid, vendor;
+ uint16_t revid, sdevid;
+ int i;
+
+ vendor = pci_get_vendor(dev);
+ devid = pci_get_device(dev);
+ revid = pci_get_revid(dev);
+ sdevid = pci_get_subdevice(dev);
+
+ if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
+ if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
+ /*
+ * Only attach to rev. 3 of the Linksys EG1032 adapter.
+ * Rev. 2 is supported by sk(4).
+ */
+ return (ENXIO);
+ }
+ }
+
+ if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
+ if (revid != 0x20) {
+ /* 8139, let rl(4) take care of this device. */
+ return (ENXIO);
+ }
+ }
+
+ t = re_devs;
+ for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
+ if (vendor == t->rl_vid && devid == t->rl_did) {
+ device_set_desc(dev, t->rl_name);
+ return (BUS_PROBE_DEFAULT);
+ }
+ }
+
+ return (ENXIO);
+}
+
+/*
+ * Map a single buffer address.
+ */
+
+static void
+re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+ bus_addr_t *addr;
+
+ if (error)
+ return;
+
+ KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
+ addr = arg;
+ *addr = segs->ds_addr;
+}
+
+static int
+re_allocmem(device_t dev, struct rl_softc *sc)
+{
+ bus_size_t rx_list_size, tx_list_size;
+ int error;
+ int i;
+
+ rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
+ tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
+
+ /*
+ * Allocate the parent bus DMA tag appropriate for PCI.
+ * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
+ * register should be set. However some RealTek chips are known
+ * to be buggy on DAC handling, therefore disable DAC by limiting
+ * DMA address space to 32bit. PCIe variants of RealTek chips
+ * may not have the limitation but I took safer path.
+ */
+ error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
+ BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
+ BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
+ NULL, NULL, &sc->rl_parent_tag);
+ if (error) {
+ device_printf(dev, "could not allocate parent DMA tag\n");
+ return (error);
+ }
+
+ /*
+ * Allocate map for TX mbufs.
+ */
+ error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
+ BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
+ NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
+ NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
+ if (error) {
+ device_printf(dev, "could not allocate TX DMA tag\n");
+ return (error);
+ }
+
+ /*
+ * Allocate map for RX mbufs.
+ */
+
+ error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
+ BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+ MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
+ if (error) {
+ device_printf(dev, "could not allocate RX DMA tag\n");
+ return (error);
+ }
+
+ /*
+ * Allocate map for TX descriptor list.
+ */
+ error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
+ 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
+ NULL, tx_list_size, 1, tx_list_size, 0,
+ NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
+ if (error) {
+ device_printf(dev, "could not allocate TX DMA ring tag\n");
+ return (error);
+ }
+
+ /* Allocate DMA'able memory for the TX ring */
+
+ error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
+ (void **)&sc->rl_ldata.rl_tx_list,
+ BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
+ &sc->rl_ldata.rl_tx_list_map);
+ if (error) {
+ device_printf(dev, "could not allocate TX DMA ring\n");
+ return (error);
+ }
+
+ /* Load the map for the TX ring. */
+
+ sc->rl_ldata.rl_tx_list_addr = 0;
+ error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
+ sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
+ tx_list_size, re_dma_map_addr,
[... truncated: 3159 lines follow ...]
Other related posts:
- » [haiku-commits] r37038 - haiku/vendor/freebsd/current/dev/re - korli
