hrev54417 adds 3 changesets to branch 'master'
old head: dabd6c739f7c596e0b1e3d1345f39742aedfee1f
new head: 733e150b7457eab9713bed18f45410cb07be1ab1
overview:
https://git.haiku-os.org/haiku/log/?qt=range&q=733e150b7457+%5Edabd6c739f7c
----------------------------------------------------------------------------
0615a177b794: pci: Rework 64 bit base address register handling.
This moves the entire 64 bit handling into _GetBarInfo() and applies it
to the PCI address and size too. Previously only the RAM address was
handled for the 64 bit case.
Also fixes the 64 bit check to be done after the type determination.
Previously it would theoretically be possible for an IO BAR with the
lowest address bit set for that type (bit 3) to be mistaken to be 64 bit
and then skipping/mishandling the next BAR. Due to alignment this would
have needed to be a 4 byte IO BAR though.
This also corrects the limit for 64 bit BARs of type 1 devices. As there
are only two slots, only slot 0 can be 64 bit.
Also removes a copy&paste error that would lead to the high address of
64 bit BARs of type 1 devices to get taken from the h0 instead of h1
struct, corrupting its value.
Make the mandatory arguments to _GetBarInfo() references to make the
distinction more obvious and replace 0 with NULL in the default values.
Change-Id: Iae59f2875c93f15411a4d9791e71e69ba7a42287
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3022
Reviewed-by: waddlesplash <waddlesplash@xxxxxxxxx>
74c9e88b759b: pci: Cleanup, no functional change intended.
Make mandatory argument of _GetRomBarInfo a reference too and use NULL
instead of 0 for pointer argument default value.
Some line length cleanup.
Change-Id: I1bdb59eeae4496b75fd4a1b8c5b305283da266f9
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3023
Reviewed-by: waddlesplash <waddlesplash@xxxxxxxxx>
733e150b7457: drivers: Fix 64 bit BAR checks and remove redundant masking.
Fix address type mask to use the right bits via PCI_address_type. The
previous 0xc value applies to the upper of the two address type and
the prefetchable bit instead of the two adddress type bits. This would
cause prefetchable 64 bit BARs to be misidentified as not being 64 bit.
Remove address masking as this is already done on the field in pci_info.
Use uint64 instead of phys_addr_t explicitly as on pure 32 bit platforms
this would otherwise result in a shift greater than type size.
Note that the sizes should theoretically be adjusted as well, but in all
of these cases a size needing the upper 32 bits doesn't make much sense.
Change-Id: Idd0d6e9a6cc18656b43cafcac720b132fc1f2ad3
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3024
Reviewed-by: waddlesplash <waddlesplash@xxxxxxxxx>
[ Michael Lotz <mmlr@xxxxxxxx> ]
----------------------------------------------------------------------------
6 files changed, 105 insertions(+), 80 deletions(-)
src/add-ons/kernel/bus_managers/pci/pci.cpp | 143 +++++++++++--------
src/add-ons/kernel/bus_managers/pci/pci.h | 13 +-
src/add-ons/kernel/busses/i2c/pch_i2c_pci.cpp | 8 +-
src/add-ons/kernel/busses/usb/xhci.cpp | 7 +-
.../kernel/drivers/audio/hda/hda_controller.cpp | 7 +-
.../drivers/power/pch_thermal/pch_thermal.cpp | 7 +-
############################################################################
Commit: 0615a177b794413c757b2b26dab3c53f5b0fc688
URL: https://git.haiku-os.org/haiku/commit/?id=0615a177b794
Author: Michael Lotz <mmlr@xxxxxxxx>
Date: Thu Jul 9 20:19:26 2020 UTC
Committer: waddlesplash <waddlesplash@xxxxxxxxx>
Commit-Date: Sat Jul 11 23:25:44 2020 UTC
pci: Rework 64 bit base address register handling.
This moves the entire 64 bit handling into _GetBarInfo() and applies it
to the PCI address and size too. Previously only the RAM address was
handled for the 64 bit case.
Also fixes the 64 bit check to be done after the type determination.
Previously it would theoretically be possible for an IO BAR with the
lowest address bit set for that type (bit 3) to be mistaken to be 64 bit
and then skipping/mishandling the next BAR. Due to alignment this would
have needed to be a 4 byte IO BAR though.
This also corrects the limit for 64 bit BARs of type 1 devices. As there
are only two slots, only slot 0 can be 64 bit.
Also removes a copy&paste error that would lead to the high address of
64 bit BARs of type 1 devices to get taken from the h0 instead of h1
struct, corrupting its value.
Make the mandatory arguments to _GetBarInfo() references to make the
distinction more obvious and replace 0 with NULL in the default values.
Change-Id: Iae59f2875c93f15411a4d9791e71e69ba7a42287
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3022
Reviewed-by: waddlesplash <waddlesplash@xxxxxxxxx>
----------------------------------------------------------------------------
diff --git a/src/add-ons/kernel/bus_managers/pci/pci.cpp
b/src/add-ons/kernel/bus_managers/pci/pci.cpp
index 61b0d0a6b7..11a9935284 100644
--- a/src/add-ons/kernel/bus_managers/pci/pci.cpp
+++ b/src/add-ons/kernel/bus_managers/pci/pci.cpp
@@ -1174,47 +1174,78 @@ PCI::_CreateDevice(PCIBus *parent, uint8 device, uint8
function)
}
-uint32
-PCI::_BarSize(uint32 bits, uint32 mask)
+uint64
+PCI::_BarSize(uint64 bits)
{
- bits &= mask;
if (!bits)
return 0;
- uint32 size = 1;
- while (!(bits & size))
+
+ uint64 size = 1;
+ while ((bits & size) == 0)
size <<= 1;
+
return size;
}
size_t
-PCI::_GetBarInfo(PCIDev *dev, uint8 offset, uint32 *_address, uint32 *_size,
- uint8 *_flags, uint32 *_highAddress)
+PCI::_GetBarInfo(PCIDev *dev, uint8 offset, uint32 &_ramAddress,
+ uint32 &_pciAddress, uint32 &_size, uint8 &flags, uint32
*_highRAMAddress,
+ uint32 *_highPCIAddress, uint32 *_highSize)
{
- uint32 oldValue = ReadConfig(dev->domain, dev->bus, dev->device,
dev->function,
- offset, 4);
+ uint64 pciAddress = ReadConfig(dev->domain, dev->bus, dev->device,
+ dev->function, offset, 4);
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset,
4,
0xffffffff);
- uint32 newValue = ReadConfig(dev->domain, dev->bus, dev->device,
dev->function,
+ uint64 size = ReadConfig(dev->domain, dev->bus, dev->device,
dev->function,
offset, 4);
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset,
4,
- oldValue);
+ pciAddress);
uint32 mask = PCI_address_memory_32_mask;
- bool is64bit = (oldValue & PCI_address_type_64) != 0;
- if ((oldValue & PCI_address_space) == PCI_address_space)
+ bool is64bit = false;
+ if ((pciAddress & PCI_address_space) != 0)
mask = PCI_address_io_mask;
- else if (is64bit && _highAddress != NULL) {
- *_highAddress = ReadConfig(dev->domain, dev->bus, dev->device,
- dev->function, offset + 4, 4);
+ else {
+ is64bit = (pciAddress & PCI_address_type) ==
PCI_address_type_64;
+
+ if (is64bit && _highRAMAddress != NULL) {
+ uint64 highPCIAddress = ReadConfig(dev->domain,
dev->bus,
+ dev->device, dev->function, offset + 4, 4);
+ WriteConfig(dev->domain, dev->bus, dev->device,
dev->function,
+ offset + 4, 4, 0xffffffff);
+ uint64 highSize = ReadConfig(dev->domain, dev->bus,
dev->device,
+ dev->function, offset + 4, 4);
+ WriteConfig(dev->domain, dev->bus, dev->device,
dev->function,
+ offset + 4, 4, highPCIAddress);
+
+ pciAddress |= highPCIAddress << 32;
+ size |= highSize << 32;
+ }
}
- *_address = oldValue & mask;
- if (_size != NULL)
- *_size = _BarSize(newValue, mask);
- if (_flags != NULL)
- *_flags = oldValue & ~mask;
- return is64bit ? 2 : 1;
+ flags = (uint32)pciAddress & ~mask;
+ pciAddress &= ((uint64)0xffffffff << 32) | mask;
+ size &= ((uint64)0xffffffff << 32) | mask;
+
+ size = _BarSize(size);
+ uint64 ramAddress = pci_ram_address(pciAddress);
+
+ _ramAddress = ramAddress;
+ _pciAddress = pciAddress;
+ _size = size;
+ if (!is64bit)
+ return 1;
+
+ if (_highRAMAddress == NULL || _highPCIAddress == NULL || _highSize ==
NULL)
+ panic("64 bit PCI BAR but no space to store high values\n");
+ else {
+ *_highRAMAddress = ramAddress >> 32;
+ *_highPCIAddress = pciAddress >> 32;
+ *_highSize = size >> 32;
+ }
+
+ return 2;
}
@@ -1233,7 +1264,7 @@ PCI::_GetRomBarInfo(PCIDev *dev, uint8 offset, uint32
*_address, uint32 *_size,
*_address = oldValue & PCI_rom_address_mask;
if (_size != NULL)
- *_size = _BarSize(newValue, PCI_rom_address_mask);
+ *_size = _BarSize(newValue & PCI_rom_address_mask);
if (_flags != NULL)
*_flags = newValue & 0xf;
}
@@ -1296,23 +1327,14 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
_GetRomBarInfo(dev, PCI_rom_base,
&dev->info.u.h0.rom_base_pci,
&dev->info.u.h0.rom_size);
for (int i = 0; i < 6;) {
- size_t barSize = _GetBarInfo(dev,
PCI_base_registers + 4 * i,
- &dev->info.u.h0.base_registers_pci[i],
- &dev->info.u.h0.base_register_sizes[i],
- &dev->info.u.h0.base_register_flags[i],
- i < 5 ?
&dev->info.u.h0.base_registers_pci[i + 1] : NULL);
-
- phys_addr_t addr =
dev->info.u.h0.base_registers_pci[i];
- if (barSize == 2) {
- addr +=
((phys_addr_t)dev->info.u.h0.base_registers_pci[i + 1])
- << 32;
- }
- addr = pci_ram_address(addr);
- dev->info.u.h0.base_registers[i] = (uint32)addr;
- if (barSize == 2)
- dev->info.u.h0.base_registers[i + 1] =
(uint32)(addr >> 32);
-
- i += barSize;
+ i += _GetBarInfo(dev, PCI_base_registers + 4 *
i,
+ dev->info.u.h0.base_registers[i],
+ dev->info.u.h0.base_registers_pci[i],
+ dev->info.u.h0.base_register_sizes[i],
+ dev->info.u.h0.base_register_flags[i],
+ i < 5 ?
&dev->info.u.h0.base_registers[i + 1] : NULL,
+ i < 5 ?
&dev->info.u.h0.base_registers_pci[i + 1] : NULL,
+ i < 5 ?
&dev->info.u.h0.base_register_sizes[i + 1] : NULL);
}
// restore PCI device address decoding
@@ -1351,22 +1373,14 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
_GetRomBarInfo(dev, PCI_bridge_rom_base,
&dev->info.u.h1.rom_base_pci);
for (int i = 0; i < 2;) {
- size_t barSize = _GetBarInfo(dev,
PCI_base_registers + 4 * i,
- &dev->info.u.h1.base_registers_pci[i],
- &dev->info.u.h1.base_register_sizes[i],
- &dev->info.u.h1.base_register_flags[i],
- i < 2 ?
&dev->info.u.h1.base_registers_pci[i + 1] : NULL);
-
- phys_addr_t addr =
dev->info.u.h1.base_registers_pci[i];
- if (barSize == 2) {
- addr +=
((phys_addr_t)dev->info.u.h0.base_registers_pci[i + 1])
- << 32;
- }
- addr = pci_ram_address(addr);
- dev->info.u.h1.base_registers[i] = (uint32)addr;
- if (barSize == 2)
- dev->info.u.h1.base_registers[i + 1] =
(uint32)(addr >> 32);
- i += barSize;
+ i += _GetBarInfo(dev, PCI_base_registers + 4 *
i,
+ dev->info.u.h1.base_registers[i],
+ dev->info.u.h1.base_registers_pci[i],
+ dev->info.u.h1.base_register_sizes[i],
+ dev->info.u.h1.base_register_flags[i],
+ i < 1 ?
&dev->info.u.h1.base_registers[i + 1] : NULL,
+ i < 1 ?
&dev->info.u.h1.base_registers_pci[i + 1] : NULL,
+ i < 1 ?
&dev->info.u.h1.base_register_sizes[i + 1] : NULL);
}
// restore PCI device address decoding
diff --git a/src/add-ons/kernel/bus_managers/pci/pci.h
b/src/add-ons/kernel/bus_managers/pci/pci.h
index 6b4d1a84d6..435a2a6ba1 100644
--- a/src/add-ons/kernel/bus_managers/pci/pci.h
+++ b/src/add-ons/kernel/bus_managers/pci/pci.h
@@ -146,10 +146,13 @@ private:
void _ConfigureBridges(PCIBus *bus);
void _RefreshDeviceInfo(PCIBus *bus);
- uint32 _BarSize(uint32 bits, uint32
mask);
+ uint64 _BarSize(uint64 bits);
size_t _GetBarInfo(PCIDev *dev, uint8
offset,
- uint32
*address, uint32 *size = 0,
- uint8 *flags =
0, uint32 *highAddress = 0);
+ uint32
&ramAddress, uint32 &pciAddress,
+ uint32 &size,
uint8 &flags,
+ uint32
*highRAMAddress = NULL,
+ uint32
*highPCIAddress = NULL,
+ uint32
*highSize = NULL);
void _GetRomBarInfo(PCIDev *dev,
uint8 offset,
uint32
*address, uint32 *size = 0,
uint8 *flags =
0);
############################################################################
Commit: 74c9e88b759b9fa8c5bd42789037b361892f7c7a
URL: https://git.haiku-os.org/haiku/commit/?id=74c9e88b759b
Author: Michael Lotz <mmlr@xxxxxxxx>
Date: Thu Jul 9 21:13:47 2020 UTC
Committer: waddlesplash <waddlesplash@xxxxxxxxx>
Commit-Date: Sat Jul 11 23:25:44 2020 UTC
pci: Cleanup, no functional change intended.
Make mandatory argument of _GetRomBarInfo a reference too and use NULL
instead of 0 for pointer argument default value.
Some line length cleanup.
Change-Id: I1bdb59eeae4496b75fd4a1b8c5b305283da266f9
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3023
Reviewed-by: waddlesplash <waddlesplash@xxxxxxxxx>
----------------------------------------------------------------------------
diff --git a/src/add-ons/kernel/bus_managers/pci/pci.cpp
b/src/add-ons/kernel/bus_managers/pci/pci.cpp
index 11a9935284..bbc11a3885 100644
--- a/src/add-ons/kernel/bus_managers/pci/pci.cpp
+++ b/src/add-ons/kernel/bus_managers/pci/pci.cpp
@@ -1250,7 +1250,7 @@ PCI::_GetBarInfo(PCIDev *dev, uint8 offset, uint32
&_ramAddress,
void
-PCI::_GetRomBarInfo(PCIDev *dev, uint8 offset, uint32 *_address, uint32 *_size,
+PCI::_GetRomBarInfo(PCIDev *dev, uint8 offset, uint32 &_address, uint32 *_size,
uint8 *_flags)
{
uint32 oldValue = ReadConfig(dev->domain, dev->bus, dev->device,
dev->function,
@@ -1262,7 +1262,7 @@ PCI::_GetRomBarInfo(PCIDev *dev, uint8 offset, uint32
*_address, uint32 *_size,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset,
4,
oldValue);
- *_address = oldValue & PCI_rom_address_mask;
+ _address = oldValue & PCI_rom_address_mask;
if (_size != NULL)
*_size = _BarSize(newValue & PCI_rom_address_mask);
if (_flags != NULL)
@@ -1324,7 +1324,7 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
pcicmd & ~(PCI_command_io |
PCI_command_memory));
// get BAR size infos
- _GetRomBarInfo(dev, PCI_rom_base,
&dev->info.u.h0.rom_base_pci,
+ _GetRomBarInfo(dev, PCI_rom_base,
dev->info.u.h0.rom_base_pci,
&dev->info.u.h0.rom_size);
for (int i = 0; i < 6;) {
i += _GetBarInfo(dev, PCI_base_registers + 4 *
i,
@@ -1349,7 +1349,8 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
dev->info.u.h0.subsystem_id = ReadConfig(dev->domain,
dev->bus,
dev->device, dev->function, PCI_subsystem_id,
2);
dev->info.u.h0.subsystem_vendor_id =
ReadConfig(dev->domain,
- dev->bus, dev->device, dev->function,
PCI_subsystem_vendor_id, 2);
+ dev->bus, dev->device, dev->function,
PCI_subsystem_vendor_id,
+ 2);
dev->info.u.h0.interrupt_line = ReadConfig(dev->domain,
dev->bus,
dev->device, dev->function, PCI_interrupt_line,
1);
dev->info.u.h0.interrupt_pin = ReadConfig(dev->domain,
dev->bus,
@@ -1363,7 +1364,8 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
case PCI_header_type_PCI_to_PCI_bridge:
{
- // disable PCI device address decoding (io and memory)
while BARs are modified
+ // disable PCI device address decoding (io and memory)
while BARs
+ // are modified
uint16 pcicmd = ReadConfig(dev->domain, dev->bus,
dev->device,
dev->function, PCI_command, 2);
WriteConfig(dev->domain, dev->bus, dev->device,
dev->function,
@@ -1371,7 +1373,7 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
pcicmd & ~(PCI_command_io |
PCI_command_memory));
_GetRomBarInfo(dev, PCI_bridge_rom_base,
- &dev->info.u.h1.rom_base_pci);
+ dev->info.u.h1.rom_base_pci);
for (int i = 0; i < 2;) {
i += _GetBarInfo(dev, PCI_base_registers + 4 *
i,
dev->info.u.h1.base_registers[i],
@@ -1409,7 +1411,8 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
dev->info.u.h1.memory_limit = ReadConfig(dev->domain,
dev->bus,
dev->device, dev->function, PCI_memory_limit,
2);
dev->info.u.h1.prefetchable_memory_base =
ReadConfig(dev->domain,
- dev->bus, dev->device, dev->function,
PCI_prefetchable_memory_base, 2);
+ dev->bus, dev->device, dev->function,
+ PCI_prefetchable_memory_base, 2);
dev->info.u.h1.prefetchable_memory_limit = ReadConfig(
dev->domain, dev->bus, dev->device,
dev->function,
PCI_prefetchable_memory_limit, 2);
diff --git a/src/add-ons/kernel/bus_managers/pci/pci.h
b/src/add-ons/kernel/bus_managers/pci/pci.h
index 435a2a6ba1..f3a7f9370c 100644
--- a/src/add-ons/kernel/bus_managers/pci/pci.h
+++ b/src/add-ons/kernel/bus_managers/pci/pci.h
@@ -154,8 +154,8 @@ private:
uint32
*highPCIAddress = NULL,
uint32
*highSize = NULL);
void _GetRomBarInfo(PCIDev *dev,
uint8 offset,
- uint32
*address, uint32 *size = 0,
- uint8 *flags =
0);
+ uint32
&address, uint32 *size = NULL,
+ uint8 *flags =
NULL);
domain_data * _GetDomainData(uint8 domain);
############################################################################
Revision: hrev54417
Commit: 733e150b7457eab9713bed18f45410cb07be1ab1
URL: https://git.haiku-os.org/haiku/commit/?id=733e150b7457
Author: Michael Lotz <mmlr@xxxxxxxx>
Date: Sat Jul 11 19:56:30 2020 UTC
Committer: waddlesplash <waddlesplash@xxxxxxxxx>
Commit-Date: Sat Jul 11 23:25:44 2020 UTC
drivers: Fix 64 bit BAR checks and remove redundant masking.
Fix address type mask to use the right bits via PCI_address_type. The
previous 0xc value applies to the upper of the two address type and
the prefetchable bit instead of the two adddress type bits. This would
cause prefetchable 64 bit BARs to be misidentified as not being 64 bit.
Remove address masking as this is already done on the field in pci_info.
Use uint64 instead of phys_addr_t explicitly as on pure 32 bit platforms
this would otherwise result in a shift greater than type size.
Note that the sizes should theoretically be adjusted as well, but in all
of these cases a size needing the upper 32 bits doesn't make much sense.
Change-Id: Idd0d6e9a6cc18656b43cafcac720b132fc1f2ad3
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3024
Reviewed-by: waddlesplash <waddlesplash@xxxxxxxxx>
----------------------------------------------------------------------------
diff --git a/src/add-ons/kernel/busses/i2c/pch_i2c_pci.cpp
b/src/add-ons/kernel/busses/i2c/pch_i2c_pci.cpp
index 088d26e1c3..afb01af582 100644
--- a/src/add-ons/kernel/busses/i2c/pch_i2c_pci.cpp
+++ b/src/add-ons/kernel/busses/i2c/pch_i2c_pci.cpp
@@ -131,9 +131,11 @@ init_device(device_node* node, void** device_cookie)
pci->get_pci_info(device, pciInfo);
bus->info.base_addr = pciInfo->u.h0.base_registers[0];
- bus->info.base_addr &= PCI_address_memory_32_mask;
- if ((pciInfo->u.h0.base_register_flags[0] & 0xc) == PCI_address_type_64)
- bus->info.base_addr +=
(phys_addr_t)pciInfo->u.h0.base_registers[1] << 32;
+ if ((pciInfo->u.h0.base_register_flags[0] & PCI_address_type)
+ == PCI_address_type_64) {
+ bus->info.base_addr |= (uint64)pciInfo->u.h0.base_registers[1]
<< 32;
+ }
+
bus->info.map_size = pciInfo->u.h0.base_register_sizes[0];
// enable power
diff --git a/src/add-ons/kernel/busses/usb/xhci.cpp
b/src/add-ons/kernel/busses/usb/xhci.cpp
index ca444f08f1..600e9ecd19 100644
--- a/src/add-ons/kernel/busses/usb/xhci.cpp
+++ b/src/add-ons/kernel/busses/usb/xhci.cpp
@@ -237,9 +237,10 @@ XHCI::XHCI(pci_info *info, Stack *stack)
// map the registers (low + high for 64-bit when requested)
phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0];
- physicalAddress &= PCI_address_memory_32_mask;
- if ((fPCIInfo->u.h0.base_register_flags[0] & 0xC) ==
PCI_address_type_64)
- physicalAddress +=
(phys_addr_t)fPCIInfo->u.h0.base_registers[1] << 32;
+ if ((fPCIInfo->u.h0.base_register_flags[0] & PCI_address_type)
+ == PCI_address_type_64) {
+ physicalAddress |= (uint64)fPCIInfo->u.h0.base_registers[1] <<
32;
+ }
size_t mapSize = fPCIInfo->u.h0.base_register_sizes[0];
diff --git a/src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp
b/src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp
index 6a3c10b35c..949a57c386 100644
--- a/src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp
+++ b/src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp
@@ -1008,9 +1008,10 @@ hda_hw_init(hda_controller* controller)
// map the registers (low + high for 64-bit when requested)
phys_addr_t physicalAddress = pciInfo.u.h0.base_registers[0];
- physicalAddress &= PCI_address_memory_32_mask;
- if ((pciInfo.u.h0.base_register_flags[0] & 0xC) == PCI_address_type_64)
- physicalAddress += (phys_addr_t)pciInfo.u.h0.base_registers[1]
<< 32;
+ if ((pciInfo.u.h0.base_register_flags[0] & PCI_address_type)
+ == PCI_address_type_64) {
+ physicalAddress |= (uint64)pciInfo.u.h0.base_registers[1] << 32;
+ }
// Map MMIO registers
controller->regs_area = map_physical_memory("hda_hw_regs",
diff --git a/src/add-ons/kernel/drivers/power/pch_thermal/pch_thermal.cpp
b/src/add-ons/kernel/drivers/power/pch_thermal/pch_thermal.cpp
index 3d990f1ef0..126e405d4b 100644
--- a/src/add-ons/kernel/drivers/power/pch_thermal/pch_thermal.cpp
+++ b/src/add-ons/kernel/drivers/power/pch_thermal/pch_thermal.cpp
@@ -290,9 +290,10 @@ pch_thermal_init_device(void *_cookie, void **cookie)
// map the registers (low + high for 64-bit when requested)
phys_addr_t physicalAddress = info.u.h0.base_registers[0];
- physicalAddress &= PCI_address_memory_32_mask;
- if ((info.u.h0.base_register_flags[0] & 0xc) == PCI_address_type_64)
- physicalAddress += (phys_addr_t)info.u.h0.base_registers[1] <<
32;
+ if ((info.u.h0.base_register_flags[0] & PCI_address_type)
+ == PCI_address_type_64) {
+ physicalAddress |= (uint64)info.u.h0.base_registers[1] << 32;
+ }
size_t mapSize = info.u.h0.base_register_sizes[0];
