hrev53970 adds 2 changesets to branch 'master'
old head: 2e99f0e1fe64acd26a66cae16a326a2477aa09f3
new head: 6a30d84f3c234b2d9f631b2a392045fa74b09124
overview:
https://git.haiku-os.org/haiku/log/?qt=range&q=6a30d84f3c23+%5E2e99f0e1fe64
----------------------------------------------------------------------------
22ec64553f27: intel_extreme: some minor fixes
- Cleanup HEAD_MODE constants. These should be completely removed, now
that we have a proper notion of pipes and displays. But the DPMS code
still uses them, for now.
- Fix the ie_pipe command where width and height were swapped and
missing a +1 to show the actual videomode values
6a30d84f3c23: add some docs for agp_gart and intel_extreme drivers
Not a lot of info there yet, but it's a start.
[ Adrien Destugues <pulkomandy@xxxxxxxxxxxxx> ]
----------------------------------------------------------------------------
9 files changed, 187 insertions(+), 54 deletions(-)
docs/develop/busses/agp_gart/ReadMe.md | 22 +++++
.../drivers/intel_extreme/generations.txt | 98 ++++++++++++++++++++
.../graphics/intel_extreme/intel_extreme.h | 17 ++--
src/add-ons/accelerants/intel_extreme/Pipes.cpp | 20 +++-
src/add-ons/accelerants/intel_extreme/Ports.cpp | 13 +--
.../accelerants/intel_extreme/accelerant.cpp | 6 --
.../accelerants/intel_extreme/accelerant.h | 3 -
src/add-ons/accelerants/intel_extreme/mode.cpp | 6 +-
.../drivers/graphics/intel_extreme/device.cpp | 56 +++++------
############################################################################
Commit: 22ec64553f27ac1fff59b5ff32ecb266dba7c06e
URL: https://git.haiku-os.org/haiku/commit/?id=22ec64553f27
Author: Adrien Destugues <pulkomandy@xxxxxxxxxxxxx>
Date: Fri Mar 13 08:47:36 2020 UTC
intel_extreme: some minor fixes
- Cleanup HEAD_MODE constants. These should be completely removed, now
that we have a proper notion of pipes and displays. But the DPMS code
still uses them, for now.
- Fix the ie_pipe command where width and height were swapped and
missing a +1 to show the actual videomode values
----------------------------------------------------------------------------
diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h
b/headers/private/graphics/intel_extreme/intel_extreme.h
index f29566145b..a77398f3fc 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -521,8 +521,10 @@ struct intel_free_graphics_memory {
#define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21)
#define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000
#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000
+#define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff
#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000
#define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16
+#define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0
#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15
#define DISPLAY_PLL_DIVISOR_1 (1UL << 8)
#define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000
@@ -647,8 +649,7 @@ struct intel_free_graphics_memory {
// planes
#define INTEL_PIPE_ENABLED (1UL << 31)
-#define INTEL_PIPE_CONTROL 0x0008
-#define INTEL_PIPE_STATUS 0x0024
+#define INTEL_PIPE_STATE (1UL << 30)
#define INTEL_PLANE_OFFSET 0x1000
@@ -719,12 +720,6 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_A_PALETTE (0xa000 |
REGS_NORTH_SHARED)
#define INTEL_DISPLAY_B_PALETTE (0xa800 |
REGS_NORTH_SHARED)
-// PLL registers
-#define INTEL_DISPLAY_A_PLL (0x6014 |
REGS_SOUTH_SHARED)
-#define INTEL_DISPLAY_B_PLL (0x6018 |
REGS_SOUTH_SHARED)
-#define CHV_DISPLAY_C_PLL (0x6030 |
REGS_SOUTH_SHARED)
-#define SNB_DPLL_SEL (0x7000 |
REGS_SOUTH_SHARED)
-
// Ironlake PCH reference clk control
#define PCH_DREF_CONTROL (0x6200 |
REGS_SOUTH_SHARED)
#define DREF_CONTROL_MASK 0x7fc3
@@ -749,9 +744,13 @@ struct intel_free_graphics_memory {
#define DREF_SSC4_DISABLE (0 << 0)
#define DREF_SSC4_ENABLE (1 << 0)
+// PLL registers
// Multiplier Divisor
+#define INTEL_DISPLAY_A_PLL (0x6014 |
REGS_SOUTH_SHARED)
+#define INTEL_DISPLAY_B_PLL (0x6018 |
REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED)
+#define CHV_DISPLAY_C_PLL (0x6030 |
REGS_SOUTH_SHARED)
#define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED)
@@ -759,6 +758,8 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED)
+#define SNB_DPLL_SEL (0x7000 |
REGS_SOUTH_SHARED)
+
// i2c
#define INTEL_I2C_IO_A (0x5010 |
REGS_SOUTH_SHARED)
#define INTEL_I2C_IO_B (0x5014 |
REGS_SOUTH_SHARED)
diff --git a/src/add-ons/accelerants/intel_extreme/Pipes.cpp
b/src/add-ons/accelerants/intel_extreme/Pipes.cpp
index 8b34bbe6e5..1fa06121de 100644
--- a/src/add-ons/accelerants/intel_extreme/Pipes.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Pipes.cpp
@@ -138,6 +138,12 @@ Pipe::Configure(display_mode* mode)
write32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset, pipeControl);
read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);
#endif
+
+ // According to SandyBridge modesetting sequence, pipe must be enabled
+ // before PLL are configured.
+ addr_t pipeReg = INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset;
+ write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED);
+
}
@@ -320,6 +326,13 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32
pixelClock,
// & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
}
+ // Also configure the FP0 divisor on SandyBridge
+ if (gInfo->shared_info->device_type.Generation() == 6) {
+ pll |= ((1 << (divisors.p1 - 1))
+ <<
DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT)
+ & DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK;
+ }
+
if (divisors.p2 == 5 || divisors.p2 == 7)
pll |= DISPLAY_PLL_DIVIDE_HIGH;
@@ -339,12 +352,17 @@ Pipe::ConfigureClocks(const pll_divisors& divisors,
uint32 pixelClock,
pll |= DISPLAY_PLL_POST1_DIVIDE_2;
}
- // Allow the PLL to warm up by masking its bit.
write32(pllControl, pll & ~DISPLAY_PLL_NO_VGA_CONTROL);
+ // FIXME what is this doing? Why put the PLL back under
VGA_CONTROL
+ // here?
read32(pllControl);
spin(150);
+
+ // Configure and enable the PLL
write32(pllControl, pll);
read32(pllControl);
+
+ // Allow the PLL to warm up.
spin(150);
if (gInfo->shared_info->device_type.Generation() >= 6) {
diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp
b/src/add-ons/accelerants/intel_extreme/Ports.cpp
index ba8c99ac74..acdca8213e 100644
--- a/src/add-ons/accelerants/intel_extreme/Ports.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp
@@ -381,9 +381,10 @@ LVDSPort::PipePreference()
// Ideally we could just return INTEL_PIPE_ANY for the newer devices,
but
// this doesn't quite work yet.
- // For Ibex Point and Sandy Bridge, read the existing LVDS configuration
- // and just reuse that (it seems our attempt to change it doesn't work,
- // anyway)
+ // For Ibex Point and SandyBridge, read the existing LVDS configuration
and
+ // just reuse that (it seems our attempt to change it doesn't work,
anyway)
+ // On SandyBridge, there is a transcoder C that can't be used by the
LVDS
+ // port (but A and B would be fine).
if (gInfo->shared_info->device_type.Generation() <= 6) {
uint32 portState = read32(_PortRegister());
if (portState & DISPLAY_MONITOR_PIPE_B)
@@ -392,9 +393,9 @@ LVDSPort::PipePreference()
return INTEL_PIPE_A;
}
- // For later PCH versions, assume pipe B for now. Note that later
devices
- // add a pipe C (but do they add a transcoder C?), so we'd need to
handle
- // that and the port register has a different format because of it.
+ // For later generations, assume pipe B for now. Note that later devices
+ // add a pipe C (and a transcoder C), so we'd need to handle that and
the
+ // port register has a different format because of it.
// (using PORT_TRANS_*_SEL_CPT to select which transcoder to use)
return INTEL_PIPE_B;
}
diff --git a/src/add-ons/accelerants/intel_extreme/accelerant.cpp
b/src/add-ons/accelerants/intel_extreme/accelerant.cpp
index ad9414f436..2ce15758aa 100644
--- a/src/add-ons/accelerants/intel_extreme/accelerant.cpp
+++ b/src/add-ons/accelerants/intel_extreme/accelerant.cpp
@@ -366,9 +366,6 @@ probe_ports()
foundLVDS = true;
gInfo->ports[gInfo->port_count++] = lvdsPort;
gInfo->head_mode |= HEAD_MODE_LVDS_PANEL;
- gInfo->head_mode |= HEAD_MODE_A_ANALOG;
- // FIXME this should not be set, but without it, LVDS
modesetting
- // doesn't work on SandyBridge. Find out why it makes a
difference.
gInfo->head_mode |= HEAD_MODE_B_DIGITAL;
} else
delete lvdsPort;
@@ -497,9 +494,6 @@ intel_init_accelerant(int device)
setup_ring_buffer(info.primary_ring_buffer, "intel primary ring
buffer");
- TRACE("pipe control for: 0x%" B_PRIx32 " 0x%" B_PRIx32 "\n",
- read32(INTEL_PIPE_CONTROL), read32(INTEL_PIPE_CONTROL));
-
// Probe all ports
status = probe_ports();
diff --git a/src/add-ons/accelerants/intel_extreme/accelerant.h
b/src/add-ons/accelerants/intel_extreme/accelerant.h
index 0b34dda2f1..0014fd79df 100644
--- a/src/add-ons/accelerants/intel_extreme/accelerant.h
+++ b/src/add-ons/accelerants/intel_extreme/accelerant.h
@@ -75,10 +75,7 @@ struct accelerant_info {
#define HEAD_MODE_A_ANALOG 0x0001
#define HEAD_MODE_B_DIGITAL 0x0002
-#define HEAD_MODE_CLONE 0x0003
#define HEAD_MODE_LVDS_PANEL 0x0008
-#define HEAD_MODE_TESTING 0x1000
-#define HEAD_MODE_STIPPI 0x2000
extern accelerant_info* gInfo;
diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp
b/src/add-ons/accelerants/intel_extreme/mode.cpp
index 06e73a1b98..529dbf7961 100644
--- a/src/add-ons/accelerants/intel_extreme/mode.cpp
+++ b/src/add-ons/accelerants/intel_extreme/mode.cpp
@@ -210,9 +210,11 @@ void
wait_for_vblank(void)
{
acquire_sem_etc(gInfo->shared_info->vblank_sem, 1, B_RELATIVE_TIMEOUT,
- 25000);
+ 21000);
// With the output turned off via DPMS, we might not get any
interrupts
- // anymore that's why we don't wait forever for it.
+ // anymore that's why we don't wait forever for it. At 50Hz,
we're sure
+ // to get a vblank in at most 20ms, so there is no need to wait
longer
+ // than that.
}
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp
b/src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp
index aaa891c48e..8ab3614c37 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp
@@ -120,51 +120,51 @@ dump_pipe_info(int argc, char** argv)
kprintf("intel_extreme pipe configuration:\n");
value = read32(info, INTEL_DISPLAY_A_HTOTAL + pipeOffset);
- kprintf(" HTOTAL start %" B_PRIu32 " end %" B_PRIu32 "\n", value >> 16,
- value & 0xFFFF);
+ kprintf(" HTOTAL start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_DISPLAY_A_HBLANK + pipeOffset);
- kprintf(" HBLANK start %" B_PRIu32 " end %" B_PRIu32 "\n", value >> 16,
- value & 0xFFFF);
+ kprintf(" HBLANK start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_DISPLAY_A_HSYNC + pipeOffset);
- kprintf(" HSYNC start %" B_PRIu32 " end %" B_PRIu32 "\n", value >> 16,
- value & 0xFFFF);
+ kprintf(" HSYNC start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_DISPLAY_A_VTOTAL + pipeOffset);
- kprintf(" VTOTAL start %" B_PRIu32 " end %" B_PRIu32 "\n", value >> 16,
- value & 0xFFFF);
+ kprintf(" VTOTAL start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_DISPLAY_A_VBLANK + pipeOffset);
- kprintf(" VBLANK start %" B_PRIu32 " end %" B_PRIu32 "\n", value >> 16,
- value & 0xFFFF);
+ kprintf(" VBLANK start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_DISPLAY_A_VSYNC + pipeOffset);
- kprintf(" VSYNC start %" B_PRIu32 " end %" B_PRIu32 "\n", value >> 16,
- value & 0xFFFF);
+ kprintf(" VSYNC start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_DISPLAY_A_PIPE_SIZE + pipeOffset);
- kprintf(" SIZE %" B_PRIu32 "x%" B_PRIu32 "\n", value >> 16,
- value & 0xFFFF);
+ kprintf(" SIZE %" B_PRIu32 "x%" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
if (info.pch_info != INTEL_PCH_NONE) {
kprintf("intel_extreme transcoder configuration:\n");
value = read32(info, INTEL_TRANSCODER_A_HTOTAL + pipeOffset);
- kprintf(" HTOTAL start %" B_PRIu32 " end %" B_PRIu32 "\n",
value >> 16,
- value & 0xFFFF);
+ kprintf(" HTOTAL start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_TRANSCODER_A_HBLANK + pipeOffset);
- kprintf(" HBLANK start %" B_PRIu32 " end %" B_PRIu32 "\n",
value >> 16,
- value & 0xFFFF);
+ kprintf(" HBLANK start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_TRANSCODER_A_HSYNC + pipeOffset);
- kprintf(" HSYNC start %" B_PRIu32 " end %" B_PRIu32 "\n",
value >> 16,
- value & 0xFFFF);
+ kprintf(" HSYNC start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_TRANSCODER_A_VTOTAL + pipeOffset);
- kprintf(" VTOTAL start %" B_PRIu32 " end %" B_PRIu32 "\n",
value >> 16,
- value & 0xFFFF);
+ kprintf(" VTOTAL start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_TRANSCODER_A_VBLANK + pipeOffset);
- kprintf(" VBLANK start %" B_PRIu32 " end %" B_PRIu32 "\n",
value >> 16,
- value & 0xFFFF);
+ kprintf(" VBLANK start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_TRANSCODER_A_VSYNC + pipeOffset);
- kprintf(" VSYNC start %" B_PRIu32 " end %" B_PRIu32 "\n",
value >> 16,
- value & 0xFFFF);
+ kprintf(" VSYNC start %" B_PRIu32 " end %" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
value = read32(info, INTEL_TRANSCODER_A_IMAGE_SIZE +
pipeOffset);
- kprintf(" SIZE %" B_PRIu32 "x%" B_PRIu32 "\n", value >> 16,
- value & 0xFFFF);
+ kprintf(" SIZE %" B_PRIu32 "x%" B_PRIu32 "\n",
+ (value & 0xFFFF) + 1, (value >> 16) + 1);
}
kprintf("intel_extreme display plane configuration:\n");
############################################################################
Revision: hrev53970
Commit: 6a30d84f3c234b2d9f631b2a392045fa74b09124
URL: https://git.haiku-os.org/haiku/commit/?id=6a30d84f3c23
Author: Adrien Destugues <pulkomandy@xxxxxxxxxxxxx>
Date: Fri Mar 13 08:51:28 2020 UTC
add some docs for agp_gart and intel_extreme drivers
Not a lot of info there yet, but it's a start.
----------------------------------------------------------------------------
diff --git a/docs/develop/busses/agp_gart/ReadMe.md
b/docs/develop/busses/agp_gart/ReadMe.md
new file mode 100644
index 0000000000..f89255d789
--- /dev/null
+++ b/docs/develop/busses/agp_gart/ReadMe.md
@@ -0,0 +1,22 @@
+AGP (and PCI-express) Graphics Address Re-Mapping Table
+=======================================================
+
+The GART is an IO-MMU allowing the videocard and CPU to share some memory.
+Either the CPU can access the video RAM directly ("aperture"), or the video
+card can access the system RAM using DMA access.
+
+The GART converts between physical addresses and virtual addresses on the
+video card side. Of course, the CPU must then map these physical addresses
+in its own address space to use them (using the MMU).
+
+The GART works as you'd expect from an MMU. It has a page table (called GTT)
+in RAM and walks it to figure out mappings. Since there cannot be page misses
+(that would require exception handling on the GPU side), access to missing
+pages are instead sent to a dedicated "scratch" page which is not used for
+anything else.
+
+Our driver implements the GART and GTT for Intel graphics card only, so far.
+Since our videodrivers are only doing modesetting, they do not need much
+support and other drivers implemented GTT management directly on their own
+(it is usually enough to make the framebuffer accessible to the CPU). However,
+this could be generalized into a more flexible iommu bus protocol.
diff --git a/docs/develop/drivers/intel_extreme/generations.txt
b/docs/develop/drivers/intel_extreme/generations.txt
new file mode 100644
index 0000000000..31db9f2457
--- /dev/null
+++ b/docs/develop/drivers/intel_extreme/generations.txt
@@ -0,0 +1,98 @@
+Intel video hardware generations
+================================
+
+This file summarizes the different generations of Intel hardware, because the
+naming is a bit inconsistent and it's hard to follow which is which sometimes.
+The devices can be referred to by year of introduction, generation number,
+chipset commercial number, or internal codenames.
+
+Generation 1
+============
+
+These are the i740 and i810 devices handled by intel_810. No further info will
+be provided here.
+
+Generation 2 / 2002
+============
+
+i830, 845, 85x, 865
+
+Generation 3 / 2004
+============
+
+This is the first generation to be documented at intellinuxgraphics.org.
+Generation 2 devices are quite similar for the modesetting part, but not
+identical.
+
+GMA 900 (i915G)
+GMA 950 (i945G)
+GMA 3000 (946GZ, Q965, Q963)
+GMA 3100 (G31, G33, Q33 et Q35)
+GMA 3150 (Pineview for Atom CPUs)
+
+Generation 4 / 2006
+============
+
+GMA X3000 (i965G)
+GMA X3100 (i965GM)
+GMA X3500 (G35)
+GMA 4500 (Q43, Q45)
+GMA 4500M / 4500HD (GL40, GS45, GM45, GM47)
+GMA X4500 / X4500HD (G41, G43 (X4500), G45 (X4500HD))
+
+Generation 5 / 2010
+============
+
+Westmere / Clarkdale, Arrandale / Iron Lake / Ibex Peak
+
+Switches from the traditional northbridge / southbridge to the new
+"platform control hub" design. Essentially, most of the northbridge functions
+are now directly in the CPU package.
+
+Generation 6 / 2011
+============
+
+Sandybridge / Cougar Point
+
+The northbridge and CPU are now even on the same die.
+
+Generation 7 / 2012
+============
+
+Ivy Bridge / Panther Point and Haswell / Lynx Point
+
+A lot of the video output hardware is moved from the northbridge (CPU) to the
+PCH. This makes sense because it allows to match the PCH chipset (soldered on
+to the motherboard) with the video ports (also soldered there). Otherwise, the
+CPU generation would define which ports are usable or not.
+
+This impacts several things in the modesetting sequence, as well as the address
+of the registers which are moved.
+
+This is also the first generation to support 3 independant displays, which
+also impacts the register layout in many places.
+
+Generation 8 / 2013
+============
+
+Broadwell / Wildcat Point and Braswell
+
+Generation 9 / 2015
+============
+
+Skylake / Sunrise Point, Apollo Lake, Kaby Lake / Union Point
+
+Generation 10
+=============
+
+Cannon Point / Coffee Lake
+
+Generation 11
+=============
+
+Ice Lake
+
+Generation 12
+=============
+
+Tiger Lake
