hrev52711 adds 1 changeset to branch 'master'
old head: 3987287dc64fb40d6472a1d0dd4fcb140286e60d
new head: 6086986d30f646d1fae16b63666adc6b8e4f50b3
overview:
https://git.haiku-os.org/haiku/log/?qt=range&q=6086986d30f6+%5E3987287dc64f
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6086986d30f6: kernel/x86: additional msr and cpuid items
Adds SSBD and L1TF related items
Change-Id: Iccea2bb9e057e0d011a18609212f175f9b5e678d
Reviewed-on: https://review.haiku-os.org/825
Reviewed-by: Adrien Destugues <pulkomandy@xxxxxxxxxxxxx>
[ Rob Gill <rrobgill@xxxxxxxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev52711
Commit: 6086986d30f646d1fae16b63666adc6b8e4f50b3
URL: https://git.haiku-os.org/haiku/commit/?id=6086986d30f6
Author: Rob Gill <rrobgill@xxxxxxxxxxxxxx>
Date: Fri Jan 4 22:30:20 2019 UTC
Committer: waddlesplash <waddlesplash@xxxxxxxxx>
Commit-Date: Fri Jan 4 19:06:05 2019 UTC
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2 files changed, 18 insertions(+), 3 deletions(-)
headers/private/kernel/arch/x86/arch_cpu.h | 15 ++++++++++++---
src/system/kernel/arch/x86/arch_cpu.cpp | 6 ++++++
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diff --git a/headers/private/kernel/arch/x86/arch_cpu.h
b/headers/private/kernel/arch/x86/arch_cpu.h
index 685cf4a748..dc4b3d1e23 100644
--- a/headers/private/kernel/arch/x86/arch_cpu.h
+++ b/headers/private/kernel/arch/x86/arch_cpu.h
@@ -42,6 +42,7 @@
#define IA32_MSR_APERF 0xe8
#define IA32_MSR_MTRR_CAPABILITIES 0xfe
#define IA32_MSR_ARCH_CAPABILITIES 0x10a
+#define IA32_MSR_FLUSH_CMD 0x10b
#define IA32_MSR_SYSENTER_CS 0x174
#define IA32_MSR_SYSENTER_ESP 0x175
#define IA32_MSR_SYSENTER_EIP 0x176
@@ -56,6 +57,7 @@
// MSR SPEC CTRL bits
#define IA32_MSR_SPEC_CTRL_IBRS (1 << 0)
#define IA32_MSR_SPEC_CTRL_STIBP (1 << 1)
+#define IA32_MSR_SPEC_CTRL_SSBD (1 << 2)
// MSR PRED CMD bits
#define IA32_MSR_PRED_CMD_IBPB (1 << 0)
@@ -72,8 +74,14 @@
#define IA32_MSR_EFER_NX (1 << 11)
// MSR ARCH CAPABILITIES bits
-#define IA32_MSR_ARCH_CAP_RDCL_NO (1 << 0)
-#define IA32_MSR_ARCH_CAP_IBRS_ALL (1 << 1)
+#define IA32_MSR_ARCH_CAP_RDCL_NO (1 << 0)
+#define IA32_MSR_ARCH_CAP_IBRS_ALL (1 << 1)
+#define IA32_MSR_ARCH_CAP_RSBA (1 << 2)
+#define IA32_MSR_ARCH_CAP_SKIP_L1D_VMENTRY (1 << 3)
+#define IA32_MSR_ARCH_CAP_SSB_NO (1 << 4)
+
+// MSR FLUSH CMD bits
+#define IA32_MSR_L1D_FLUSH (1 << 1)
// X2APIC MSRs.
#define IA32_MSR_APIC_ID 0x00000802
@@ -276,8 +284,9 @@
#define IA32_FEATURE_AVX512_4FMAPS (1 << 3) // AVX-512 4-register Multiply
Accumulation Single precision
#define IA32_FEATURE_IBRS (1 << 26) // IBRS / IBPB
Speculation Control
#define IA32_FEATURE_STIBP (1 << 27) // STIBP
Speculation Control
+#define IA32_FEATURE_L1D_FLUSH (1 << 28) // L1D_FLUSH supported
#define IA32_FEATURE_ARCH_CAPABILITIES (1 << 29) //
IA32_ARCH_CAPABILITIES MSR
-
+#define IA32_FEATURE_SSBD (1 << 30) // Speculative
Store Bypass Disable
// x86 defined features from cpuid eax 0x80000007, edx register
#define IA32_FEATURE_INVARIANT_TSC (1 << 8)
diff --git a/src/system/kernel/arch/x86/arch_cpu.cpp
b/src/system/kernel/arch/x86/arch_cpu.cpp
index 85d2108f64..26bf254eb5 100644
--- a/src/system/kernel/arch/x86/arch_cpu.cpp
+++ b/src/system/kernel/arch/x86/arch_cpu.cpp
@@ -546,6 +546,12 @@ dump_feature_string(int currentCPU, cpu_ent* cpu)
strlcat(features, "ibrs ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_STIBP)
strlcat(features, "stibp ", sizeof(features));
+ if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_L1D_FLUSH)
+ strlcat(features, "l1d_flush ", sizeof(features));
+ if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_ARCH_CAPABILITIES)
+ strlcat(features, "msr_arch ", sizeof(features));
+ if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_SSBD)
+ strlcat(features, "ssbd ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_EXT_IBPB)
strlcat(features, "ibpb ", sizeof(features));
dprintf("CPU %d: features: %s\n", currentCPU, features);
