hrev52093 adds 2 changesets to branch 'master'
old head: 3248de3de47011137e0c667a7247dd424c827bd7
new head: a052f4807f90e41eb8029a270541420d57f95ef9
overview:
https://git.haiku-os.org/haiku/log/?qt=range&q=a052f4807f90+%5E3248de3de470
----------------------------------------------------------------------------
09ddf9b9f3f5: freebsd11_network: Properly implement CALLOUT_RETURNUNLOCKED.
Fixes a double-lock situation in the Atheros driver. We really should
implement FreeBSD's MTX_SPIN instead of relying on cpu_status here...
a052f4807f90: atheroswifi: Sync with FreeBSD 11.1.
Thanks to khaled and return0e for testing!
[ Augustin Cavalier <waddlesplash@xxxxxxxxx> ]
----------------------------------------------------------------------------
231 files changed, 31354 insertions(+), 6412 deletions(-)
src/add-ons/kernel/drivers/network/wlan/Jamfile | 4 +-
.../drivers/network/wlan/atheroswifi/Jamfile | 34 +-
.../network/wlan/atheroswifi/dev/ath/ah_osdep.c | 134 +-
.../network/wlan/atheroswifi/dev/ath/ah_osdep.h | 89 +-
.../atheroswifi/dev/ath/ath_dfs/null/dfs_null.c | 93 +-
.../wlan/atheroswifi/dev/ath/ath_hal/ah.c | 301 +-
.../wlan/atheroswifi/dev/ath/ath_hal/ah.h | 579 +-
.../wlan/atheroswifi/dev/ath/ath_hal/ah_btcoex.h | 523 ++
.../wlan/atheroswifi/dev/ath/ath_hal/ah_debug.h | 11 +-
.../wlan/atheroswifi/dev/ath/ath_hal/ah_decode.h | 6 +-
.../wlan/atheroswifi/dev/ath/ath_hal/ah_desc.h | 98 +-
.../wlan/atheroswifi/dev/ath/ath_hal/ah_devid.h | 19 +-
.../atheroswifi/dev/ath/ath_hal/ah_diagcodes.h | 6 +-
.../wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom.h | 30 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_9287.c | 14 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_9287.h | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_v1.c | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_v1.h | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_v14.c | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_v14.h | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_v3.c | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_v3.h | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.c | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.h | 2 +-
.../atheroswifi/dev/ath/ath_hal/ah_internal.h | 265 +-
.../atheroswifi/dev/ath/ath_hal/ah_regdomain.c | 493 +-
.../atheroswifi/dev/ath/ath_hal/ah_regdomain.h | 7 +-
.../dev/ath/ath_hal/ah_regdomain/ah_rd_ctry.h | 2 +-
.../dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h | 27 +-
.../ath/ath_hal/ah_regdomain/ah_rd_freqbands.h | 2 +-
.../dev/ath/ath_hal/ah_regdomain/ah_rd_regenum.h | 3 +-
.../dev/ath/ath_hal/ah_regdomain/ah_rd_regmap.h | 3 +-
.../wlan/atheroswifi/dev/ath/ath_hal/ah_soc.h | 2 +-
.../atheroswifi/dev/ath/ath_hal/ar5210/ar5210.h | 28 +-
.../dev/ath/ath_hal/ar5210/ar5210_attach.c | 37 +-
.../dev/ath/ath_hal/ar5210/ar5210_beacon.c | 2 +-
.../dev/ath/ath_hal/ar5210/ar5210_interrupts.c | 2 +-
.../dev/ath/ath_hal/ar5210/ar5210_keycache.c | 2 +-
.../dev/ath/ath_hal/ar5210/ar5210_misc.c | 63 +-
.../dev/ath/ath_hal/ar5210/ar5210_phy.c | 2 +-
.../dev/ath/ath_hal/ar5210/ar5210_power.c | 14 +-
.../dev/ath/ath_hal/ar5210/ar5210_recv.c | 14 +-
.../dev/ath/ath_hal/ar5210/ar5210_reset.c | 23 +-
.../dev/ath/ath_hal/ar5210/ar5210_xmit.c | 44 +-
.../dev/ath/ath_hal/ar5210/ar5210desc.h | 6 +-
.../dev/ath/ath_hal/ar5210/ar5210phy.h | 2 +-
.../dev/ath/ath_hal/ar5210/ar5210reg.h | 3 +-
.../dev/ath/ath_hal/ar5210/ar5k_0007.ini | 2 +-
.../atheroswifi/dev/ath/ath_hal/ar5211/ar5211.h | 24 +-
.../dev/ath/ath_hal/ar5211/ar5211_attach.c | 35 +-
.../dev/ath/ath_hal/ar5211/ar5211_beacon.c | 2 +-
.../dev/ath/ath_hal/ar5211/ar5211_interrupts.c | 2 +-
.../dev/ath/ath_hal/ar5211/ar5211_keycache.c | 2 +-
.../dev/ath/ath_hal/ar5211/ar5211_misc.c | 39 +-
.../dev/ath/ath_hal/ar5211/ar5211_phy.c | 2 +-
.../dev/ath/ath_hal/ar5211/ar5211_power.c | 14 +-
.../dev/ath/ath_hal/ar5211/ar5211_recv.c | 10 +-
.../dev/ath/ath_hal/ar5211/ar5211_reset.c | 13 +-
.../dev/ath/ath_hal/ar5211/ar5211_xmit.c | 32 +-
.../dev/ath/ath_hal/ar5211/ar5211desc.h | 4 +-
.../dev/ath/ath_hal/ar5211/ar5211phy.h | 2 +-
.../dev/ath/ath_hal/ar5211/ar5211reg.h | 2 +-
.../atheroswifi/dev/ath/ath_hal/ar5211/boss.ini | 2 +-
.../atheroswifi/dev/ath/ath_hal/ar5212/ar2316.c | 6 +-
.../atheroswifi/dev/ath/ath_hal/ar5212/ar2317.c | 6 +-
.../atheroswifi/dev/ath/ath_hal/ar5212/ar2413.c | 6 +-
.../atheroswifi/dev/ath/ath_hal/ar5212/ar2425.c | 6 +-
.../atheroswifi/dev/ath/ath_hal/ar5212/ar5111.c | 2 +-
.../atheroswifi/dev/ath/ath_hal/ar5212/ar5112.c | 4 +-
.../atheroswifi/dev/ath/ath_hal/ar5212/ar5212.h | 44 +-
.../dev/ath/ath_hal/ar5212/ar5212.ini | 2 +-
.../dev/ath/ath_hal/ar5212/ar5212_ani.c | 67 +-
.../dev/ath/ath_hal/ar5212/ar5212_attach.c | 65 +-
.../dev/ath/ath_hal/ar5212/ar5212_beacon.c | 21 +-
.../dev/ath/ath_hal/ar5212/ar5212_eeprom.c | 2 +-
.../dev/ath/ath_hal/ar5212/ar5212_gpio.c | 2 +-
.../dev/ath/ath_hal/ar5212/ar5212_interrupts.c | 2 +-
.../dev/ath/ath_hal/ar5212/ar5212_keycache.c | 2 +-
.../dev/ath/ath_hal/ar5212/ar5212_misc.c | 255 +-
.../dev/ath/ath_hal/ar5212/ar5212_phy.c | 2 +-
.../dev/ath/ath_hal/ar5212/ar5212_power.c | 14 +-
.../dev/ath/ath_hal/ar5212/ar5212_recv.c | 29 +-
.../dev/ath/ath_hal/ar5212/ar5212_reset.c | 179 +-
.../dev/ath/ath_hal/ar5212/ar5212_rfgain.c | 2 +-
.../dev/ath/ath_hal/ar5212/ar5212_xmit.c | 81 +-
.../dev/ath/ath_hal/ar5212/ar5212desc.h | 3 +-
.../dev/ath/ath_hal/ar5212/ar5212phy.h | 15 +-
.../dev/ath/ath_hal/ar5212/ar5212reg.h | 4 +-
.../dev/ath/ath_hal/ar5212/ar5311reg.h | 2 +-
.../atheroswifi/dev/ath/ath_hal/ar5212/ar5413.c | 6 +-
.../atheroswifi/dev/ath/ath_hal/ar5312/ar5312.h | 8 +-
.../dev/ath/ath_hal/ar5312/ar5312_attach.c | 8 +-
.../dev/ath/ath_hal/ar5312/ar5312_eeprom.c | 2 +-
.../dev/ath/ath_hal/ar5312/ar5312_gpio.c | 2 +-
.../dev/ath/ath_hal/ar5312/ar5312_interrupts.c | 2 +-
.../dev/ath/ath_hal/ar5312/ar5312_misc.c | 2 +-
.../dev/ath/ath_hal/ar5312/ar5312_power.c | 7 +-
.../dev/ath/ath_hal/ar5312/ar5312_reset.c | 9 +-
.../dev/ath/ath_hal/ar5312/ar5312phy.h | 2 +-
[ *** stats truncated: 132 lines dropped *** ]
############################################################################
Commit: 09ddf9b9f3f5e310afa87522054f7fe1d2885ef4
URL: https://git.haiku-os.org/haiku/commit/?id=09ddf9b9f3f5
Author: Augustin Cavalier <waddlesplash@xxxxxxxxx>
Date: Wed Jul 11 23:03:27 2018 UTC
freebsd11_network: Properly implement CALLOUT_RETURNUNLOCKED.
Fixes a double-lock situation in the Atheros driver. We really should
implement FreeBSD's MTX_SPIN instead of relying on cpu_status here...
----------------------------------------------------------------------------
diff --git a/src/libs/compat/freebsd11_network/callout.cpp
b/src/libs/compat/freebsd11_network/callout.cpp
index 00f68d3180..7f2315ca3e 100644
--- a/src/libs/compat/freebsd11_network/callout.cpp
+++ b/src/libs/compat/freebsd11_network/callout.cpp
@@ -1,6 +1,7 @@
/*
* Copyright 2010, Axel Dörfler, axeld@xxxxxxxxxxxxxxxx.
- * Distributed under the terms of the MIT License.
+ * Copyright 2018, Haiku, Inc. All rights reserved.
+ * Distributed under the terms of the MIT license.
*/
@@ -66,7 +67,8 @@ callout_thread(void* /*data*/)
c->c_func(c->c_arg);
- if (mutex != NULL)
+ if (mutex != NULL
+ && (c->c_flags &
CALLOUT_RETURNUNLOCKED) == 0)
mtx_unlock(mutex);
mutex_lock(&sLock);
diff --git a/src/libs/compat/freebsd11_network/taskqueue.c
b/src/libs/compat/freebsd11_network/taskqueue.c
index 67a45d3281..cb8fac155b 100644
--- a/src/libs/compat/freebsd11_network/taskqueue.c
+++ b/src/libs/compat/freebsd11_network/taskqueue.c
@@ -293,11 +293,10 @@ taskqueue_drain_timeout(struct taskqueue *queue,
}
-int
-taskqueue_enqueue(struct taskqueue *taskQueue, struct task *task)
+static void
+taskqueue_enqueue_locked(struct taskqueue *taskQueue, struct task *task,
+ cpu_status status)
{
- cpu_status status;
- tq_lock(taskQueue, &status);
/* we don't really support priorities */
if (task->ta_pending) {
task->ta_pending++;
@@ -310,6 +309,18 @@ taskqueue_enqueue(struct taskqueue *taskQueue, struct task
*task)
taskQueue->tq_flags |= TQ_FLAGS_PENDING;
}
tq_unlock(taskQueue, status);
+}
+
+
+int
+taskqueue_enqueue(struct taskqueue *taskQueue, struct task *task)
+{
+ cpu_status status;
+
+ tq_lock(taskQueue, &status);
+ taskqueue_enqueue_locked(taskQueue, task, status);
+ /* The lock is released inside. */
+
return 0;
}
@@ -319,13 +330,16 @@ taskqueue_timeout_func(void *arg)
{
struct taskqueue *queue;
struct timeout_task *timeout_task;
+ cpu_status status;
+ // dummy, as we should never get here on a spin taskqueue
timeout_task = arg;
queue = timeout_task->q;
KASSERT((timeout_task->f & DT_CALLOUT_ARMED) != 0, ("Stray timeout"));
timeout_task->f &= ~DT_CALLOUT_ARMED;
queue->tq_callouts--;
- taskqueue_enqueue(timeout_task->q, &timeout_task->t);
+ taskqueue_enqueue_locked(timeout_task->q, &timeout_task->t, status);
+ /* The lock is released inside. */
}
############################################################################
Revision: hrev52093
Commit: a052f4807f90e41eb8029a270541420d57f95ef9
URL: https://git.haiku-os.org/haiku/commit/?id=a052f4807f90
Author: Augustin Cavalier <waddlesplash@xxxxxxxxx>
Date: Wed Jul 11 23:05:25 2018 UTC
atheroswifi: Sync with FreeBSD 11.1.
Thanks to khaled and return0e for testing!
----------------------------------------------------------------------------
diff --git a/src/add-ons/kernel/drivers/network/wlan/Jamfile
b/src/add-ons/kernel/drivers/network/wlan/Jamfile
index e19ceeed18..f3b1c150f7 100644
--- a/src/add-ons/kernel/drivers/network/wlan/Jamfile
+++ b/src/add-ons/kernel/drivers/network/wlan/Jamfile
@@ -8,7 +8,6 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network wlan
iprowifi2100 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan marvell88w8335 ;
# FreeBSD 9.3 drivers
-SubInclude HAIKU_TOP src add-ons kernel drivers network wlan atheroswifi ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan broadcom43xx ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan marvell88w8363 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan ralinkwifi ;
@@ -16,9 +15,10 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network wlan
wavelanwifi ;
# FreeBSD 11.1 drivers
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan aironetwifi ;
-SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi2200 ;
+SubInclude HAIKU_TOP src add-ons kernel drivers network wlan atheroswifi ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi3945 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi4965 ;
# FreeBSD 11.2 drivers
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan idualwifi7260 ;
+SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi2200 ;
diff --git a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/Jamfile
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/Jamfile
index e1fb7d85ba..84f948ee44 100644
--- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/Jamfile
+++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/Jamfile
@@ -1,14 +1,14 @@
SubDir HAIKU_TOP src add-ons kernel drivers network wlan atheroswifi ;
-UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ]
+UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd11_network compat ]
: true ;
-UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_wlan ] : true ;
+UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd11_wlan ] : true ;
UsePrivateHeaders net system ;
UsePrivateKernelHeaders ;
-SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 _XOPEN_SOURCE ]
- -Wno-format
- -Wno-unused
+SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 _XOPEN_SOURCE ]
+ -Wno-format
+ -Wno-unused
-Wno-uninitialized ;
UseHeaders [ FDirName $(SUBDIR) ] : true ;
@@ -20,18 +20,32 @@ Depends atheroswifi : atheroswifi_hal.o ;
Depends atheroswifi : atheroswifi_rate.o ;
KernelAddon atheroswifi :
+ glue.c
+
if_ath.c
+ if_ath_beacon.c
+ if_ath_btcoex.c
+ if_ath_btcoex_mci.c
+ if_ath_descdma.c
+ if_ath_ioctl.c
if_ath_pci.c
+ if_ath_led.c
+ if_ath_lna_div.c
if_ath_keycache.c
if_ath_sysctl.c
+ if_ath_rx.c
+ if_ath_rx_edma.c
+ if_ath_spectral.c
+ if_ath_tdma.c
if_ath_tx.c
+ if_ath_tx_edma.c
if_ath_tx_ht.c
- glue.c
+
atheroswifi_hal.o
atheroswifi_rate.o
:
- libfreebsd_wlan.a
- libfreebsd_network.a
+ libfreebsd11_wlan.a
+ libfreebsd11_network.a
;
SEARCH_SOURCE += [ FDirName $(SUBDIR) dev ath ath_hal ] ;
@@ -119,11 +133,15 @@ KernelMergeObject atheroswifi_hal.o :
ar5416_recv.c
ar5416_reset.c
ar5416_xmit.c
+ ar5416_btcoex.c
+ ar5416_radar.c
+ ar5416_spectral.c
# RF backend for 5416 and 9160
ar2133.c
# AR9001 and AR9002 support
+ ar9285_btcoex.c
ar9130_attach.c
ar9130_eeprom.c
ar9130_phy.c
diff --git
a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c
index c9a7a261af..900e071f8d 100644
--- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c
+++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c
@@ -26,7 +26,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
- * $FreeBSD$
+ * $FreeBSD: releng/11.1/sys/dev/ath/ah_osdep.c 293111 2016-01-03 17:58:11Z
adrian $
*/
#include "opt_ah.h"
@@ -38,12 +38,16 @@
#include <sys/bus.h>
#include <sys/malloc.h>
#include <sys/proc.h>
+#include <sys/pcpu.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
#include <machine/stdarg.h>
#include <net/ethernet.h> /* XXX for ether_sprintf */
#include <dev/ath/ath_hal/ah.h>
+#include <dev/ath/ath_hal/ah_debug.h>
/*
* WiSoC boards overload the bus tag with information about the
@@ -59,6 +63,23 @@
#define BUSTAG(ah) ((ah)->ah_st)
#endif
+/*
+ * This lock is used to seralise register access for chips which have
+ * problems w/ SMP CPUs issuing concurrent PCI transactions.
+ *
+ * XXX This is a global lock for now; it should be pushed to
+ * a per-device lock in some platform-independent fashion.
+ */
+#ifndef __HAIKU__
+struct mtx ah_regser_mtx;
+MTX_SYSINIT(ah_regser, &ah_regser_mtx, "Atheros register access mutex",
+ MTX_SPIN);
+#else
+spinlock ah_regser_mtx = B_SPINLOCK_INITIALIZER;
+#define mtx_lock_spin(a) acquire_spinlock(a)
+#define mtx_unlock_spin(a) release_spinlock(a)
+#endif
+
extern void ath_hal_printf(struct ath_hal *, const char*, ...)
__printflike(2,3);
extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
@@ -81,9 +102,8 @@ static SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0,
#ifdef AH_DEBUG
int ath_hal_debug = 0;
-SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
+SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RWTUN, &ath_hal_debug,
0, "Atheros HAL debugging printfs");
-TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
#endif /* AH_DEBUG */
static MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
@@ -123,13 +143,29 @@ ath_hal_ether_sprintf(const u_int8_t *mac)
#ifdef AH_DEBUG
-/* This must match the definition in ath_hal/ah_debug.h */
-#define HAL_DEBUG_UNMASKABLE 0xf0000000
+/*
+ * XXX This is highly relevant only for the AR5416 and later
+ * PCI/PCIe NICs. It'll need adjustment for other hardware
+ * variations.
+ */
+static int
+ath_hal_reg_whilst_asleep(struct ath_hal *ah, uint32_t reg)
+{
+
+ if (reg >= 0x4000 && reg < 0x5000)
+ return (1);
+ if (reg >= 0x6000 && reg < 0x7000)
+ return (1);
+ if (reg >= 0x7000 && reg < 0x8000)
+ return (1);
+ return (0);
+}
+
void
DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
{
if ((mask == HAL_DEBUG_UNMASKABLE) ||
- (ah->ah_config.ah_debug & mask) ||
+ (ah != NULL && ah->ah_config.ah_debug & mask) ||
(ath_hal_debug & mask)) {
__va_list ap;
va_start(ap, fmt);
@@ -240,22 +276,32 @@ ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg,
u_int32_t val)
bus_space_tag_t tag = BUSTAG(ah);
bus_space_handle_t h = ah->ah_sh;
+#ifdef AH_DEBUG
+ /* Debug - complain if we haven't fully waken things up */
+ if (! ath_hal_reg_whilst_asleep(ah, reg) &&
+ ah->ah_powerMode != HAL_PM_AWAKE) {
+ ath_hal_printf(ah, "%s: reg=0x%08x, val=0x%08x, pm=%d\n",
+ __func__, reg, val, ah->ah_powerMode);
+ }
+#endif
+
if (ath_hal_alq) {
struct ale *ale = ath_hal_alq_get(ah);
if (ale) {
struct athregrec *r = (struct athregrec *) ale->ae_data;
+ r->threadid = curthread->td_tid;
r->op = OP_WRITE;
r->reg = reg;
r->val = val;
alq_post(ath_hal_alq, ale);
}
}
-#if _BYTE_ORDER == _BIG_ENDIAN
- if (OS_REG_UNSWAPPED(reg))
- bus_space_write_4(tag, h, reg, val);
- else
-#endif
- bus_space_write_stream_4(tag, h, reg, val);
+ if (ah->ah_config.ah_serialise_reg_war)
+ mtx_lock_spin(&ah_regser_mtx);
+ bus_space_write_4(tag, h, reg, val);
+ OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);
+ if (ah->ah_config.ah_serialise_reg_war)
+ mtx_unlock_spin(&ah_regser_mtx);
}
u_int32_t
@@ -265,16 +311,26 @@ ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
bus_space_handle_t h = ah->ah_sh;
u_int32_t val;
-#if _BYTE_ORDER == _BIG_ENDIAN
- if (OS_REG_UNSWAPPED(reg))
- val = bus_space_read_4(tag, h, reg);
- else
+#ifdef AH_DEBUG
+ /* Debug - complain if we haven't fully waken things up */
+ if (! ath_hal_reg_whilst_asleep(ah, reg) &&
+ ah->ah_powerMode != HAL_PM_AWAKE) {
+ ath_hal_printf(ah, "%s: reg=0x%08x, pm=%d\n",
+ __func__, reg, ah->ah_powerMode);
+ }
#endif
- val = bus_space_read_stream_4(tag, h, reg);
+
+ if (ah->ah_config.ah_serialise_reg_war)
+ mtx_lock_spin(&ah_regser_mtx);
+ OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);
+ val = bus_space_read_4(tag, h, reg);
+ if (ah->ah_config.ah_serialise_reg_war)
+ mtx_unlock_spin(&ah_regser_mtx);
if (ath_hal_alq) {
struct ale *ale = ath_hal_alq_get(ah);
if (ale) {
struct athregrec *r = (struct athregrec *) ale->ae_data;
+ r->threadid = curthread->td_tid;
r->op = OP_READ;
r->reg = reg;
r->val = val;
@@ -291,6 +347,7 @@ OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
struct ale *ale = ath_hal_alq_get(ah);
if (ale) {
struct athregrec *r = (struct athregrec *) ale->ae_data;
+ r->threadid = curthread->td_tid;
r->op = OP_MARK;
r->reg = id;
r->val = v;
@@ -298,7 +355,8 @@ OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
}
}
}
-#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
+#else /* AH_DEBUG_ALQ */
+
/*
* Memory-mapped device register read/write. These are here
* as routines when debugging support is enabled and/or when
@@ -316,12 +374,21 @@ ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg,
u_int32_t val)
bus_space_tag_t tag = BUSTAG(ah);
bus_space_handle_t h = ah->ah_sh;
-#if _BYTE_ORDER == _BIG_ENDIAN
- if (OS_REG_UNSWAPPED(reg))
- bus_space_write_4(tag, h, reg, val);
- else
+#ifdef AH_DEBUG
+ /* Debug - complain if we haven't fully waken things up */
+ if (! ath_hal_reg_whilst_asleep(ah, reg) &&
+ ah->ah_powerMode != HAL_PM_AWAKE) {
+ ath_hal_printf(ah, "%s: reg=0x%08x, val=0x%08x, pm=%d\n",
+ __func__, reg, val, ah->ah_powerMode);
+ }
#endif
- bus_space_write_stream_4(tag, h, reg, val);
+
+ if (ah->ah_config.ah_serialise_reg_war)
+ mtx_lock_spin(&ah_regser_mtx);
+ bus_space_write_4(tag, h, reg, val);
+ OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);
+ if (ah->ah_config.ah_serialise_reg_war)
+ mtx_unlock_spin(&ah_regser_mtx);
}
u_int32_t
@@ -331,15 +398,24 @@ ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
bus_space_handle_t h = ah->ah_sh;
u_int32_t val;
-#if _BYTE_ORDER == _BIG_ENDIAN
- if (OS_REG_UNSWAPPED(reg))
- val = bus_space_read_4(tag, h, reg);
- else
+#ifdef AH_DEBUG
+ /* Debug - complain if we haven't fully waken things up */
+ if (! ath_hal_reg_whilst_asleep(ah, reg) &&
+ ah->ah_powerMode != HAL_PM_AWAKE) {
+ ath_hal_printf(ah, "%s: reg=0x%08x, pm=%d\n",
+ __func__, reg, ah->ah_powerMode);
+ }
#endif
- val = bus_space_read_stream_4(tag, h, reg);
+
+ if (ah->ah_config.ah_serialise_reg_war)
+ mtx_lock_spin(&ah_regser_mtx);
+ OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);
+ val = bus_space_read_4(tag, h, reg);
+ if (ah->ah_config.ah_serialise_reg_war)
+ mtx_unlock_spin(&ah_regser_mtx);
return val;
}
-#endif /* AH_DEBUG || AH_REGOPS_FUNC */
+#endif /* AH_DEBUG_ALQ */
#ifdef AH_ASSERT
void
diff --git
a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.h
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.h
index 99b94c4f4f..b37b4bb6c5 100644
--- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.h
+++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.h
@@ -26,7 +26,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
- * $FreeBSD$
+ * $FreeBSD: releng/11.1/sys/dev/ath/ah_osdep.h 293111 2016-01-03 17:58:11Z
adrian $
*/
#ifndef _ATH_AH_OSDEP_H_
#define _ATH_AH_OSDEP_H_
@@ -48,6 +48,12 @@ typedef void *HAL_SOFTC;
typedef bus_space_tag_t HAL_BUS_TAG;
typedef bus_space_handle_t HAL_BUS_HANDLE;
+/*
+ * Although the underlying hardware may support 64 bit DMA, the
+ * current Atheros hardware only supports 32 bit addressing.
+ */
+typedef uint32_t HAL_DMA_ADDR;
+
/*
* Linker set writearounds for chip and RF backend registration.
*/
@@ -63,6 +69,7 @@ typedef bus_space_handle_t HAL_BUS_HANDLE;
#define OS_INLINE __inline
#define OS_MEMZERO(_a, _n) bzero((_a), (_n))
#define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n)
+#define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l))
#define abs(_a) __builtin_abs(_a)
@@ -75,6 +82,10 @@ struct ath_hal;
* domain registers are not byte swapped! Thus, on big-endian
* platforms we have to explicitly byte-swap those registers.
* OS_REG_UNSWAPPED identifies the registers that need special handling.
+ *
+ * This is not currently used by the FreeBSD HAL osdep code; the HAL
+ * currently does not configure hardware byteswapping for register space
+ * accesses and instead does it through the FreeBSD bus space code.
*/
#if _BYTE_ORDER == _BIG_ENDIAN
#define OS_REG_UNSWAPPED(_reg) \
@@ -85,51 +96,49 @@ struct ath_hal;
#endif /* _BYTE_ORDER */
/*
- * Register read/write operations are either handled through
- * platform-dependent routines (or when debugging is enabled
- * with AH_DEBUG); or they are inline expanded using the macros
- * defined below.
+ * For USB/SDIO support (where access latencies are quite high);
+ * some write accesses may be buffered and then flushed when
+ * either a read is done, or an explicit flush is done.
+ *
+ * These are simply placeholders for now.
+ */
+#define OS_REG_WRITE_BUFFER_ENABLE(_ah) \
+ do { } while (0)
+#define OS_REG_WRITE_BUFFER_DISABLE(_ah) \
+ do { } while (0)
+#define OS_REG_WRITE_BUFFER_FLUSH(_ah) \
+ do { } while (0)
+
+/*
+ * Read and write barriers. Some platforms require more strongly ordered
+ * operations and unfortunately most of the HAL is written assuming everything
+ * is either an x86 or the bus layer will do the barriers for you.
+ *
+ * Read barriers should occur before each read, and write barriers
+ * occur after each write.
+ *
+ * Later on for SDIO/USB parts we will methodize this and make them no-ops;
+ * register accesses will go via USB commands.
+ */
+#define OS_BUS_BARRIER_READ BUS_SPACE_BARRIER_READ
+#define OS_BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE
+#define OS_BUS_BARRIER_RW \
+ (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
+#define OS_BUS_BARRIER(_ah, _start, _len, _t) \
+ bus_space_barrier((bus_space_tag_t)(_ah)->ah_st, \
+ (bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t))
+#define OS_BUS_BARRIER_REG(_ah, _reg, _t) \
+ OS_BUS_BARRIER((_ah), (_reg), 4, (_t))
+
+/*
+ * Register read/write operations are handled through
+ * platform-dependent routines.
*/
-#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg,
_val)
#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
-#else
-/*
- * The hardware registers are native little-endian byte order.
- * Big-endian hosts are handled by enabling hardware byte-swap
- * of register reads and writes at reset. But the PCI clock
- * domain registers are not byte swapped! Thus, on big-endian
- * platforms we have to explicitly byte-swap those registers.
- * Most of this code is collapsed at compile time because the
- * register values are constants.
- */
-#if _BYTE_ORDER == _BIG_ENDIAN
-#define OS_REG_WRITE(_ah, _reg, _val) do { \
- if (OS_REG_UNSWAPPED(_reg)) \
- bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
- (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
- else \
- bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \
- (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
-} while (0)
-#define OS_REG_READ(_ah, _reg) \
- (OS_REG_UNSWAPPED(_reg) ? \
- bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
- (bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \
- bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \
- (bus_space_handle_t)(_ah)->ah_sh, (_reg)))
-#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
-#define OS_REG_WRITE(_ah, _reg, _val)
\
- bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
- (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
-#define OS_REG_READ(_ah, _reg)
\
- bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
- (bus_space_handle_t)(_ah)->ah_sh, (_reg))
-#endif /* _BYTE_ORDER */
-#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
#ifdef AH_DEBUG_ALQ
extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
diff --git
a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_dfs/null/dfs_null.c
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_dfs/null/dfs_null.c
index 75574b4e4a..f91eadbd15 100644
---
a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_dfs/null/dfs_null.c
+++
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_dfs/null/dfs_null.c
@@ -26,14 +26,15 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
- * $FreeBSD$
+ * $FreeBSD: releng/11.1/sys/dev/ath/ath_dfs/null/dfs_null.c 298939 2016-05-02
19:56:48Z pfg $
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: releng/11.1/sys/dev/ath/ath_dfs/null/dfs_null.c 298939
2016-05-02 19:56:48Z pfg $");
/*
* This implements an empty DFS module.
*/
+#include "opt_ath.h"
#include "opt_inet.h"
#include "opt_wlan.h"
@@ -42,6 +43,7 @@ __FBSDID("$FreeBSD$");
#include <sys/sysctl.h>
#include <sys/kernel.h>
#include <sys/lock.h>
+#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/errno.h>
@@ -52,6 +54,7 @@ __FBSDID("$FreeBSD$");
#include <sys/socket.h>
#include <net/if.h>
+#include <net/if_var.h>
#include <net/if_media.h>
#include <net/if_arp.h>
#include <net/ethernet.h> /* XXX for ether_sprintf */
@@ -80,7 +83,7 @@ __FBSDID("$FreeBSD$");
int
ath_dfs_attach(struct ath_softc *sc)
{
- return 1;
+ return (1);
}
/*
@@ -89,32 +92,96 @@ ath_dfs_attach(struct ath_softc *sc)
int
ath_dfs_detach(struct ath_softc *sc)
{
- return 1;
+ return (1);
}
/*
- * Enable radar check
+ * Enable radar check. Return 1 if the driver should
+ * enable radar PHY errors, or 0 if not.
*/
-void
+int
ath_dfs_radar_enable(struct ath_softc *sc, struct ieee80211_channel *chan)
{
+#if 0
+ HAL_PHYERR_PARAM pe;
+
+ /* Check if the hardware supports radar reporting */
+ /* XXX TODO: migrate HAL_CAP_RADAR/HAL_CAP_AR to somewhere public! */
+ if (ath_hal_getcapability(sc->sc_ah,
+ HAL_CAP_PHYDIAG, 0, NULL) != HAL_OK)
+ return (0);
+
/* Check if the current channel is radar-enabled */
if (! IEEE80211_IS_CHAN_DFS(chan))
- return;
+ return (0);
+
+ /* Fetch the default parameters */
+ memset(&pe, '\0', sizeof(pe));
+ if (! ath_hal_getdfsdefaultthresh(sc->sc_ah, &pe))
+ return (0);
+
+ /* Enable radar PHY error reporting */
+ sc->sc_dodfs = 1;
+
+ /* Tell the hardware to enable radar reporting */
+ pe.pe_enabled = 1;
+
+ /* Flip on extension channel events only if doing HT40 */
+ if (IEEE80211_IS_CHAN_HT40(chan))
+ pe.pe_extchannel = 1;
+ else
+ pe.pe_extchannel = 0;
+
+ ath_hal_enabledfs(sc->sc_ah, &pe);
+
+ /*
+ * Disable strong signal fast diversity - needed for
+ * AR5212 and similar PHYs for reliable short pulse
+ * duration.
+ */
+ (void) ath_hal_setcapability(sc->sc_ah, HAL_CAP_DIVERSITY, 2, 0, NULL);
+
+ return (1);
+#else
+ return (0);
+#endif
+}
+
+/*
+ * Explicity disable radar reporting.
+ *
+ * Return 0 if it was disabled, < 0 on error.
+ */
+int
+ath_dfs_radar_disable(struct ath_softc *sc)
+{
+#if 0
+ HAL_PHYERR_PARAM pe;
+
+ (void) ath_hal_getdfsthresh(sc->sc_ah, &pe);
+ pe.pe_enabled = 0;
+ (void) ath_hal_enabledfs(sc->sc_ah, &pe);
+ return (0);
+#else
+ return (0);
+#endif
}
/*
* Process DFS related PHY errors
+ *
+ * The mbuf is not "ours" and if we want a copy, we have
+ * to take a copy. It'll be freed after this function returns.
*/
void
-ath_dfs_process_phy_err(struct ath_softc *sc, const char *buf,
+ath_dfs_process_phy_err(struct ath_softc *sc, struct mbuf *m,
uint64_t tsf, struct ath_rx_status *rxstat)
{
}
/*
- * Process the radar events and determine whether a DFS event has occured.
+ * Process the radar events and determine whether a DFS event has occurred.
*
* This is designed to run outside of the RX processing path.
* The RX path will call ath_dfs_tasklet_needed() to see whether
@@ -124,7 +191,7 @@ int
ath_dfs_process_radar_event(struct ath_softc *sc,
struct ieee80211_channel *chan)
{
- return 0;
+ return (0);
}
/*
@@ -137,7 +204,7 @@ ath_dfs_process_radar_event(struct ath_softc *sc,
int
ath_dfs_tasklet_needed(struct ath_softc *sc, struct ieee80211_channel *chan)
{
- return 0;
+ return (0);
}
/*
@@ -214,7 +281,7 @@ bad:
free(indata, M_TEMP);
if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
free(outdata, M_TEMP);
- return error;
+ return (error);
}
/*
@@ -224,5 +291,5 @@ int
ath_dfs_get_thresholds(struct ath_softc *sc, HAL_PHYERR_PARAM *param)
{
ath_hal_getdfsthresh(sc->sc_ah, param);
- return 1;
+ return (1);
}
diff --git
a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c
index 4055079dc7..b8d401cede 100644
--- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c
+++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $FreeBSD$
+ * $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah.c 298939 2016-05-02 19:56:48Z
pfg $
*/
#include "opt_ah.h"
@@ -24,6 +24,7 @@
#include "ah_eeprom.h" /* for 5ghz fast clock flag */
#include "ar5416/ar5416reg.h" /* NB: includes ar5212reg.h */
+#include "ar9003/ar9300_devid.h"
/* linker set of registered chips */
OS_SET_DECLARE(ah_chips, struct ath_hal_chip);
@@ -54,7 +55,9 @@ ath_hal_probe(uint16_t vendorid, uint16_t devid)
*/
struct ath_hal*
ath_hal_attach(uint16_t devid, HAL_SOFTC sc,
- HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS
*error)
+ HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
+ HAL_OPS_CONFIG *ah_config,
+ HAL_STATUS *error)
{
struct ath_hal_chip * const *pchip;
@@ -65,7 +68,8 @@ ath_hal_attach(uint16_t devid, HAL_SOFTC sc,
/* XXX don't have vendorid, assume atheros one works */
if (chip->probe(ATHEROS_VENDOR_ID, devid) == AH_NULL)
continue;
- ah = chip->attach(devid, sc, st, sh, eepromdata, error);
+ ah = chip->attach(devid, sc, st, sh, eepromdata, ah_config,
+ error);
if (ah != AH_NULL) {
/* copy back private state to public area */
ah->ah_devid = AH_PRIVATE(ah)->ah_devid;
@@ -87,38 +91,60 @@ ath_hal_mac_name(struct ath_hal *ah)
switch (ah->ah_macVersion) {
case AR_SREV_VERSION_CRETE:
case AR_SREV_VERSION_MAUI_1:
- return "5210";
+ return "AR5210";
case AR_SREV_VERSION_MAUI_2:
case AR_SREV_VERSION_OAHU:
- return "5211";
+ return "AR5211";
case AR_SREV_VERSION_VENICE:
- return "5212";
+ return "AR5212";
case AR_SREV_VERSION_GRIFFIN:
- return "2413";
+ return "AR2413";
case AR_SREV_VERSION_CONDOR:
- return "5424";
+ return "AR5424";
case AR_SREV_VERSION_EAGLE:
- return "5413";
+ return "AR5413";
case AR_SREV_VERSION_COBRA:
- return "2415";
- case AR_SREV_2425:
- return "2425";
- case AR_SREV_2417:
- return "2417";
+ return "AR2415";
+ case AR_SREV_2425: /* Swan */
+ return "AR2425";
+ case AR_SREV_2417: /* Nala */
+ return "AR2417";
case AR_XSREV_VERSION_OWL_PCI:
- return "5416";
+ return "AR5416";
case AR_XSREV_VERSION_OWL_PCIE:
- return "5418";
+ return "AR5418";
case AR_XSREV_VERSION_HOWL:
- return "9130";
+ return "AR9130";
case AR_XSREV_VERSION_SOWL:
- return "9160";
+ return "AR9160";
case AR_XSREV_VERSION_MERLIN:
- return "9280";
+ if (AH_PRIVATE(ah)->ah_ispcie)
+ return "AR9280";
+ return "AR9220";
case AR_XSREV_VERSION_KITE:
- return "9285";
+ return "AR9285";
case AR_XSREV_VERSION_KIWI:
- return "9287";
+ if (AH_PRIVATE(ah)->ah_ispcie)
+ return "AR9287";
+ return "AR9227";
+ case AR_SREV_VERSION_AR9380:
+ if (ah->ah_macRev >= AR_SREV_REVISION_AR9580_10)
+ return "AR9580";
+ return "AR9380";
+ case AR_SREV_VERSION_AR9460:
+ return "AR9460";
+ case AR_SREV_VERSION_AR9330:
+ return "AR9330";
+ case AR_SREV_VERSION_AR9340:
+ return "AR9340";
+ case AR_SREV_VERSION_QCA9550:
+ return "QCA9550";
+ case AR_SREV_VERSION_AR9485:
+ return "AR9485";
+ case AR_SREV_VERSION_QCA9565:
+ return "QCA9565";
+ case AR_SREV_VERSION_QCA9530:
+ return "QCA9530";
}
return "????";
}
@@ -271,36 +297,42 @@ ath_hal_pkt_txtime(struct ath_hal *ah, const
HAL_RATE_TABLE *rates, uint32_t fra
/* 11n frame - extract out the number of spatial streams */
numStreams = HT_RC_2_STREAMS(rc);
- KASSERT(numStreams == 1 || numStreams == 2, ("number of spatial streams
needs to be 1 or 2: MCS rate 0x%x!", rateix));
+ KASSERT(numStreams > 0 && numStreams <= 4,
+ ("number of spatial streams needs to be 1..3: MCS rate 0x%x!",
+ rateix));
return ath_computedur_ht(frameLen, rc, numStreams, isht40,
shortPreamble);
}
+static const uint16_t ht20_bps[32] = {
+ 26, 52, 78, 104, 156, 208, 234, 260,
+ 52, 104, 156, 208, 312, 416, 468, 520,
+ 78, 156, 234, 312, 468, 624, 702, 780,
+ 104, 208, 312, 416, 624, 832, 936, 1040
+};
+static const uint16_t ht40_bps[32] = {
+ 54, 108, 162, 216, 324, 432, 486, 540,
+ 108, 216, 324, 432, 648, 864, 972, 1080,
+ 162, 324, 486, 648, 972, 1296, 1458, 1620,
+ 216, 432, 648, 864, 1296, 1728, 1944, 2160
+};
+
/*
* Calculate the transmit duration of an 11n frame.
- * This only works for MCS0->MCS15.
*/
uint32_t
-ath_computedur_ht(uint32_t frameLen, uint16_t rate, int streams, HAL_BOOL
isht40,
- HAL_BOOL isShortGI)
+ath_computedur_ht(uint32_t frameLen, uint16_t rate, int streams,
+ HAL_BOOL isht40, HAL_BOOL isShortGI)
{
- static const uint16_t ht20_bps[16] = {
- 26, 52, 78, 104, 156, 208, 234, 260,
- 52, 104, 156, 208, 312, 416, 468, 520
- };
- static const uint16_t ht40_bps[16] = {
- 54, 108, 162, 216, 324, 432, 486, 540,
- 108, 216, 324, 432, 648, 864, 972, 1080,
- };
uint32_t bitsPerSymbol, numBits, numSymbols, txTime;
KASSERT(rate & IEEE80211_RATE_MCS, ("not mcs %d", rate));
- KASSERT((rate &~ IEEE80211_RATE_MCS) < 16, ("bad mcs 0x%x", rate));
+ KASSERT((rate &~ IEEE80211_RATE_MCS) < 31, ("bad mcs 0x%x", rate));
if (isht40)
- bitsPerSymbol = ht40_bps[rate & 0xf];
+ bitsPerSymbol = ht40_bps[rate & 0x1f];
else
- bitsPerSymbol = ht20_bps[rate & 0xf];
+ bitsPerSymbol = ht20_bps[rate & 0x1f];
numBits = OFDM_PLCP_BITS + (frameLen << 3);
numSymbols = howmany(numBits, bitsPerSymbol);
if (isShortGI)
@@ -330,7 +362,7 @@ ath_hal_computetxtime(struct ath_hal *ah,
kbps = rates->info[rateix].rateKbps;
/*
- * index can be invalid duting dynamic Turbo transitions.
+ * index can be invalid during dynamic Turbo transitions.
* XXX
*/
if (kbps == 0)
@@ -394,6 +426,50 @@ ath_hal_computetxtime(struct ath_hal *ah,
return txTime;
}
+int
+ath_hal_get_curmode(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ /*
+ * Pick a default mode at bootup. A channel change is inevitable.
+ */
+ if (!chan)
+ return HAL_MODE_11NG_HT20;
+
+ if (IEEE80211_IS_CHAN_TURBO(chan))
+ return HAL_MODE_TURBO;
+
+ /* check for NA_HT before plain A, since IS_CHAN_A includes NA_HT */
+ if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan))
+ return HAL_MODE_11NA_HT20;
+ if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT40U(chan))
+ return HAL_MODE_11NA_HT40PLUS;
+ if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT40D(chan))
+ return HAL_MODE_11NA_HT40MINUS;
+ if (IEEE80211_IS_CHAN_A(chan))
+ return HAL_MODE_11A;
+
+ /* check for NG_HT before plain G, since IS_CHAN_G includes NG_HT */
+ if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan))
+ return HAL_MODE_11NG_HT20;
+ if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT40U(chan))
+ return HAL_MODE_11NG_HT40PLUS;
+ if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT40D(chan))
+ return HAL_MODE_11NG_HT40MINUS;
+
+ /*
+ * XXX For FreeBSD, will this work correctly given the DYN
+ * chan mode (OFDM+CCK dynamic) ? We have pure-G versions DYN-BG..
+ */
+ if (IEEE80211_IS_CHAN_G(chan))
+ return HAL_MODE_11G;
+ if (IEEE80211_IS_CHAN_B(chan))
+ return HAL_MODE_11B;
+
+ HALASSERT(0);
+ return HAL_MODE_11NG_HT20;
+}
+
+
typedef enum {
WIRELESS_MODE_11a = 0,
WIRELESS_MODE_TURBO = 1,
@@ -444,6 +520,13 @@ ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
clks <<= 1;
} else
clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
+
+ /* Compensate for half/quarter rate */
+ if (c != AH_NULL && IEEE80211_IS_CHAN_HALF(c))
+ clks = clks / 2;
+ else if (c != AH_NULL && IEEE80211_IS_CHAN_QUARTER(c))
+ clks = clks / 4;
+
return clks;
}
@@ -615,6 +698,10 @@ ath_hal_getcapability(struct ath_hal *ah,
HAL_CAPABILITY_TYPE type,
return pCap->hal4AddrAggrSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_EXT_CHAN_DFS:
return pCap->halExtChanDfsSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_RX_STBC:
+ return pCap->halRxStbcSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_TX_STBC:
+ return pCap->halTxStbcSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_COMBINED_RADAR_RSSI:
return pCap->halUseCombinedRadarRssi ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_AUTO_SLEEP:
@@ -626,13 +713,47 @@ ath_hal_getcapability(struct ath_hal *ah,
HAL_CAPABILITY_TYPE type,
case HAL_CAP_REG_FLAG:
*result = AH_PRIVATE(ah)->ah_currentRDext;
return HAL_OK;
+ case HAL_CAP_ENHANCED_DMA_SUPPORT:
+ return pCap->halEnhancedDmaSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_NUM_TXMAPS:
+ *result = pCap->halNumTxMaps;
+ return HAL_OK;
+ case HAL_CAP_TXDESCLEN:
+ *result = pCap->halTxDescLen;
+ return HAL_OK;
+ case HAL_CAP_TXSTATUSLEN:
+ *result = pCap->halTxStatusLen;
+ return HAL_OK;
+ case HAL_CAP_RXSTATUSLEN:
+ *result = pCap->halRxStatusLen;
+ return HAL_OK;
+ case HAL_CAP_RXFIFODEPTH:
+ switch (capability) {
+ case HAL_RX_QUEUE_HP:
+ *result = pCap->halRxHpFifoDepth;
+ return HAL_OK;
+ case HAL_RX_QUEUE_LP:
+ *result = pCap->halRxLpFifoDepth;
+ return HAL_OK;
+ default:
+ return HAL_ENOTSUPP;
+ }
+ case HAL_CAP_RXBUFSIZE:
+ case HAL_CAP_NUM_MR_RETRIES:
+ *result = pCap->halNumMRRetries;
+ return HAL_OK;
case HAL_CAP_BT_COEX:
return pCap->halBtCoexSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_SPECTRAL_SCAN:
+ return pCap->halSpectralScanSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_HT20_SGI:
return pCap->halHTSGI20Support ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_RXTSTAMP_PREC: /* rx desc tstamp precision (bits) */
*result = pCap->halTstampPrecision;
return HAL_OK;
+ case HAL_CAP_ANT_DIV_COMB: /* AR9285/AR9485 LNA diversity */
+ return pCap->halAntDivCombSupport ? HAL_OK : HAL_ENOTSUPP;
+
case HAL_CAP_ENHANCED_DFS_SUPPORT:
return pCap->halEnhancedDfsSupport ? HAL_OK : HAL_ENOTSUPP;
@@ -659,6 +780,17 @@ ath_hal_getcapability(struct ath_hal *ah,
HAL_CAPABILITY_TYPE type,
return pCap->halHasRxSelfLinkedTail ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_LONG_RXDESC_TSF: /* 32 bit TSF in RX descriptor?
*/
return pCap->halHasLongRxDescTsf ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_BB_READ_WAR: /* Baseband read WAR */
+ return pCap->halHasBBReadWar? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_SERIALISE_WAR: /* PCI register serialisation */
+ return pCap->halSerialiseRegWar ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_MFP: /* Management frame protection
setting */
+ *result = pCap->halMfpSupport;
+ return HAL_OK;
+ case HAL_CAP_RX_LNA_MIXING: /* Hardware uses an RX LNA mixer to map
2 antennas to a 1 stream receiver */
+ return pCap->halRxUsingLnaMixing ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_DO_MYBEACON: /* Hardware supports filtering
my-beacons */
+ return pCap->halRxDoMyBeacon ? HAL_OK : HAL_ENOTSUPP;
default:
return HAL_EINVAL;
}
@@ -721,10 +853,11 @@ ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE
*regs,
int i;
for (i = 0; space >= 2*sizeof(uint32_t); i++) {
- u_int r = regs[i].start;
- u_int e = regs[i].end;
- *dp++ = (r<<16) | e;
- space -= sizeof(uint32_t);
+ uint32_t r = regs[i].start;
+ uint32_t e = regs[i].end;
+ *dp++ = r;
+ *dp++ = e;
+ space -= 2*sizeof(uint32_t);
do {
*dp++ = OS_REG_READ(ah, r);
r += sizeof(uint32_t);
@@ -748,6 +881,7 @@ ath_hal_getdiagstate(struct ath_hal *ah, int request,
const void *args, uint32_t argsize,
void **result, uint32_t *resultsize)
{
+
switch (request) {
case HAL_DIAG_REVS:
*result = &AH_PRIVATE(ah)->ah_devid;
@@ -805,6 +939,10 @@ ath_hal_getdiagstate(struct ath_hal *ah, int request,
} else
return AH_FALSE;
return AH_TRUE;
+ case HAL_DIAG_CHANSURVEY:
+ *result = &AH_PRIVATE(ah)->ah_chansurvey;
+ *resultsize = sizeof(HAL_CHANNEL_SURVEY);
+ return AH_TRUE;
}
return AH_FALSE;
}
@@ -940,7 +1078,7 @@ ath_hal_getChanNoise(struct ath_hal *ah, const struct
ieee80211_channel *chan)
* populated with values from NOISE_FLOOR[] + ath_hal_getNfAdjust().
*
* The caller must supply ctl/ext NF arrays which are at least
- * AH_MIMO_MAX_CHAINS entries long.
+ * AH_MAX_CHAINS entries long.
*/
int
ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
@@ -956,7 +1094,7 @@ ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"%s: invalid channel %u/0x%x; no mapping\n",
__func__, chan->ic_freq, chan->ic_flags);
- for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
+ for (i = 0; i < AH_MAX_CHAINS; i++) {
nf_ctl[i] = nf_ext[i] = 0;
}
return 0;
@@ -964,7 +1102,7 @@ ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
/* Return 0 if there's no valid MIMO values (yet) */
if (! (ichan->privFlags & CHANNEL_MIMO_NF_VALID)) {
- for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
+ for (i = 0; i < AH_MAX_CHAINS; i++) {
nf_ctl[i] = nf_ext[i] = 0;
}
return 0;
@@ -977,7 +1115,7 @@ ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
* stations which have a very low RSSI, below the
* 'normalised' NF values in NOISE_FLOOR[].
*/
- for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
+ for (i = 0; i < AH_MAX_CHAINS; i++) {
nf_ctl[i] = nf_ext[i] = NOISE_FLOOR[mode] +
ath_hal_getNfAdjust(ah, ichan);
}
@@ -996,7 +1134,7 @@ ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
* don't "wrap" when RSSI is less than the "adjusted" NF value.
* ("Adjust" here is via ichan->noiseFloorAdjust.)
*/
- for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
+ for (i = 0; i < AH_MAX_CHAINS; i++) {
nf_ctl[i] = ichan->noiseFloorCtl[i] +
ath_hal_getNfAdjust(ah, ichan);
nf_ext[i] = ichan->noiseFloorExt[i] +
ath_hal_getNfAdjust(ah, ichan);
}
@@ -1258,3 +1396,74 @@ ath_hal_getcca(struct ath_hal *ah)
return 1;
return ((diag & 0x500000) == 0);
}
+
+/*
+ * This routine is only needed when supporting EEPROM-in-RAM setups
+ * (eg embedded SoCs and on-board PCI/PCIe devices.)
+ */
+/* NB: This is in 16 bit words; not bytes */
+/* XXX This doesn't belong here! */
+#define ATH_DATA_EEPROM_SIZE 2048
+
+HAL_BOOL
+ath_hal_EepromDataRead(struct ath_hal *ah, u_int off, uint16_t *data)
+{
+ if (ah->ah_eepromdata == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: no eeprom data!\n", __func__);
+ return AH_FALSE;
+ }
+ if (off > ATH_DATA_EEPROM_SIZE) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: offset %x > %x\n",
+ __func__, off, ATH_DATA_EEPROM_SIZE);
+ return AH_FALSE;
+ }
+ (*data) = ah->ah_eepromdata[off];
+ return AH_TRUE;
+}
+
+/*
+ * Do a 2GHz specific MHz->IEEE based on the hardware
+ * frequency.
+ *
+ * This is the unmapped frequency which is programmed into the hardware.
+ */
+int
+ath_hal_mhz2ieee_2ghz(struct ath_hal *ah, int freq)
+{
+
+ if (freq == 2484)
+ return 14;
+ if (freq < 2484)
+ return ((int) freq - 2407) / 5;
+ else
+ return 15 + ((freq - 2512) / 20);
+}
+
+/*
+ * Clear the current survey data.
+ *
+ * This should be done during a channel change.
+ */
+void
+ath_hal_survey_clear(struct ath_hal *ah)
+{
+
+ OS_MEMZERO(&AH_PRIVATE(ah)->ah_chansurvey,
+ sizeof(AH_PRIVATE(ah)->ah_chansurvey));
+}
+
+/*
+ * Add a sample to the channel survey.
+ */
+void
+ath_hal_survey_add_sample(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
+{
+ HAL_CHANNEL_SURVEY *cs;
+
+ cs = &AH_PRIVATE(ah)->ah_chansurvey;
+
+ OS_MEMCPY(&cs->samples[cs->cur_sample], hs, sizeof(*hs));
+ cs->samples[cs->cur_sample].seq_num = cs->cur_seq;
+ cs->cur_sample = (cs->cur_sample + 1) % CHANNEL_SURVEY_SAMPLE_COUNT;
+ cs->cur_seq++;
+}
diff --git
a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.h
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.h
index f4254c14fa..08cd53a661 100644
--- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.h
+++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.h
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $FreeBSD$
+ * $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah.h 301043 2016-05-31 16:08:06Z
adrian $
*/
#ifndef _ATH_AH_H_
@@ -35,7 +35,7 @@
* This is intended to be used by various statistics gathering operations
* (NF, RSSI, EVM).
*/
-#define AH_MIMO_MAX_CHAINS 3
+#define AH_MAX_CHAINS 3
#define AH_MIMO_MAX_EVM_PILOTS 6
/*
@@ -73,6 +73,7 @@ typedef enum {
HAL_EINPROGRESS = 15, /* Operation incomplete */
HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
HAL_EEBADCC = 17, /* EEPROM invalid country code */
+ HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */
} HAL_STATUS;
typedef enum {
@@ -109,7 +110,7 @@ typedef enum {
HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
-
+ HAL_CAP_PCIE_PS = 29,
HAL_CAP_HT = 30, /* hardware can support HT */
HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout
*/
HAL_CAP_FAST_CC = 32, /* hardware supports fast channel
change */
@@ -118,7 +119,9 @@ typedef enum {
HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */
HAL_CAP_CST = 38, /* hardware supports carrier sense
timeout */
-
+ HAL_CAP_RIFS_RX = 39,
+ HAL_CAP_RIFS_TX = 40,
+ HAL_CAP_FORCE_PPM = 41,
HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr
aggregation */
HAL_CAP_DFS_DMN = 44, /* current DFS domain */
@@ -130,25 +133,73 @@ typedef enum {
HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation
*/
HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors
straddling a 4k page boundary */
HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */
+ HAL_CAP_BB_RIFS_HANG = 52,
+ HAL_CAP_RIFS_RX_ENABLED = 53,
+ HAL_CAP_BB_DFS_HANG = 54,
+
+ HAL_CAP_RX_STBC = 58,
+ HAL_CAP_TX_STBC = 59,
HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth
coexistence */
+ HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware
support */
+
+ HAL_CAP_DS = 67, /* 2 stream */
+ HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68,
+ HAL_CAP_MAC_HANG = 69, /* can MAC hang */
+ HAL_CAP_MFP = 70, /* Management Frame Protection in
hardware */
+
+ HAL_CAP_TS = 72, /* 3 stream */
+
+ HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */
+ HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit
descriptor */
+ HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */
+ HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor
*/
+ HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor
*/
+ HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */
+ HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */
+ HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */
+ HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */
+ HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */
+
+ HAL_CAP_BB_PANIC_WATCHDOG = 92,
HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
+ HAL_CAP_LDPC = 99,
+
HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */
+
+ HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */
+ HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy
restart to fix bb hang */
+ HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */
+ HAL_CAP_LDPCWAR = 108,
+ HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time,
usec */
+ HAL_CAP_ENABLE_APM = 110, /* APM enabled */
+ HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111,
+ HAL_CAP_PCIE_LCR_OFFSET = 112,
+
HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced
DFS */
+ HAL_CAP_MCI = 118,
+ HAL_CAP_SMARTANTENNA = 119,
+ HAL_CAP_TRAFFIC_FAST_RECOVER = 120,
+ HAL_CAP_TX_DIVERSITY = 121,
+ HAL_CAP_CRDC = 122,
/* The following are private to the FreeBSD HAL (224 onward) */
HAL_CAP_INTMIT = 229, /* interference mitigation */
HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */
HAL_CAP_BB_HANG = 235, /* can baseband hang */
- HAL_CAP_MAC_HANG = 236, /* can MAC hang */
HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */
HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */
HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are
available */
HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX
descriptor */
HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX
descriptor */
+ HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */
+ HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */
+ HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */
+ HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */
+ HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */
} HAL_CAPABILITY_TYPE;
/*
@@ -178,10 +229,26 @@ typedef enum {
HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */
+ HAL_TX_QUEUE_CFEND = 6,
+ HAL_TX_QUEUE_PAPRD = 7,
} HAL_TX_QUEUE;
#define HAL_NUM_TX_QUEUES 10 /* max possible # of
queues */
+/*
+ * Receive queue types. These are used to tag
+ * each transmit queue in the hardware and to identify a set
+ * of transmit queues for operations such as start/stop dma.
+ */
+typedef enum {
+ HAL_RX_QUEUE_HP = 0, /* high priority recv queue */
+ HAL_RX_QUEUE_LP = 1, /* low priority recv queue */
+} HAL_RX_QUEUE;
+
+#define HAL_NUM_RX_QUEUES 2 /* max possible # of
queues */
+
+#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth
*/
+
/*
* Transmit queue subtype. These map directly to
* WME Access Categories (except for UPSD). Refer
@@ -338,6 +405,7 @@ typedef enum {
HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
+ HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than
mine */
HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */
HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */
@@ -346,7 +414,7 @@ typedef enum {
/* Allow all mcast/bcast frames
*/
/*
- * Magic RX filter flags that aren't targetting hardware bits
+ * Magic RX filter flags that aren't targeting hardware bits
* but instead the HAL sets individual bits - eg PHYERR will result
* in OFDM/CCK timing error frames being received.
*/
@@ -360,6 +428,23 @@ typedef enum {
HAL_PM_UNDEFINED = 3
} HAL_POWER_MODE;
+/*
+ * Enterprise mode flags
+ */
+#define AH_ENT_DUAL_BAND_DISABLE 0x00000001
+#define AH_ENT_CHAIN2_DISABLE 0x00000002
+#define AH_ENT_5MHZ_DISABLE 0x00000004
+#define AH_ENT_10MHZ_DISABLE 0x00000008
+#define AH_ENT_49GHZ_DISABLE 0x00000010
+#define AH_ENT_LOOPBACK_DISABLE 0x00000020
+#define AH_ENT_TPC_PERF_DISABLE 0x00000040
+#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080
+#define AH_ENT_SPECTRAL_PRECISION 0x00000300
+#define AH_ENT_SPECTRAL_PRECISION_S 8
+#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000
+
+#define AH_FIRST_DESC_NDELIMS 60
+
/*
* NOTE WELL:
* These are mapped to take advantage of the common locations for many of
@@ -371,18 +456,24 @@ typedef enum {
*/
typedef enum {
HAL_INT_RX = 0x00000001, /* Non-common mapping */
- HAL_INT_RXDESC = 0x00000002,
+ HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */
+ HAL_INT_RXERR = 0x00000004,
+ HAL_INT_RXHP = 0x00000001, /* EDMA */
+ HAL_INT_RXLP = 0x00000002, /* EDMA */
HAL_INT_RXNOFRM = 0x00000008,
HAL_INT_RXEOL = 0x00000010,
HAL_INT_RXORN = 0x00000020,
HAL_INT_TX = 0x00000040, /* Non-common mapping */
HAL_INT_TXDESC = 0x00000080,
HAL_INT_TIM_TIMER= 0x00000100,
+ HAL_INT_MCI = 0x00000200,
+ HAL_INT_BBPANIC = 0x00000400,
HAL_INT_TXURN = 0x00000800,
HAL_INT_MIB = 0x00001000,
HAL_INT_RXPHY = 0x00004000,
HAL_INT_RXKCM = 0x00008000,
HAL_INT_SWBA = 0x00010000,
+ HAL_INT_BRSSI = 0x00020000,
HAL_INT_BMISS = 0x00040000,
HAL_INT_BNR = 0x00100000,
HAL_INT_TIM = 0x00200000, /* Non-common mapping */
@@ -392,6 +483,8 @@ typedef enum {
HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
+ /* Atheros ref driver has a generic timer interrupt now..*/
+ HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */
HAL_INT_CST = 0x10000000, /* Non-common mapping */
HAL_INT_GTT = 0x20000000, /* Non-common mapping */
HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
@@ -414,18 +507,86 @@ typedef enum {
| HAL_INT_RXKCM
| HAL_INT_SWBA
| HAL_INT_BMISS
+ | HAL_INT_BRSSI
| HAL_INT_BNR
| HAL_INT_GPIO,
} HAL_INT;
+/*
+ * MSI vector assignments
+ */
+typedef enum {
+ HAL_MSIVEC_MISC = 0,
+ HAL_MSIVEC_TX = 1,
+ HAL_MSIVEC_RXLP = 2,
+ HAL_MSIVEC_RXHP = 3,
+} HAL_MSIVEC;
+
typedef enum {
- HAL_GPIO_MUX_OUTPUT = 0,
- HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1,
- HAL_GPIO_MUX_PCIE_POWER_LED = 2,
- HAL_GPIO_MUX_TX_FRAME = 3,
- HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4,
- HAL_GPIO_MUX_MAC_NETWORK_LED = 5,
- HAL_GPIO_MUX_MAC_POWER_LED = 6
+ HAL_INT_LINE = 0,
+ HAL_INT_MSI = 1,
+} HAL_INT_TYPE;
+
+/* For interrupt mitigation registers */
+typedef enum {
+ HAL_INT_RX_FIRSTPKT=0,
+ HAL_INT_RX_LASTPKT,
+ HAL_INT_TX_FIRSTPKT,
+ HAL_INT_TX_LASTPKT,
+ HAL_INT_THRESHOLD
+} HAL_INT_MITIGATION;
+
+/* XXX this is duplicate information! */
+typedef struct {
+ u_int32_t cyclecnt_diff; /* delta cycle count */
+ u_int32_t rxclr_cnt; /* rx clear count */
+ u_int32_t extrxclr_cnt; /* ext chan rx clear count */
+ u_int32_t txframecnt_diff; /* delta tx frame count */
+ u_int32_t rxframecnt_diff; /* delta rx frame count */
+ u_int32_t listen_time; /* listen time in msec - time
for which ch is free */
+ u_int32_t ofdmphyerr_cnt; /* OFDM err count since last
reset */
+ u_int32_t cckphyerr_cnt; /* CCK err count since last
reset */
+ u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */
+ HAL_BOOL valid; /* if the stats are valid*/
+} HAL_ANISTATS;
+
+typedef struct {
+ u_int8_t txctl_offset;
+ u_int8_t txctl_numwords;
+ u_int8_t txstatus_offset;
+ u_int8_t txstatus_numwords;
+
+ u_int8_t rxctl_offset;
+ u_int8_t rxctl_numwords;
+ u_int8_t rxstatus_offset;
+ u_int8_t rxstatus_numwords;
+
+ u_int8_t macRevision;
+} HAL_DESC_INFO;
+
+typedef enum {
+ HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0,
+ HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1,
+ HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2,
+ HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3,
+ HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4,
+ HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5,
+ HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6,
+
+ HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA,
+ HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK,
+ HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA,
+ HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK,
+ HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX,
+ HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX,
+ HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX,
+ HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX,
+ HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE,
+ HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA,
+ HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0,
+ HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
+ HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2,
+ HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES
} HAL_GPIO_MUX_TYPE;
typedef enum {
@@ -434,6 +595,15 @@ typedef enum {
HAL_GPIO_INTR_DISABLE = 2
} HAL_GPIO_INTR_TYPE;
+typedef struct halCounters {
+ u_int32_t tx_frame_count;
+ u_int32_t rx_frame_count;
+ u_int32_t rx_clear_count;
+ u_int32_t cycle_count;
+ u_int8_t is_rx_active; // true (1) or false (0)
+ u_int8_t is_tx_active; // true (1) or false (0)
+} HAL_COUNTERS;
+
typedef enum {
HAL_RFGAIN_INACTIVE = 0,
HAL_RFGAIN_READ_REQUESTED = 1,
@@ -456,6 +626,17 @@ typedef struct {
uint32_t beacons;
} HAL_MIB_STATS;
+/*
+ * These bits represent what's in ah_currentRDext.
+ */
+typedef enum {
+ REG_EXT_FCC_MIDBAND = 0,
+ REG_EXT_JAPAN_MIDBAND = 1,
+ REG_EXT_FCC_DFS_HT40 = 2,
+ REG_EXT_JAPAN_NONDFS_HT40 = 3,
+ REG_EXT_JAPAN_DFS_HT40 = 4
+} REG_EXT_BITMAP;
+
enum {
HAL_MODE_11A = 0x001, /* 11a channels */
HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
@@ -483,7 +664,7 @@ enum {
typedef struct {
int rateCount; /* NB: for proper padding */
- uint8_t rateCodeToIndex[144]; /* back mapping */
+ uint8_t rateCodeToIndex[256]; /* back mapping */
struct {
uint8_t valid; /* valid for rate control use */
uint8_t phy; /* CCK/OFDM/XR */
@@ -497,12 +678,12 @@ typedef struct {
* rate; used for dur. calcs */
uint16_t lpAckDuration; /* long preamble ACK duration */
uint16_t spAckDuration; /* short preamble ACK duration*/
- } info[32];
+ } info[64];
} HAL_RATE_TABLE;
typedef struct {
u_int rs_count; /* number of valid entries */
- uint8_t rs_rates[32]; /* rates */
+ uint8_t rs_rates[64]; /* rates */
} HAL_RATE_SET;
/*
@@ -515,13 +696,16 @@ typedef enum {
typedef struct {
u_int Tries;
- u_int Rate;
+ u_int Rate; /* hardware rate code */
+ u_int RateIndex; /* rate series table index */
u_int PktDuration;
u_int ChSel;
u_int RateFlags;
#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this
series */
#define HAL_RATESERIES_2040 0x0002 /* use ext channel for
series */
#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for
series */
+#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series
*/
+ u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */
} HAL_11N_RATE_SERIES;
typedef enum {
@@ -545,6 +729,11 @@ typedef enum {
HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear
busy */
} HAL_HT_RXCLEAR;
+typedef enum {
+ HAL_FREQ_BAND_5GHZ = 0,
+ HAL_FREQ_BAND_2GHZ = 1,
+} HAL_FREQ_BAND;
+
/*
* Antenna switch control. By default antenna selection
* enables multiple (2) antenna use. To force use of the
@@ -564,15 +753,33 @@ typedef enum {
HAL_M_MONITOR = 8 /* Monitor mode */
} HAL_OPMODE;
+typedef enum {
+ HAL_RESET_NORMAL = 0, /* Do normal reset */
+ HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */
+ HAL_RESET_FORCE_COLD = 2, /* Force full reset */
+} HAL_RESET_TYPE;
+
typedef struct {
uint8_t kv_type; /* one of HAL_CIPHER */
- uint8_t kv_pad;
+ uint8_t kv_apsd; /* Mask for APSD enabled ACs */
uint16_t kv_len; /* length in bits */
uint8_t kv_val[16]; /* enough for 128-bit keys */
uint8_t kv_mic[8]; /* TKIP MIC key */
uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
} HAL_KEYVAL;
+/*
+ * This is the TX descriptor field which marks the key padding requirement.
+ * The naming is unfortunately unclear.
+ */
+#define AH_KEYTYPE_MASK 0x0F
+typedef enum {
+ HAL_KEY_TYPE_CLEAR,
+ HAL_KEY_TYPE_WEP,
+ HAL_KEY_TYPE_AES,
+ HAL_KEY_TYPE_TKIP,
+} HAL_KEY_TYPE;
+
typedef enum {
HAL_CIPHER_WEP = 0,
HAL_CIPHER_AES_OCB = 1,
@@ -601,9 +808,16 @@ typedef struct {
uint32_t bs_nexttbtt; /* next beacon in TU */
uint32_t bs_nextdtim; /* next DTIM in TU */
uint32_t bs_intval; /* beacon interval+flags */
+/*
+ * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF
+ * are all 1:1 correspondances with the pre-11n chip AR_BEACON
+ * register.
+ */
#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval
period */
+#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval,
tu/8 */
#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
+#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k
uS) */
uint32_t bs_dtimperiod;
uint16_t bs_cfpperiod; /* CFP period in TU */
uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
@@ -611,6 +825,7 @@ typedef struct {
uint16_t bs_timoffset; /* byte offset to TIM bitmap */
uint16_t bs_bmissthreshold; /* beacon miss threshold */
uint32_t bs_sleepduration; /* max sleep duration */
+ uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */
} HAL_BEACON_STATE;
/*
@@ -641,6 +856,49 @@ typedef struct {
#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and /
*/
+/*
+ * This is the ANI state and MIB stats.
+ *
+ * It's used by the HAL modules to keep state /and/ by the debug ioctl
+ * to fetch ANI information.
+ */
+typedef struct {
+ uint32_t ast_ani_niup; /* ANI increased noise immunity */
+ uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
+ uint32_t ast_ani_spurup; /* ANI increased spur immunity */
+ uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
+ uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
+ uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
+ uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
+ uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
+ uint32_t ast_ani_stepup; /* ANI increased first step level */
+ uint32_t ast_ani_stepdown;/* ANI decreased first step level */
+ uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
+ uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
+ uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
+ uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
+ uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
+ HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
+ HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
+} HAL_ANI_STATS;
+
+typedef struct {
+ uint8_t noiseImmunityLevel;
+ uint8_t spurImmunityLevel;
+ uint8_t firstepLevel;
+ uint8_t ofdmWeakSigDetectOff;
+ uint8_t cckWeakSigThreshold;
+ uint32_t listenTime;
+
+ /* NB: intentionally ordered so data exported to user space is first */
+ uint32_t txFrameCount; /* Last txFrameCount */
+ uint32_t rxFrameCount; /* Last rx Frame count */
+ uint32_t cycleCount; /* Last cycleCount
+ (to detect wrap-around) */
+ uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
+ uint32_t cckPhyErrCount; /* CCK err count since last reset */
+} HAL_ANI_STATE;
+
struct ath_desc;
struct ath_tx_status;
struct ath_rx_status;
@@ -658,7 +916,11 @@ typedef struct {
uint32_t tx_busy;
uint32_t rx_busy;
uint32_t chan_busy;
+ uint32_t ext_chan_busy;
uint32_t cycle_count;
+ /* XXX TODO */
+ uint32_t ofdm_phyerr_count;
+ uint32_t cck_phyerr_count;
} HAL_SURVEY_SAMPLE;
/*
@@ -691,8 +953,11 @@ typedef enum {
HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */
HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX
do not change) */
HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */
+ HAL_ANI_MRC_CCK = 8,
} HAL_ANI_CMD;
+#define HAL_ANI_ALL 0xffffffff
+
/*
* This is the layout of the ANI INTMIT capability.
*
@@ -731,10 +996,27 @@ typedef struct {
*/
int32_t pe_extchannel; /* Enable DFS on ext channel */
int32_t pe_enabled; /* Whether radar detection is enabled */
+ int32_t pe_enrelpwr;
+ int32_t pe_en_relstep_check;
} HAL_PHYERR_PARAM;
#define HAL_PHYERR_PARAM_NOVAL 65535
-#define HAL_PHYERR_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable
*/
+
+typedef struct {
+ u_int16_t ss_fft_period; /* Skip interval for FFT reports */
+ u_int16_t ss_period; /* Spectral scan period */
+ u_int16_t ss_count; /* # of reports to return from
ss_active */
+ u_int16_t ss_short_report;/* Set to report ony 1 set of FFT
results */
+ u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT
threshold configuration */
+ u_int16_t ss_spectral_pri; /* are we doing a noise
power cal ? */
+ int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values
for ctl+ext from eeprom */
+ int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for
ctl+ext from eeprom */
+ int32_t ss_nf_temp_data; /* temperature data taken
during nf scan */
+ int ss_enabled;
+ int ss_active;
+} HAL_SPECTRAL_PARAM;
+#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF
+#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if
applicable */
/*
* DFS operating mode flags.
@@ -746,6 +1028,39 @@ typedef enum {
HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */
} HAL_DFS_DOMAIN;
+
+/*
+ * MFP decryption options for initializing the MAC.
+ */
+typedef enum {
+ HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All
chips before Merlin. */
+ HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough
*/
+ HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do
it. */
+} HAL_MFP_OPT_T;
+
+/* LNA config supported */
+typedef enum {
+ HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0,
+ HAL_ANT_DIV_COMB_LNA2 = 1,
+ HAL_ANT_DIV_COMB_LNA1 = 2,
+ HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3,
+} HAL_ANT_DIV_COMB_LNA_CONF;
+
+typedef struct {
+ u_int8_t main_lna_conf;
+ u_int8_t alt_lna_conf;
+ u_int8_t fast_div_bias;
+ u_int8_t main_gaintb;
+ u_int8_t alt_gaintb;
+ u_int8_t antdiv_configgroup;
+ int8_t lna1_lna2_delta;
+} HAL_ANT_COMB_CONFIG;
+
+#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00
+#define HAL_ANTDIV_CONFIG_GROUP_1 0x01
+#define HAL_ANTDIV_CONFIG_GROUP_2 0x02
+#define HAL_ANTDIV_CONFIG_GROUP_3 0x03
+
/*
* Flag for setting QUIET period
*/
@@ -770,6 +1085,48 @@ struct hal_dfs_event {
};
typedef struct hal_dfs_event HAL_DFS_EVENT;
+/*
+ * Generic Timer domain
+ */
+typedef enum {
+ HAL_GEN_TIMER_TSF = 0,
+ HAL_GEN_TIMER_TSF2,
+ HAL_GEN_TIMER_TSF_ANY
+} HAL_GEN_TIMER_DOMAIN;
+
+/*
+ * BT Co-existence definitions
+ */
+#include "ath_hal/ah_btcoex.h"
+
+struct hal_bb_panic_info {
+ u_int32_t status;
+ u_int32_t tsf;
+ u_int32_t phy_panic_wd_ctl1;
+ u_int32_t phy_panic_wd_ctl2;
+ u_int32_t phy_gen_ctrl;
+ u_int32_t rxc_pcnt;
+ u_int32_t rxf_pcnt;
+ u_int32_t txf_pcnt;
+ u_int32_t cycles;
+ u_int32_t wd;
+ u_int32_t det;
+ u_int32_t rdar;
+ u_int32_t r_odfm;
+ u_int32_t r_cck;
+ u_int32_t t_odfm;
+ u_int32_t t_cck;
+ u_int32_t agc;
+ u_int32_t src;
+};
+
+/* Serialize Register Access Mode */
+typedef enum {
+ SER_REG_MODE_OFF = 0,
+ SER_REG_MODE_ON = 1,
+ SER_REG_MODE_AUTO = 2,
+} SER_REG_MODE;
+
typedef struct
{
int ah_debug; /* only used if AH_DEBUG is defined */
@@ -779,6 +1136,51 @@ typedef struct
int ah_dma_beacon_response_time;/* in TU's */
int ah_sw_beacon_response_time; /* in TU's */
int ah_additional_swba_backoff; /* in TU's */
+ int ah_force_full_reset; /* force full chip reset rather then
warm reset */
+ int ah_serialise_reg_war; /* force serialisation of register IO */
+
+ /* XXX these don't belong here, they're just for the ar9300 HAL port
effort */
+ int ath_hal_desc_tpc; /* Per-packet TPC */
+ int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */
+ int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */
+ int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */
+ int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */
+
+ /* I'm not sure what the default values for these should be */
+ int ath_hal_pll_pwr_save;
+ int ath_hal_pcie_power_save_enable;
+ int ath_hal_intr_mitigation_rx;
+ int ath_hal_intr_mitigation_tx;
+
+ int ath_hal_pcie_clock_req;
+#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0)
+#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1)
+#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2)
+
+ int ath_hal_pcie_waen;
+ int ath_hal_pcie_ser_des_write;
+
+ /* these are important for correct AR9300 behaviour */
+ int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */
+ int ath_hal_diversity_control;
+ int ath_hal_antenna_switch_swap;
+ int ath_hal_ext_lna_ctl_gpio;
+ int ath_hal_spur_mode;
+ int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */
+ int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */
+ int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */
+
+ /* For now, set this to 0 - net80211 needs to know about hardware MFP
support */
+ int ath_hal_mfp_support;
+
+ int ath_hal_enable_ani; /* should set this.. */
+ int ath_hal_cwm_ignore_ext_cca;
+ int ath_hal_show_bb_panic;
+ int ath_hal_ant_ctrl_comm2g_switch_enable;
+ int ath_hal_ext_atten_margin_cfg;
+ int ath_hal_min_gainidx;
+ int ath_hal_war70c;
+ uint32_t ath_hal_mci_config;
} HAL_OPS_CONFIG;
/*
@@ -809,6 +1211,12 @@ struct ath_hal {
uint16_t *ah_eepromdata; /* eeprom buffer, if needed */
+ uint32_t ah_intrstate[8]; /* last int state */
+ uint32_t ah_syncstate; /* last sync intr state */
+
+ /* Current powerstate from HAL calls */
+ HAL_POWER_MODE ah_powerMode;
+
HAL_OPS_CONFIG ah_config;
const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
u_int mode);
@@ -817,10 +1225,13 @@ struct ath_hal {
/* Reset functions */
HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
struct ieee80211_channel *,
- HAL_BOOL bChannelChange, HAL_STATUS *status);
+ HAL_BOOL bChannelChange,
+ HAL_RESET_TYPE resetType,
+ HAL_STATUS *status);
HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
- void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore);
+ void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore,
+ HAL_BOOL power_off);
void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
@@ -865,7 +1276,8 @@ struct ath_hal {
u_int txRate2, u_int txTries2,
u_int txRate3, u_int txTries3);
HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
- u_int segLen, HAL_BOOL firstSeg,
+ HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
+ u_int descId, u_int qcuId, HAL_BOOL firstSeg,
HAL_BOOL lastSeg, const struct ath_desc *);
HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
struct ath_desc *, struct ath_tx_status *);
@@ -873,10 +1285,20 @@ struct ath_hal {
void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct
ath_desc*);
HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *,
const struct ath_desc *ds, int *rates, int
*tries);
+ void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds,
+ uint32_t link);
+ void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds,
+ uint32_t *link);
+ void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds,
+ uint32_t **linkptr);
+ void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *,
+ void *ts_start, uint32_t ts_paddr_start,
+ uint16_t size);
+ void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *);
/* Receive Functions */
- uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
- void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
+ uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE);
+ void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp,
HAL_RX_QUEUE);
void __ahdecl(*ah_enableReceive)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
@@ -902,9 +1324,6 @@ struct ath_hal {
const struct ieee80211_channel *);
void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
const HAL_NODE_STATS *);
- void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *,
- struct ath_rx_status *,
- unsigned long, int);
/* Misc Functions */
HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
@@ -934,6 +1353,7 @@ struct ath_hal {
void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
+ void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t);
void __ahdecl(*ah_resetTsf)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
@@ -959,17 +1379,32 @@ struct ath_hal {
HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t
period,
uint32_t duration, uint32_t nextStart,
HAL_QUIET_FLAG flag);
+ void __ahdecl(*ah_setChainMasks)(struct ath_hal *,
+ uint32_t, uint32_t);
/* DFS functions */
void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
+ HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah,
+ HAL_PHYERR_PARAM *pe);
HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah,
struct ath_rx_status *rxs, uint64_t fulltsf,
const char *buf, HAL_DFS_EVENT *event);
HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah);
+ /* Spectral Scan functions */
+ void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah,
+ HAL_SPECTRAL_PARAM *sp);
+ void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah,
+ HAL_SPECTRAL_PARAM *sp);
+ void __ahdecl(*ah_spectralStart)(struct ath_hal *);
+ void __ahdecl(*ah_spectralStop)(struct ath_hal *);
+ HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *);
+ HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *);
+ /* XXX getNfPri() and getNfExt() */
+
/* Key Cache Functions */
uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
@@ -1001,9 +1436,12 @@ struct ath_hal {
/* 802.11n Functions */
HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *,
- struct ath_desc *, u_int, u_int, HAL_PKT_TYPE,
- u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL,
- HAL_BOOL);
+ struct ath_desc *,
+ HAL_DMA_ADDR *bufAddrList,
+ uint32_t *segLenList,
+ u_int, u_int, HAL_PKT_TYPE,
+ u_int, HAL_CIPHER, uint8_t, HAL_BOOL,
+ HAL_BOOL, HAL_BOOL);
HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *,
struct ath_desc *, u_int, u_int, u_int,
u_int, u_int, u_int, u_int, u_int);
@@ -1012,12 +1450,32 @@ struct ath_hal {
void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *,
struct ath_desc *, u_int, u_int,
HAL_11N_RATE_SERIES [], u_int, u_int);
+
+ /*
+ * The next 4 (set11ntxdesc -> set11naggrlast) are specific
+ * to the EDMA HAL. Descriptors are chained together by
+ * using filltxdesc (not ChainTxDesc) and then setting the
+ * aggregate flags appropriately using first/middle/last.
+ */
+ void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *,
+ void *, u_int, HAL_PKT_TYPE, u_int, u_int,
+ u_int);
+ void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *,
+ struct ath_desc *, u_int, u_int);
void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *,
struct ath_desc *, u_int);
+ void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *,
+ struct ath_desc *);
void __ahdecl(*ah_clr11nAggr)(struct ath_hal *,
struct ath_desc *);
void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *,
struct ath_desc *, u_int);
+ void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *,
+ struct ath_desc *, u_int);
+
+ HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *,
+ HAL_SURVEY_SAMPLE *);
+
uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *);
void __ahdecl(*ah_set11nMac2040)(struct ath_hal *,
HAL_HT_MACMODE);
@@ -1030,6 +1488,40 @@ struct ath_hal {
HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
+
+ /* Bluetooth Coexistence functions */
+ void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *,
+ HAL_BT_COEX_INFO *);
+ void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *,
+ HAL_BT_COEX_CONFIG *);
+ void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *,
+ int);
+ void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *,
+ uint32_t);
+ void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *,
+ uint32_t);
+ void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *,
+ uint32_t, uint32_t);
+ void __ahdecl(*ah_btCoexDisable)(struct ath_hal *);
+ int __ahdecl(*ah_btCoexEnable)(struct ath_hal *);
+
+ /* Bluetooth MCI methods */
+ void __ahdecl(*ah_btMciSetup)(struct ath_hal *,
+ uint32_t, void *, uint16_t, uint32_t);
+ HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *,
+ uint8_t, uint32_t, uint32_t *, uint8_t,
+ HAL_BOOL, HAL_BOOL);
+ uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *,
+ uint32_t *, uint32_t *);
+ uint32_t __ahdecl(*ah_btMciState)(struct ath_hal *,
+ uint32_t, uint32_t *);
+ void __ahdecl(*ah_btMciDetach)(struct ath_hal *);
+
+ /* LNA diversity configuration */
+ void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *,
+ HAL_ANT_COMB_CONFIG *);
+ void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *,
+ HAL_ANT_COMB_CONFIG *);
};
/*
@@ -1053,7 +1545,8 @@ extern const char *__ahdecl ath_hal_probe(uint16_t
vendorid, uint16_t devid);
* be returned if the status parameter is non-zero.
*/
extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
- HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS*
status);
+ HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
+ HAL_OPS_CONFIG *ah_config, HAL_STATUS* status);
extern const char *ath_hal_mac_name(struct ath_hal *);
extern const char *ath_hal_rf_name(struct ath_hal *);
@@ -1121,6 +1614,12 @@ extern void __ahdecl ath_hal_process_noisefloor(struct
ath_hal *ah);
*/
extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);
+/*
+ * Get the HAL wireless mode for the given channel.
+ */
+extern int ath_hal_get_curmode(struct ath_hal *ah,
+ const struct ieee80211_channel *chan);
+
/*
* Calculate the packet TX time for a legacy or 11n frame
*/
@@ -1156,4 +1655,20 @@ void __ahdecl ath_hal_setcca(struct ath_hal *ah, int
ena);
*/
int __ahdecl ath_hal_getcca(struct ath_hal *ah);
+/*
+ * Read EEPROM data from ah_eepromdata
+ */
+HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah,
+ u_int off, uint16_t *data);
+
+/*
+ * For now, simply pass through MFP frames.
+ */
+static inline u_int32_t
+ath_hal_get_mfp_qos(struct ath_hal *ah)
+{
+ //return AH_PRIVATE(ah)->ah_mfp_qos;
+ return HAL_MFP_QOSDATA;
+}
+
#endif /* _ATH_AH_H_ */
diff --git
a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_btcoex.h
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_btcoex.h
new file mode 100644
index 0000000000..5c91f3a6c8
--- /dev/null
+++
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_btcoex.h
@@ -0,0 +1,523 @@
+/*
+ * Copyright (c) 2014 Qualcomm Atheros, Inc.
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_btcoex.h 301303 2016-06-04
07:28:09Z adrian $
+ */
+#ifndef __ATH_HAL_BTCOEX_H__
+#define __ATH_HAL_BTCOEX_H__
+
+/*
+ * General BT coexistence definitions.
+ */
+typedef enum {
+ HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
+ HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */
+ HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */
+ HAL_MAX_BT_MODULES
+} HAL_BT_MODULE;
+
+typedef struct {
+ HAL_BT_MODULE bt_module;
+ u_int8_t bt_coex_config;
+ u_int8_t bt_gpio_bt_active;
+ u_int8_t bt_gpio_bt_priority;
+ u_int8_t bt_gpio_wlan_active;
+ u_int8_t bt_active_polarity;
+ HAL_BOOL bt_single_ant;
+ u_int8_t bt_isolation;
+} HAL_BT_COEX_INFO;
+
+typedef enum {
+ HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
+ HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */
+ HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */
+ HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */
+} HAL_BT_COEX_MODE;
+
+typedef enum {
+ HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */
+ HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */
+ HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */
+ HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */
+ HAL_BT_COEX_CFG_3WIRE, /* 3-wire */
+ HAL_BT_COEX_CFG_MCI /* MCI */
+} HAL_BT_COEX_CFG;
+
+typedef enum {
+ HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
+ HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */
+ HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */
+ HAL_BT_COEX_MCI_MAX_TX_PWR, /* Set max tx power for concurrent tx */
+ HAL_BT_COEX_MCI_FTP_STOMP_RX, /* Use a different weight for stomp low
*/
+} HAL_BT_COEX_SET_PARAMETER;
+
+/*
+ * MCI specific coexistence definitions.
+ */
+
+#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
+#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
+/* Check Rx Diversity is allowed */
+#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
+/* Check Diversity is on or off */
+#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
+
+#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
+/* main: LNA1, alt: LNA2 */
+#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
+#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
+#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09
+#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02
+#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06
+
+#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30
+
+#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666
+
+#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02
+
+#define HAL_BT_COEX_LOW_ACK_POWER 0x0
+#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f
+
+typedef enum {
+ HAL_BT_COEX_NO_STOMP = 0,
+ HAL_BT_COEX_STOMP_ALL,
+ HAL_BT_COEX_STOMP_LOW,
+ HAL_BT_COEX_STOMP_NONE,
+ HAL_BT_COEX_STOMP_ALL_FORCE,
+ HAL_BT_COEX_STOMP_LOW_FORCE,
+ HAL_BT_COEX_STOMP_AUDIO,
+} HAL_BT_COEX_STOMP_TYPE;
+
+typedef struct {
+ /* extend rx_clear after tx/rx to protect the burst (in usec). */
+ u_int8_t bt_time_extend;
+
+ /*
+ * extend rx_clear as long as txsm is
+ * transmitting or waiting for ack.
+ */
+ HAL_BOOL bt_txstate_extend;
+
+ /*
+ * extend rx_clear so that when tx_frame
+ * is asserted, rx_clear will drop.
+ */
+ HAL_BOOL bt_txframe_extend;
+
+ /*
+ * coexistence mode
+ */
+ HAL_BT_COEX_MODE bt_mode;
+
+ /*
+ * treat BT high priority traffic as
+ * a quiet collision
+ */
+ HAL_BOOL bt_quiet_collision;
+
+ /*
+ * invert rx_clear as WLAN_ACTIVE
+ */
+ HAL_BOOL bt_rxclear_polarity;
+
+ /*
+ * slotted mode only. indicate the time in usec
+ * from the rising edge of BT_ACTIVE to the time
+ * BT_PRIORITY can be sampled to indicate priority.
+ */
+ u_int8_t bt_priority_time;
+
+ /*
+ * slotted mode only. indicate the time in usec
+ * from the rising edge of BT_ACTIVE to the time
+ * BT_PRIORITY can be sampled to indicate tx/rx and
+ * BT_FREQ is sampled.
+ */
+ u_int8_t bt_first_slot_time;
+
+ /*
+ * slotted mode only. rx_clear and bt_ant decision
+ * will be held the entire time that BT_ACTIVE is asserted,
+ * otherwise the decision is made before every slot boundary.
+ */
+ HAL_BOOL bt_hold_rxclear;
+} HAL_BT_COEX_CONFIG;
+
+#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
+#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
+#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx
Diversity is allowed */
+#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity
is on or off */
+#define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010
+#define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020
+
+#define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time
stamp */
+
+typedef enum mci_message_header {
+ MCI_LNA_CTRL = 0x10, /* len = 0 */
+ MCI_CONT_NACK = 0x20, /* len = 0 */
+ MCI_CONT_INFO = 0x30, /* len = 4 */
+ MCI_CONT_RST = 0x40, /* len = 0 */
+ MCI_SCHD_INFO = 0x50, /* len = 16 */
+ MCI_CPU_INT = 0x60, /* len = 4 */
+ MCI_SYS_WAKING = 0x70, /* len = 0 */
+ MCI_GPM = 0x80, /* len = 16 */
+ MCI_LNA_INFO = 0x90, /* len = 1 */
+ MCI_LNA_STATE = 0x94,
+ MCI_LNA_TAKE = 0x98,
+ MCI_LNA_TRANS = 0x9c,
+ MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
+ MCI_REQ_WAKE = 0xc0, /* len = 0 */
+ MCI_DEBUG_16 = 0xfe, /* len = 2 */
+ MCI_REMOTE_RESET = 0xff /* len = 16 */
+} MCI_MESSAGE_HEADER;
+
+/* Default remote BT device MCI COEX version */
+#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3
+#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
+/* Local WLAN MCI COEX version */
+#define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3
+#define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
+
+typedef enum mci_gpm_subtype {
+ MCI_GPM_BT_CAL_REQ = 0,
+ MCI_GPM_BT_CAL_GRANT = 1,
+ MCI_GPM_BT_CAL_DONE = 2,
+ MCI_GPM_WLAN_CAL_REQ = 3,
+ MCI_GPM_WLAN_CAL_GRANT = 4,
+ MCI_GPM_WLAN_CAL_DONE = 5,
+ MCI_GPM_COEX_AGENT = 0x0C,
+ MCI_GPM_RSVD_PATTERN = 0xFE,
+ MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE,
+ MCI_GPM_BT_DEBUG = 0xFF
+} MCI_GPM_SUBTYPE_T;
+
+typedef enum mci_gpm_coex_opcode {
+ MCI_GPM_COEX_VERSION_QUERY = 0,
+ MCI_GPM_COEX_VERSION_RESPONSE = 1,
+ MCI_GPM_COEX_STATUS_QUERY = 2,
+ MCI_GPM_COEX_HALT_BT_GPM = 3,
+ MCI_GPM_COEX_WLAN_CHANNELS = 4,
+ MCI_GPM_COEX_BT_PROFILE_INFO = 5,
+ MCI_GPM_COEX_BT_STATUS_UPDATE = 6,
+ MCI_GPM_COEX_BT_UPDATE_FLAGS = 7
+} MCI_GPM_COEX_OPCODE_T;
+
+typedef enum mci_gpm_coex_query_type {
+ /* WLAN information */
+ MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01,
+ /* BT information */
+ MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01,
+ MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02,
+ MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04
+} MCI_GPM_COEX_QUERY_TYPE_T;
+
+typedef enum mci_gpm_coex_halt_bt_gpm {
+ MCI_GPM_COEX_BT_GPM_UNHALT = 0,
+ MCI_GPM_COEX_BT_GPM_HALT = 1
+} MCI_GPM_COEX_HALT_BT_GPM_T;
+
+typedef enum mci_gpm_coex_profile_type {
+ MCI_GPM_COEX_PROFILE_UNKNOWN = 0,
+ MCI_GPM_COEX_PROFILE_RFCOMM = 1,
+ MCI_GPM_COEX_PROFILE_A2DP = 2,
+ MCI_GPM_COEX_PROFILE_HID = 3,
+ MCI_GPM_COEX_PROFILE_BNEP = 4,
+ MCI_GPM_COEX_PROFILE_VOICE = 5,
+ MCI_GPM_COEX_PROFILE_MAX
+} MCI_GPM_COEX_PROFILE_TYPE_T;
+
+typedef enum mci_gpm_coex_profile_state {
+ MCI_GPM_COEX_PROFILE_STATE_END = 0,
+ MCI_GPM_COEX_PROFILE_STATE_START = 1
+} MCI_GPM_COEX_PROFILE_STATE_T;
+
+typedef enum mci_gpm_coex_profile_role {
+ MCI_GPM_COEX_PROFILE_SLAVE = 0,
+ MCI_GPM_COEX_PROFILE_MASTER = 1
+} MCI_GPM_COEX_PROFILE_ROLE_T;
+
+typedef enum mci_gpm_coex_bt_status_type {
+ MCI_GPM_COEX_BT_NONLINK_STATUS = 0,
+ MCI_GPM_COEX_BT_LINK_STATUS = 1
+} MCI_GPM_COEX_BT_STATUS_TYPE_T;
+
+typedef enum mci_gpm_coex_bt_status_state {
+ MCI_GPM_COEX_BT_NORMAL_STATUS = 0,
+ MCI_GPM_COEX_BT_CRITICAL_STATUS = 1
+} MCI_GPM_COEX_BT_STATUS_STATE_T;
+
+#define MCI_GPM_INVALID_PROFILE_HANDLE 0xff
+
+typedef enum mci_gpm_coex_bt_updata_flags_op {
+ MCI_GPM_COEX_BT_FLAGS_READ = 0x00,
+ MCI_GPM_COEX_BT_FLAGS_SET = 0x01,
+ MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02
+} MCI_GPM_COEX_BT_FLAGS_OP_T;
+
+/* MCI GPM/Coex opcode/type definitions */
+enum {
+ MCI_GPM_COEX_W_GPM_PAYLOAD = 1,
+ MCI_GPM_COEX_B_GPM_TYPE = 4,
+ MCI_GPM_COEX_B_GPM_OPCODE = 5,
+ /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
+ MCI_GPM_WLAN_CAL_W_SEQUENCE = 2,
+ /* MCI_GPM_COEX_VERSION_QUERY */
+ /* MCI_GPM_COEX_VERSION_RESPONSE */
+ MCI_GPM_COEX_B_MAJOR_VERSION = 6,
+ MCI_GPM_COEX_B_MINOR_VERSION = 7,
+ /* MCI_GPM_COEX_STATUS_QUERY */
+ MCI_GPM_COEX_B_BT_BITMAP = 6,
+ MCI_GPM_COEX_B_WLAN_BITMAP = 7,
+ /* MCI_GPM_COEX_HALT_BT_GPM */
+ MCI_GPM_COEX_B_HALT_STATE = 6,
+ /* MCI_GPM_COEX_WLAN_CHANNELS */
+ MCI_GPM_COEX_B_CHANNEL_MAP = 6,
+ /* MCI_GPM_COEX_BT_PROFILE_INFO */
+ MCI_GPM_COEX_B_PROFILE_TYPE = 6,
+ MCI_GPM_COEX_B_PROFILE_LINKID = 7,
+ MCI_GPM_COEX_B_PROFILE_STATE = 8,
+ MCI_GPM_COEX_B_PROFILE_ROLE = 9,
+ MCI_GPM_COEX_B_PROFILE_RATE = 10,
+ MCI_GPM_COEX_B_PROFILE_VOTYPE = 11,
+ MCI_GPM_COEX_H_PROFILE_T = 12,
+ MCI_GPM_COEX_B_PROFILE_W = 14,
+ MCI_GPM_COEX_B_PROFILE_A = 15,
+ /* MCI_GPM_COEX_BT_STATUS_UPDATE */
+ MCI_GPM_COEX_B_STATUS_TYPE = 6,
+ MCI_GPM_COEX_B_STATUS_LINKID = 7,
+ MCI_GPM_COEX_B_STATUS_STATE = 8,
+ /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
+ MCI_GPM_COEX_B_BT_FLAGS_OP = 10,
+ MCI_GPM_COEX_W_BT_FLAGS = 6
+};
[ *** diff truncated: 46034 lines dropped *** ]
