hrev51685 adds 1 changeset to branch 'master'
old head: 46f7052c65219fcc7c899bc7812015d1b94beac9
new head: 11790e14ef21425bbf483ec21360a458f03e5bb9
overview:
http://cgit.haiku-os.org/haiku/log/?qt=range&q=11790e14ef21+%5E46f7052c6521
----------------------------------------------------------------------------
11790e14ef21: kernel/drivers: Kill Beceem WiMAX driver. RIP
I wrote this back in 2010 as my first driver project.
Reasons to remove it:
* The license is GPL
* Current WiMAX hardware is generally WIFI based.
* It controlled the hardware, but never worked
for network access since we need SSL certs and stuff
which vendors weren't too open with.
* WiMAX kind of died (at least in the US)
I left the wwan directory, it would be a nice spot
for CDMA / GSM dongle drivers.
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev51685
Commit: 11790e14ef21425bbf483ec21360a458f03e5bb9
URL: http://cgit.haiku-os.org/haiku/commit/?id=11790e14ef21
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Sun Dec 17 15:18:15 2017 UTC
----------------------------------------------------------------------------
23 files changed, 5655 deletions(-)
build/jam/images/definitions/minimum | 3 -
src/add-ons/kernel/drivers/network/wwan/Jamfile | 2 -
.../network/wwan/usb_beceemwmx/BeceemCPU.cpp | 166 ---
.../network/wwan/usb_beceemwmx/BeceemCPU.h | 43 -
.../network/wwan/usb_beceemwmx/BeceemDDR.cpp | 396 ------
.../network/wwan/usb_beceemwmx/BeceemDDR.h | 38 -
.../network/wwan/usb_beceemwmx/BeceemDDRTiming.h | 849 ------------
.../network/wwan/usb_beceemwmx/BeceemDevice.cpp | 1299 ------------------
.../network/wwan/usb_beceemwmx/BeceemDevice.h | 138 --
.../network/wwan/usb_beceemwmx/BeceemLED.cpp | 330 -----
.../network/wwan/usb_beceemwmx/BeceemLED.h | 59 -
.../network/wwan/usb_beceemwmx/BeceemNVM.cpp | 880 ------------
.../network/wwan/usb_beceemwmx/BeceemNVM.h | 140 --
.../network/wwan/usb_beceemwmx/DeviceStruct.h | 521 -------
.../network/wwan/usb_beceemwmx/Driver.cpp | 368 -----
.../drivers/network/wwan/usb_beceemwmx/Driver.h | 126 --
.../drivers/network/wwan/usb_beceemwmx/Jamfile | 16 -
.../drivers/network/wwan/usb_beceemwmx/README | 29 -
.../network/wwan/usb_beceemwmx/Settings.cpp | 129 --
.../network/wwan/usb_beceemwmx/Settings.h | 38 -
.../wwan/usb_beceemwmx/usb_beceemwmx.settings | 33 -
.../drivers/network/wwan/usb_beceemwmx/util.cpp | 39 -
.../drivers/network/wwan/usb_beceemwmx/util.h | 13 -
----------------------------------------------------------------------------
diff --git a/build/jam/images/definitions/minimum
b/build/jam/images/definitions/minimum
index e639d35..737de4a 100644
--- a/build/jam/images/definitions/minimum
+++ b/build/jam/images/definitions/minimum
@@ -208,9 +208,6 @@ SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures
ralinkwifi
wavelanwifi
}@ # x86,x86_64
-
- # WWAN drivers
- #usb_beceemwmx@gpl
] ;
SYSTEM_ADD_ONS_DRIVERS_POWER = [ FFilterByBuildFeatures
diff --git a/src/add-ons/kernel/drivers/network/wwan/Jamfile
b/src/add-ons/kernel/drivers/network/wwan/Jamfile
index 4422668..fd1dc3d 100644
--- a/src/add-ons/kernel/drivers/network/wwan/Jamfile
+++ b/src/add-ons/kernel/drivers/network/wwan/Jamfile
@@ -1,3 +1 @@
SubDir HAIKU_TOP src add-ons kernel drivers network wwan ;
-
-#SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network wwan usb_beceemwmx
;
diff --git
a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemCPU.cpp
b/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemCPU.cpp
deleted file mode 100644
index 1f07fc6..0000000
--- a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemCPU.cpp
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Beceem WiMax USB Driver.
- * Copyright (c) 2010 Alexander von Gluck <kallisti5@xxxxxxxxxxx>
- * Distributed under the terms of the GNU General Public License.
- *
- * Based on GPL code developed by: Beceem Communications Pvt. Ltd
- *
- * Control the MIPS cpu within the Beceem chipset.
- *
- */
-
-
-#include "BeceemCPU.h"
-#include "Driver.h"
-#include "Settings.h"
-
-
-BeceemCPU::BeceemCPU()
-{
- TRACE("Debug: Load CPU handler\n");
-}
-
-
-status_t
-BeceemCPU::CPUInit(WIMAX_DEVICE* swmxdevice)
-{
- TRACE("Debug: Init CPU handler\n");
- fWmxDevice = swmxdevice;
- return B_OK;
-}
-
-
-status_t
-BeceemCPU::CPURun()
-{
- uint32 clockRegister = 0;
-
- // Read current clock register contents
- if (BizarroReadRegister(CLOCK_RESET_CNTRL_REG_1,
- sizeof(clockRegister), &clockRegister) != B_OK) {
- TRACE_ALWAYS("Error: Read of clock reset reg failure\n");
- return B_ERROR;
- }
-
- // Adjust clock register contents to start cpu
- if (fWmxDevice->CPUFlashBoot)
- clockRegister &= ~(1 << 30);
- else
- clockRegister |= (1 << 30);
-
- // Write new clock register contents
- if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
- sizeof(clockRegister), &clockRegister) != B_OK) {
- TRACE_ALWAYS("Error: Write of clock reset reg failure\n");
- return B_ERROR;
- }
-
- return B_OK;
-}
-
-
-status_t
-BeceemCPU::CPUReset()
-{
- uint32 value = 0;
-
- if (fWmxDevice->deviceChipID >= T3LPB) {
- BizarroReadRegister(SYS_CFG, sizeof(value), &value);
- BizarroReadRegister(SYS_CFG, sizeof(value), &value);
- // SYS_CFG register is write protected hence for
modifying
- // this reg value, it should be read twice before
writing.
-
- value = value | (fWmxDevice->syscfgBefFw & 0x00000060);
- // making bit[6...5] same as was before f/w download.
this
- // setting forces the h/w to re-populated the SP RAM
area
- // with the string descriptor .
-
- if (BizarroWriteRegister(SYS_CFG, sizeof(value), &value) !=
B_OK) {
- TRACE_ALWAYS("Error: unable to write SYS_CFG during
reset\n");
- return B_ERROR;
- }
- }
-
- /* Reset the UMA-B Device */
- if (fWmxDevice->deviceChipID >= T3LPB) {
- // Reset UMA-B
- // TODO : USB reset needs implimented
- /*
- if (usb_reset_device(psIntfAdapter->udev) != B_OK) {
- TRACE_ALWAYS("Error: USB Reset failed\n");
- retrun B_ERROR;
- }
- */
-
- if (fWmxDevice->deviceChipID == BCS220_2
- || fWmxDevice->deviceChipID == BCS220_2BC
- || fWmxDevice->deviceChipID == BCS250_BC
- || fWmxDevice->deviceChipID == BCS220_3) {
- if (BizarroReadRegister(HPM_CONFIG_LDO145,
- sizeof(value), &value) != B_OK) {
- TRACE_ALWAYS("Error: USB read failed during
reset\n");
- return B_ERROR;
- }
- // set 0th bit
- value |= (1<<0);
-
- if (BizarroWriteRegister(HPM_CONFIG_LDO145,
- sizeof(value), &value) != B_OK) {
- TRACE_ALWAYS("Error: USB write failed during
reset\n");
- return B_ERROR;
- }
- }
-
- }
- // TODO : ELSE OLDER CHIP ID's < T3LP see Misc.c:1048
-
- uint32 uiResetValue = 0;
-
- if (fWmxDevice->CPUFlashBoot) {
- // In flash boot mode MIPS state register has reverse polarity.
- // So just or with setting bit 30.
- // Make the MIPS in Reset state.
- if (BizarroReadRegister(CLOCK_RESET_CNTRL_REG_1,
- sizeof(uiResetValue), &uiResetValue) != B_OK) {
- TRACE_ALWAYS("Error: read failed during FlashBoot
device reset\n");
- return B_ERROR;
- }
- // set 30th bit
- uiResetValue |= (1 << 30);
-
- if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
- sizeof(uiResetValue), &uiResetValue) != B_OK) {
- TRACE_ALWAYS("Error: write failed during FlashBoot
device reset\n");
- return B_ERROR;
- }
- }
-
- if (fWmxDevice->deviceChipID >= T3LPB) {
- uiResetValue = 0;
- // WA for SYSConfig Issue.
- BizarroReadRegister(SYS_CFG, sizeof(uiResetValue),
&uiResetValue);
- if (uiResetValue & (1 << 4)) {
- uiResetValue = 0;
- BizarroReadRegister(SYS_CFG, sizeof(uiResetValue),
&uiResetValue);
- // Read SYSCFG Twice to make it writable.
- uiResetValue &= ~(1 << 4);
-
- if (BizarroWriteRegister(SYS_CFG,
- sizeof(uiResetValue), &uiResetValue) != B_OK) {
- TRACE_ALWAYS("Error: unable to write SYS_CFG
during reset\n");
- return B_ERROR;
- }
- }
-
- }
-
- uiResetValue = 0;
- if (BizarroWriteRegister(0x0f01186c,
- sizeof(uiResetValue), &uiResetValue) != B_OK) {
- TRACE_ALWAYS("Error: unable to write reset to 0x0f01186c\n");
- return B_ERROR;
- }
-
- return B_OK;
-}
-
diff --git a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemCPU.h
b/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemCPU.h
deleted file mode 100644
index 5d8d762..0000000
--- a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemCPU.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Beceem WiMax USB Driver.
- * Copyright (c) 2010 Alexander von Gluck <kallisti5@xxxxxxxxxxx>
- * Distributed under the terms of the MIT license.
- *
- * Description: Wrangle Beceem CPU control calls
- */
-#ifndef _USB_BECEEM_CPU_H_
-#define _USB_BECEEM_CPU_H_
-
-
-#include <ByteOrder.h>
-#include "DeviceStruct.h"
-
-
-#define CLOCK_RESET_CNTRL_REG_1 0x0F00000C
-
-
-class BeceemCPU {
-public:
- BeceemCPU();
- status_t CPUInit(WIMAX_DEVICE*
swmxdevice);
- status_t CPURun();
- status_t CPUReset();
-
-// yuck. These are in a parent class
- virtual status_t ReadRegister(uint32 reg, size_t
size,
- uint32*
buffer) { return NULL; };
- virtual status_t WriteRegister(uint32 reg,
size_t size,
- uint32*
buffer) { return NULL; };
- virtual status_t BizarroReadRegister(uint32 reg,
- size_t
size, uint32* buffer)
-
{ return NULL; };
- virtual status_t BizarroWriteRegister(uint32 reg,
- size_t
size, uint32* buffer)
-
{ return NULL; };
-
-private:
- WIMAX_DEVICE* fWmxDevice;
-
-};
-#endif // _USB_BECEEM_CPU_H_
-
diff --git
a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDR.cpp
b/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDR.cpp
deleted file mode 100644
index 397aa79..0000000
--- a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDR.cpp
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * Beceem WiMax USB Driver.
- * Copyright (c) 2010 Alexander von Gluck <kallisti5@xxxxxxxxxxx>
- * Distributed under the terms of the GNU General Public License.
- *
- * Based on GPL code developed by: Beceem Communications Pvt. Ltd
- *
- * Description: Wrangle Beceem volatile DDR memory.
- */
-
-
-#include "BeceemDDR.h"
-#include "BeceemDDRTiming.h"
-#include "Settings.h"
-
-
-BeceemDDR::BeceemDDR()
-{
- TRACE("Debug: Load DDR handler\n");
-}
-
-
-status_t
-BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
-{
- fWmxDevice = swmxdevice;
- PDDR_SETTING psDDRSetting = NULL;
-
- uint32 chipID = fWmxDevice->deviceChipID;
-
- unsigned long registerCount = 0;
- unsigned long value = 0;
- uint32 uiResetValue = 0;
- uint32 uiClockSetting = 0;
- int retval = B_OK;
-
- // Grab the Config6 metric from the vendor config and convert endianness
- uint32 vendorConfig6raw = fWmxDevice->vendorcfg.HostDrvrConfig6;
- vendorConfig6raw &= ~(htonl(1 << 15));
- uint32 vendorConfig6 = ntohl(vendorConfig6raw);
-
- // Read our vendor provided Config6 metric and populate memory settings
- uint32 vendorDDRSetting = (ntohl(vendorConfig6raw) >> 8) & 0x0F;
- bool vendorPmuMode = (vendorConfig6 >> 24) & 0x03;
- bool vendorMipsConfig = (vendorConfig6 >> 20) & 0x01;
- bool vendorPLLConfig = (vendorConfig6 >> 19) & 0x01;
-
- switch (chipID) {
- case 0xbece3200:
- switch (vendorDDRSetting) {
- case DDR_80_MHZ:
- psDDRSetting = asT3LP_DDRSetting80MHz;
- registerCount =
sizeof(asT3LP_DDRSetting80MHz)
- / sizeof(DDR_SETTING);
- break;
-
- case DDR_100_MHZ:
- psDDRSetting = asT3LP_DDRSetting100MHz;
- registerCount =
sizeof(asT3LP_DDRSetting100MHz)
- / sizeof(DDR_SETTING);
- break;
-
- case DDR_133_MHZ:
- psDDRSetting = asT3LP_DDRSetting133MHz;
- registerCount =
sizeof(asT3LP_DDRSetting133MHz)
- / sizeof(DDR_SETTING);
- if (vendorMipsConfig == MIPS_200_MHZ)
- uiClockSetting = 0x03F13652;
- else
- uiClockSetting = 0x03F1365B;
- break;
-
- default:
- return B_BAD_VALUE;
- }
- break;
-
- case T3LPB:
- case BCS220_2:
- case BCS220_2BC:
- case BCS250_BC:
- case BCS220_3 :
- // We need to check current value and additionally set
bit 2 and
- // bit 6 to 1 for BBIC 2mA drive
- if ((chipID != BCS220_2)
- && (chipID != BCS220_2BC)
- && (chipID != BCS220_3)) {
- retval = BizarroReadRegister((uint32)0x0f000830,
- sizeof(uiResetValue), &uiResetValue);
-
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- uiResetValue |= 0x44;
- retval =
BizarroWriteRegister((uint32)0x0f000830,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d
BizarroWriteRegister failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- }
-
- switch(vendorDDRSetting) {
- case DDR_80_MHZ:
- TRACE("Debug: DDR 80MHz\n");
- psDDRSetting = asT3LPB_DDRSetting80MHz;
- registerCount =
sizeof(asT3B_DDRSetting80MHz)
- / sizeof(DDR_SETTING);
- break;
-
- case DDR_100_MHZ:
- TRACE("Debug: DDR 100MHz\n");
- psDDRSetting = asT3LPB_DDRSetting100MHz;
- registerCount =
sizeof(asT3B_DDRSetting100MHz)
- / sizeof(DDR_SETTING);
- break;
-
- case DDR_133_MHZ:
- TRACE("Debug: DDR 133MHz\n");
- psDDRSetting = asT3LPB_DDRSetting133MHz;
- registerCount =
sizeof(asT3B_DDRSetting133MHz)
- / sizeof(DDR_SETTING);
-
- if (vendorMipsConfig == MIPS_200_MHZ)
- uiClockSetting = 0x03F13652;
- else
- uiClockSetting = 0x03F1365B;
- break;
-
- case DDR_160_MHZ:
- TRACE("Debug: DDR 160MHz\n");
- psDDRSetting = asT3LPB_DDRSetting160MHz;
- registerCount =
sizeof(asT3LPB_DDRSetting160MHz)
- / sizeof(DDR_SETTING);
-
- if (vendorMipsConfig == MIPS_200_MHZ) {
- TRACE("Debug: MIPS 200Mhz\n");
- uiClockSetting = 0x03F137D2;
- } else {
- uiClockSetting = 0x03F137DB;
- }
- }
- break;
-
- case 0xbece0110:
- case 0xbece0120:
- case 0xbece0121:
- case 0xbece0130:
- case 0xbece0300:
- switch (vendorDDRSetting) {
- case DDR_80_MHZ:
- psDDRSetting = asT3_DDRSetting80MHz;
- registerCount =
sizeof(asT3_DDRSetting80MHz)
- / sizeof(DDR_SETTING);
- break;
-
- case DDR_100_MHZ:
- psDDRSetting = asT3_DDRSetting100MHz;
- registerCount =
sizeof(asT3_DDRSetting100MHz)
- / sizeof(DDR_SETTING);
- break;
-
- case DDR_133_MHZ:
- psDDRSetting = asT3_DDRSetting133MHz;
- registerCount =
sizeof(asT3_DDRSetting133MHz)
- / sizeof(DDR_SETTING);
- break;
-
- default:
- return B_BAD_VALUE;
- }
- break;
- case 0xbece0310:
- {
- switch (vendorDDRSetting) {
- case DDR_80_MHZ:
- psDDRSetting = asT3B_DDRSetting80MHz;
- registerCount =
sizeof(asT3B_DDRSetting80MHz)
- / sizeof(DDR_SETTING);
- break;
-
- case DDR_100_MHZ:
- psDDRSetting = asT3B_DDRSetting100MHz;
- registerCount =
sizeof(asT3B_DDRSetting100MHz)
- / sizeof(DDR_SETTING);
- break;
-
- case DDR_133_MHZ:
- if (vendorPLLConfig == PLL_266_MHZ) {
- // 266Mhz PLL selected.
- memcpy(asT3B_DDRSetting133MHz,
asDPLL_266MHZ,
- sizeof(asDPLL_266MHZ));
- psDDRSetting =
asT3B_DDRSetting133MHz;
- registerCount =
sizeof(asT3B_DDRSetting133MHz)
- / sizeof(DDR_SETTING);
-
- } else {
- psDDRSetting =
asT3B_DDRSetting133MHz;
- registerCount =
sizeof(asT3B_DDRSetting133MHz)
- / sizeof(DDR_SETTING);
-
- if (vendorMipsConfig ==
MIPS_200_MHZ)
- uiClockSetting =
0x07F13652;
- else
- uiClockSetting =
0x07F1365B;
- }
- break;
-
- default:
- return B_BAD_VALUE;
- }
- break;
- }
-
- default:
- return B_BAD_VALUE;
- }
-
- value = 0;
- TRACE("Debug: Register count is %lu\n", registerCount);
- while (registerCount && !retval) {
- if (uiClockSetting && psDDRSetting->ulRegAddress ==
MIPS_CLOCK_REG)
- value = uiClockSetting;
- else
- value = psDDRSetting->ulRegValue;
-
- retval = BizarroWriteRegister(psDDRSetting->ulRegAddress,
- sizeof(value), (uint32*)&value);
-
- if (B_OK != retval) {
- TRACE_ALWAYS(
- "%s:%d BizarroWriteRegister failed at 0x%x on
Register #%d.\n",
- __FUNCTION__, __LINE__,
psDDRSetting->ulRegAddress,
- registerCount);
- break;
- }
-
- registerCount--;
- psDDRSetting++;
- }
-
- if (chipID >= 0xbece3300) {
- snooze(3);
- if ((chipID != BCS220_2)
- && (chipID != BCS220_2BC)
- && (chipID != BCS220_3)) {
- /* drive MDDR to half in case of UMA-B: */
- uiResetValue = 0x01010001;
- retval = BizarroWriteRegister((uint32)0x0F007018,
- sizeof(uiResetValue), &uiResetValue);
-
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroWriteRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- uiResetValue = 0x00040020;
- retval = BizarroWriteRegister((uint32)0x0F007094,
- sizeof(uiResetValue), &uiResetValue);
-
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroWriteRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- uiResetValue = 0x01020101;
- retval = BizarroWriteRegister((uint32)0x0F00701c,
- sizeof(uiResetValue), &uiResetValue);
-
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroWriteRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- uiResetValue = 0x01010000;
- retval = BizarroWriteRegister((uint32)0x0F007018,
- sizeof(uiResetValue), &uiResetValue);
-
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroWriteRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- }
- snooze(3);
-
- /* DC/DC standby change...
- * This is to be done only for Hybrid PMU mode.
- * with the current h/w there is no way to detect this.
- * and since we dont have internal PMU lets do it under
- * UMA-B chip id. we will change this when we will have an
- * internal PMU.
- */
- if (vendorPmuMode == HYBRID_MODE_7C) {
- TRACE("Debug: Hybrid Power Mode 7C\n");
- retval = BizarroReadRegister((uint32)0x0f000c00,
- sizeof(uiResetValue), &uiResetValue);
-
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- retval = BizarroReadRegister((uint32)0x0f000c00,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- uiResetValue = 0x1322a8;
- retval = BizarroWriteRegister((uint32)0x0f000d1c,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroWriteRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- retval = BizarroReadRegister((uint32)0x0f000c00,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- retval = BizarroReadRegister((uint32)0x0f000c00,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- uiResetValue = 0x132296;
- retval = BizarroWriteRegister((uint32)0x0f000d14,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroWriteRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- } else if (vendorPmuMode == HYBRID_MODE_6) {
-
- TRACE("Debug: Hybrid Power Mode 6\n");
- retval = BizarroReadRegister((uint32)0x0f000c00,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- retval = BizarroReadRegister((uint32)0x0f000c00,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- uiResetValue = 0x6003229a;
- retval = BizarroWriteRegister((uint32)0x0f000d14,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroWriteRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- retval = BizarroReadRegister((uint32)0x0f000c00,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- retval = BizarroReadRegister((uint32)0x0f000c00,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroReadRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- uiResetValue = 0x1322a8;
- retval = BizarroWriteRegister((uint32)0x0f000d1c,
- sizeof(uiResetValue), &uiResetValue);
- if (retval < 0) {
- TRACE_ALWAYS("%s:%d BizarroWriteRegister
failed\n",
- __FUNCTION__, __LINE__);
- return retval;
- }
- }
-
- }
- return retval;
-}
-
diff --git a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDR.h
b/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDR.h
deleted file mode 100644
index ee7784b..0000000
--- a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDR.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Beceem WiMax USB Driver.
- * Copyright (c) 2010 Alexander von Gluck <kallisti5@xxxxxxxxxxx>
- * Distributed under the terms of the MIT license.
- *
- * Description: Wrangle Beceem volatile DDR memory.
- */
-#ifndef _USB_BECEEM_DDR_H_
-#define _USB_BECEEM_DDR_H_
-
-
-#include <ByteOrder.h>
-#include "DeviceStruct.h"
-
-
-class BeceemDDR {
-public:
- BeceemDDR();
- status_t DDRInit(WIMAX_DEVICE*
swmxdevice);
-
- WIMAX_DEVICE* fWmxDevice;
-
- // yuck. These are in a child class class
- virtual status_t ReadRegister(uint32 reg, size_t
size,
- uint32*
buffer) { return NULL; };
- virtual status_t WriteRegister(uint32 reg,
size_t size,
- uint32*
buffer) { return NULL; };
- virtual status_t BizarroReadRegister(uint32 reg,
- size_t
size, uint32* buffer)
-
{ return NULL; };
- virtual status_t BizarroWriteRegister(uint32 reg,
- size_t
size, uint32* buffer)
-
{ return NULL; };
-
-};
-
-
-#endif /* _USB_BECEEM_DDR_H_ */
diff --git
a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDRTiming.h
b/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDRTiming.h
deleted file mode 100644
index 194143f..0000000
--- a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDRTiming.h
+++ /dev/null
@@ -1,849 +0,0 @@
-/*
- * Beceem WiMax USB Driver.
- * Copyright (c) 2010 Alexander von Gluck <kallisti5@xxxxxxxxxxx>
- * Distributed under the terms of the GNU General Public License.
- *
- * Based on GPL code developed by: Beceem Communications Pvt. Ltd
- *
- * Description: Beceem DDR memory timings
- */
-#ifndef _USB_BECEEM_DDR_TIMING_H_
-#define _USB_BECEEM_DDR_TIMING_H_
-
-
-#include <ByteOrder.h>
-#include "DeviceStruct.h"
-
-
-#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
-#define MIPS_CLOCK_REG 0x0f000820
-
-#define MIPS_200_MHZ 0
-#define MIPS_160_MHZ 1
-#define PLL_800_MHZ 0
-#define PLL_266_MHZ 1
-
-#define DDR_80_MHZ 0
-#define DDR_100_MHZ 1
-#define DDR_120_MHZ 2 // Additional Frequency for T3LP
-#define DDR_133_MHZ 3
-#define DDR_140_MHZ 4 // Not Used (Reserved for future)
-#define DDR_160_MHZ 5 // Additional Frequency for T3LP
-#define DDR_180_MHZ 6 // Not Used (Reserved for future)
-#define DDR_200_MHZ 7 // Not Used (Reserved for future)
-
-
-/*
- * DDR Power modes
- */
-typedef enum ePMU_MODES
-{
- HYBRID_MODE_7C = 0,
- INTERNAL_MODE_6 = 1,
- HYBRID_MODE_6 = 2
-}PMU_MODE;
-
-
-/*
- * DDR Init maps, taken from Beceem GPL Linux Driver
- */
-typedef struct _DDR_SETTING
-{
- unsigned long ulRegAddress;
- unsigned long ulRegValue;
-} DDR_SETTING, *PDDR_SETTING;
-
-
-typedef DDR_SETTING DDR_SET_NODE, *PDDR_SET_NODE;
-
-
-// DDR INIT 133Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 // index for 0x0F007000
-static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// DPLL Clock Setting
- {0x0F000800, 0x00007212},
- {0x0f000820, 0x07F13FFF},
- {0x0f000810, 0x00000F95},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- // Changed source for Xbar and MIPS clock to APLL
- {0x0f000840, 0x0FFF1B00},
- {0x0f000870, 0x00000002},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- {0x0F00a04C, 0x0000000C},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01010100},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
- {0x0F007024, 0x02000007},
- {0x0F007028, 0x02020202},
- {0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
- {0x0F007030, 0x05000000},
- {0x0F007034, 0x00000003},
- {0x0F007038, 0x110a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
- {0x0F00703C, 0x02101010}, // ROB - 0x02101010, 0x02101018},
- {0x0F007040, 0x45751200}, // ROB - 0x45751200, 0x450f1200},
- {0x0F007044, 0x110a0d00}, // ROB - 0x110a0d00, 0x111f0d00
- {0x0F007048, 0x081b0306},
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0000001c},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x0010246c},
- {0x0F007064, 0x00000010},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00007000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- // # Enable BW improvement within memory controller
- {0x0F007094, 0x00000104},
- // # Enable 2 ports within Xbar
- {0x0F00A000, 0x00000016},
- // # Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-// 80Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 // index for 0x0F007000
-static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// DPLL Clock Setting
- {0x0f000810, 0x00000F95},
- {0x0f000820, 0x07f1ffff},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- {0x0F00a000, 0x00000016},
- {0x0F00a04C, 0x0000000C},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01000000},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020000},
- {0x0F007020, 0x04020107},
- {0x0F007024, 0x00000007},
- {0x0F007028, 0x02020201},
- {0x0F00702c, 0x0204040a},
- {0x0F007030, 0x04000000},
- {0x0F007034, 0x00000002},
- {0x0F007038, 0x1F060200},
- {0x0F00703C, 0x1C22221F},
- {0x0F007040, 0x8A006600},
- {0x0F007044, 0x221a0800},
- {0x0F007048, 0x02690204},
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0000001c},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x000A15D6},
- {0x0F007064, 0x0000000A},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00004000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- {0x0F007094, 0x00000104},
- // Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-// 100Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 // index for 0x0F007000
-static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// DPLL Clock Setting
- {0x0F000800, 0x00007008},
- {0x0f000810, 0x00000F95},
- {0x0f000820, 0x07F13E3F},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- // Changed source for Xbar and MIPS clock to APLL
- // 0x0f000840, 0x0FFF1800,
- {0x0f000840, 0x0FFF1B00},
- {0x0f000870, 0x00000002},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- {0x0F00a04C, 0x0000000C},
- // Enable 2 ports within Xbar
- {0x0F00A000, 0x00000016},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01010100},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001}, // POP - 0x00020000 Normal 0x01020000
- {0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
- {0x0F007024, 0x00000007},
- {0x0F007028, 0x01020201},
- {0x0F00702c, 0x0204040A},
- {0x0F007030, 0x06000000},
- {0x0F007034, 0x00000004},
- {0x0F007038, 0x20080200},
- {0x0F00703C, 0x02030320},
- {0x0F007040, 0x6E7F1200},
- {0x0F007044, 0x01190A00},
- {0x0F007048, 0x06120305}, // 0x02690204 // 0x06120305
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0000001C},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x00082ED6},
- {0x0F007064, 0x0000000A},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00005000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- // Enable BW improvement within memory controller
- {0x0F007094, 0x00000104},
- // Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-// Net T3B DDR Settings
-// DDR INIT 133Mhz
-static DDR_SET_NODE asDPLL_266MHZ[] = {
- {0x0F000800, 0x00007212},
- {0x0f000820, 0x07F13FFF},
- {0x0f000810, 0x00000F95},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- // Changed source for X - bar and MIPS clock to APLL
- {0x0f000840, 0x0FFF1B00},
- {0x0f000870, 0x00000002}
-};
-
-
-#if 0
-static DDR_SET_NODE asDPLL_800MHZ[] = {
- {0x0f000810, 0x00000F95},
- {0x0f000810, 0x00000F95},
- {0x0f000810, 0x00000F95},
- {0x0f000820, 0x03F1365B},
- {0x0f000840, 0x0FFF0000},
- {0x0f000880, 0x000003DD},
- {0x0f000860, 0x00000000}
-};
-#endif
-
-
-#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 // index for 0x0F007000
-static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// DPLL Clock Setting
- {0x0f000810, 0x00000F95},
- {0x0f000810, 0x00000F95},
- {0x0f000810, 0x00000F95},
- {0x0f000820, 0x07F13652},
- {0x0f000840, 0x0FFF0800},
- // Changed source for Xbar and MIPS clock to APLL
- {0x0f000880, 0x000003DD},
- {0x0f000860, 0x00000000},
- // Changed source for Xbar and MIPS clock to APLL
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- // Enable 2 ports within Xbar
- {0x0F00A000, 0x00000016},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01010100},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
- {0x0F007024, 0x02000007},
- {0x0F007028, 0x02020202},
- {0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
- {0x0F007030, 0x05000000},
- {0x0F007034, 0x00000003},
- {0x0F007038, 0x130a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
- {0x0F00703C, 0x02101012}, // ROB - 0x02101010, 0x02101018},
- {0x0F007040, 0x457D1200}, // ROB - 0x45751200, 0x450f1200},
- {0x0F007044, 0x11130d00}, // ROB - 0x110a0d00, 0x111f0d00
- {0x0F007048, 0x040D0306},
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0000001c},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x0010246c},
- {0x0F007064, 0x00000012},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00007000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- // # Enable BW improvement within memory controller
- {0x0F007094, 0x00000104},
- // # Enable start bit within memory controller
- {0x0F007018, 0x01010000},
-};
-
-
-#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
-static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// DPLL Clock Setting
- {0x0f000810, 0x00000F95},
- {0x0f000820, 0x07F13FFF},
- {0x0f000840, 0x0FFF1F00},
- {0x0f000880, 0x000003DD},
- {0x0f000860, 0x00000000},
-
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- {0x0F00a000, 0x00000016},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01000000},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020000},
- {0x0F007020, 0x04020107},
- {0x0F007024, 0x00000007},
- {0x0F007028, 0x02020201},
- {0x0F00702c, 0x0204040a},
- {0x0F007030, 0x04000000},
- {0x0F007034, 0x02000002},
- {0x0F007038, 0x1F060202},
- {0x0F00703C, 0x1C22221F},
- {0x0F007040, 0x8A006600},
- {0x0F007044, 0x221a0800},
- {0x0F007048, 0x02690204},
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0100001c},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x000A15D6},
- {0x0F007064, 0x0000000A},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00004000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- {0x0F007094, 0x00000104},
- // Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-// 100Mhz
-#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 // index for 0x0F007000
-static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// DPLL Clock Setting
- {0x0f000810, 0x00000F95},
- {0x0f000820, 0x07F1369B},
- {0x0f000840, 0x0FFF0800},
- {0x0f000880, 0x000003DD},
- {0x0f000860, 0x00000000},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- // Enable 2 ports within Xbar
- {0x0F00A000, 0x00000016},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01010100},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020000}, // POP - 0x00020000 Normal 0x01020000
- {0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
- {0x0F007024, 0x00000007},
- {0x0F007028, 0x01020201},
- {0x0F00702c, 0x0204040A},
- {0x0F007030, 0x06000000},
- {0x0F007034, 0x02000004},
- {0x0F007038, 0x20080200},
- {0x0F00703C, 0x02030320},
- {0x0F007040, 0x6E7F1200},
- {0x0F007044, 0x01190A00},
- {0x0F007048, 0x06120305}, // 0x02690204 // 0x06120305
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0100001C},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x00082ED6},
- {0x0F007064, 0x0000000A},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00005000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- // # Enable BW improvement within memory controller
- {0x0F007094, 0x00000104},
- // # Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 // index for 0x0F007000
-static DDR_SET_NODE asT3LP_DDRSetting133MHz[] = {// DPLL Clock Setting
- {0x0f000820, 0x03F1365B},
- {0x0f000810, 0x00002F95},
- {0x0f000880, 0x000003DD},
- // Changed source for Xbar and MIPS clock to APLL
- {0x0f000840, 0x0FFF0000},
- {0x0f000860, 0x00000000},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- {0x0F00A000, 0x00000016},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01010100},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
- {0x0F007024, 0x02000007},
- {0x0F007028, 0x02020200},
- {0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
- {0x0F007030, 0x05000000},
- {0x0F007034, 0x00000003},
- {0x0F007038, 0x200a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
- {0x0F00703C, 0x02101020}, // ROB - 0x02101010, 0x02101018,
- {0x0F007040, 0x45711200}, // ROB - 0x45751200, 0x450f1200,
- {0x0F007044, 0x110D0D00}, // ROB - 0x110a0d00, 0x111f0d00
- {0x0F007048, 0x04080306},
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0100001c},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x0010245F},
- {0x0F007064, 0x00000010},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00007000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- {0x0F007088, 0x01000001},
- {0x0F00708c, 0x00000101},
- {0x0F007090, 0x00000000},
- // Enable BW improvement within memory controller
- {0x0F007094, 0x00040000},
- {0x0F007098, 0x00000000},
- {0x0F0070c8, 0x00000104},
- // Enable 2 ports within Xbar
- // Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 // index for 0x0F007000
-static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
- {0x0f000810, 0x00002F95},
- {0x0f000820, 0x03F1369B},
- {0x0f000840, 0x0fff0000},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- // Changed source for Xbar and MIPS clock to APLL
- {0x0f000840, 0x0FFF0000},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01010100},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020000}, // POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
- {0x0F007024, 0x00000007},
- {0x0F007028, 0x01020200},
- {0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
- {0x0F007030, 0x06000000},
- {0x0F007034, 0x00000004},
- {0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
- {0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
- {0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
- {0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
- {0x0F007048, 0x03000305},
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0100001c},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x00082ED6},
- {0x0F007064, 0x0000000A},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00005000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- {0x0F007088, 0x01000001},
- {0x0F00708c, 0x00000101},
- {0x0F007090, 0x00000000},
- {0x0F007094, 0x00010000},
- {0x0F007098, 0x00000000},
- {0x0F0070C8, 0x00000104},
- // Enable 2 ports within Xbar
- {0x0F00A000, 0x00000016},
- // Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
-static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
- {0x0f000820, 0x07F13FFF},
- {0x0f000810, 0x00002F95},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- {0x0f000840, 0x0FFF1F00},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0F00a084, 0x1Cffffff},
- {0x0F00a080, 0x1C000000},
- {0x0F00A000, 0x00000016},
- {0x0f007000, 0x00010001},
- {0x0f007004, 0x01000000},
- {0x0f007008, 0x01000001},
- {0x0f00700c, 0x00000000},
- {0x0f007010, 0x01000000},
- {0x0f007014, 0x01000100},
- {0x0f007018, 0x01000000},
- {0x0f00701c, 0x01020000},
- {0x0f007020, 0x04020107},
- {0x0f007024, 0x00000007},
- {0x0f007028, 0x02020200},
- {0x0f00702c, 0x0204040a},
- {0x0f007030, 0x04000000},
- {0x0f007034, 0x00000002},
- {0x0f007038, 0x1d060200},
- {0x0f00703c, 0x1c22221d},
- {0x0f007040, 0x8A116600},
- {0x0f007044, 0x222d0800},
- {0x0f007048, 0x02690204},
- {0x0f00704c, 0x00000000},
- {0x0f007050, 0x0100001c},
- {0x0f007054, 0x00000000},
- {0x0f007058, 0x00000000},
- {0x0f00705c, 0x00000000},
- {0x0f007060, 0x000A15D6},
- {0x0f007064, 0x0000000A},
- {0x0f007068, 0x00000000},
- {0x0f00706c, 0x00000001},
- {0x0f007070, 0x00004000},
- {0x0f007074, 0x00000000},
- {0x0f007078, 0x00000000},
- {0x0f00707c, 0x00000000},
- {0x0f007080, 0x00000000},
- {0x0f007084, 0x00000000},
- {0x0f007088, 0x01000001},
- {0x0f00708c, 0x00000101},
- {0x0f007090, 0x00000000},
- {0x0f007094, 0x00010000},
- {0x0f007098, 0x00000000},
- {0x0F0070C8, 0x00000104},
- {0x0F007018, 0x01010000}
-};
-
-
-// T3 LP-B (UMA-B)
-#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 // index for 0x0F007000
-static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
- {0x0f000820, 0x03F137DB},
- {0x0f000810, 0x01842795},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- {0x0f000840, 0x0FFF0400},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to
20 MHz
- {0x0F00a084, 0x1Cffffff}, // Now dump from her in internal memory
- {0x0F00a080, 0x1C000000},
- {0x0F00A000, 0x00000016},
- {0x0f007000, 0x00010001},
- {0x0f007004, 0x01000001},
- {0x0f007008, 0x01000101},
- {0x0f00700c, 0x00000000},
- {0x0f007010, 0x01000100},
- {0x0f007014, 0x01000100},
- {0x0f007018, 0x01000000},
- {0x0f00701c, 0x01020000},
- {0x0f007020, 0x04030107},
- {0x0f007024, 0x02000007},
- {0x0f007028, 0x02020200},
- {0x0f00702c, 0x0206060a},
- {0x0f007030, 0x050d0d00},
- {0x0f007034, 0x00000003},
- {0x0f007038, 0x170a0200},
- {0x0f00703c, 0x02101012},
- {0x0f007040, 0x45161200},
- {0x0f007044, 0x11250c00},
- {0x0f007048, 0x04da0307},
- {0x0f00704c, 0x00000000},
- {0x0f007050, 0x0000001c},
- {0x0f007054, 0x00000000},
- {0x0f007058, 0x00000000},
- {0x0f00705c, 0x00000000},
- {0x0f007060, 0x00142bb6},
- {0x0f007064, 0x20430014},
- {0x0f007068, 0x00000000},
- {0x0f00706c, 0x00000001},
- {0x0f007070, 0x00009000},
- {0x0f007074, 0x00000000},
- {0x0f007078, 0x00000000},
- {0x0f00707c, 0x00000000},
- {0x0f007080, 0x00000000},
- {0x0f007084, 0x00000000},
- {0x0f007088, 0x01000001},
- {0x0f00708c, 0x00000101},
- {0x0f007090, 0x00000000},
- {0x0f007094, 0x00040000},
- {0x0f007098, 0x00000000},
- {0x0F0070C8, 0x00000104},
- {0x0F007018, 0x01010000}
-};
-
-
-#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 // index for 0x0F007000
-static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
- {0x0f000820, 0x03F1365B},
- {0x0f000810, 0x00002F95},
- {0x0f000880, 0x000003DD},
- // Changed source for Xbar and MIPS clock to APLL
- {0x0f000840, 0x0FFF0000},
- {0x0f000860, 0x00000000},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to
20 MHz
- {0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
- {0x0F00a080, 0x1C000000},
- {0x0F00A000, 0x00000016},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01010100},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
- {0x0F007024, 0x02000007},
- {0x0F007028, 0x02020200},
- {0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
- {0x0F007030, 0x05000000},
- {0x0F007034, 0x00000003},
- {0x0F007038, 0x190a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
- {0x0F00703C, 0x02101017}, // ROB - 0x02101010, 0x02101018,
- {0x0F007040, 0x45171200}, // ROB - 0x45751200, 0x450f1200,
- {0x0F007044, 0x11290D00}, // ROB - 0x110a0d00, 0x111f0d00
- {0x0F007048, 0x04080306},
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0100001c},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x0010245F},
- {0x0F007064, 0x00000010},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00007000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- {0x0F007088, 0x01000001},
- {0x0F00708c, 0x00000101},
- {0x0F007090, 0x00000000},
- // Enable BW improvement within memory controller
- {0x0F007094, 0x00040000},
- {0x0F007098, 0x00000000},
- {0x0F0070c8, 0x00000104},
- // Enable 2 ports within Xbar
- // Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 // index for 0x0F007000
-static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
- {0x0f000810, 0x00002F95},
- {0x0f000820, 0x03F1369B},
- {0x0f000840, 0x0fff0000},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- // Changed source for Xbar and MIPS clock to APLL
- {0x0f000840, 0x0FFF0000},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to
20 MHz
- {0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
- {0x0F00a080, 0x1C000000},
- // Memcontroller Default values
- {0x0F007000, 0x00010001},
- {0x0F007004, 0x01010100},
- {0x0F007008, 0x01000001},
- {0x0F00700c, 0x00000000},
- {0x0F007010, 0x01000000},
- {0x0F007014, 0x01000100},
- {0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020000}, // POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
- {0x0F007024, 0x00000007},
- {0x0F007028, 0x01020200},
- {0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
- {0x0F007030, 0x06000000},
- {0x0F007034, 0x00000004},
- {0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
- {0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
- {0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
- {0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
- {0x0F007048, 0x03000305},
- {0x0F00704c, 0x00000000},
- {0x0F007050, 0x0100001c},
- {0x0F007054, 0x00000000},
- {0x0F007058, 0x00000000},
- {0x0F00705c, 0x00000000},
- {0x0F007060, 0x00082ED6},
- {0x0F007064, 0x0000000A},
- {0x0F007068, 0x00000000},
- {0x0F00706c, 0x00000001},
- {0x0F007070, 0x00005000},
- {0x0F007074, 0x00000000},
- {0x0F007078, 0x00000000},
- {0x0F00707C, 0x00000000},
- {0x0F007080, 0x00000000},
- {0x0F007084, 0x00000000},
- {0x0F007088, 0x01000001},
- {0x0F00708c, 0x00000101},
- {0x0F007090, 0x00000000},
- {0x0F007094, 0x00010000},
- {0x0F007098, 0x00000000},
- {0x0F0070C8, 0x00000104},
- // # Enable 2 ports within Xbar
- {0x0F00A000, 0x00000016},
- // # Enable start bit within memory controller
- {0x0F007018, 0x01010000}
-};
-
-
-#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 // index for 0x0F007000
-static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// DPLL Clock Setting
- {0x0f000820, 0x07F13FFF},
- {0x0f000810, 0x00002F95},
- {0x0f000860, 0x00000000},
- {0x0f000880, 0x000003DD},
- {0x0f000840, 0x0FFF1F00},
- {0x0F00a044, 0x1fffffff},
- {0x0F00a040, 0x1f000000},
- {0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to
20 MHz
- {0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
- {0x0F00a080, 0x1C000000},
- {0x0F00A000, 0x00000016},
- {0x0f007000, 0x00010001},
- {0x0f007004, 0x01000000},
- {0x0f007008, 0x01000001},
- {0x0f00700c, 0x00000000},
- {0x0f007010, 0x01000000},
- {0x0f007014, 0x01000100},
- {0x0f007018, 0x01000000},
- {0x0f00701c, 0x01020000},
- {0x0f007020, 0x04020107},
- {0x0f007024, 0x00000007},
- {0x0f007028, 0x02020200},
- {0x0f00702c, 0x0204040a},
- {0x0f007030, 0x04000000},
- {0x0f007034, 0x00000002},
- {0x0f007038, 0x1d060200},
- {0x0f00703c, 0x1c22221d},
- {0x0f007040, 0x8A116600},
- {0x0f007044, 0x222d0800},
- {0x0f007048, 0x02690204},
- {0x0f00704c, 0x00000000},
- {0x0f007050, 0x0100001c},
- {0x0f007054, 0x00000000},
- {0x0f007058, 0x00000000},
- {0x0f00705c, 0x00000000},
- {0x0f007060, 0x000A15D6},
- {0x0f007064, 0x0000000A},
- {0x0f007068, 0x00000000},
- {0x0f00706c, 0x00000001},
- {0x0f007070, 0x00004000},
- {0x0f007074, 0x00000000},
- {0x0f007078, 0x00000000},
- {0x0f00707c, 0x00000000},
- {0x0f007080, 0x00000000},
- {0x0f007084, 0x00000000},
- {0x0f007088, 0x01000001},
- {0x0f00708c, 0x00000101},
- {0x0f007090, 0x00000000},
- {0x0f007094, 0x00010000},
- {0x0f007098, 0x00000000},
- {0x0F0070C8, 0x00000104},
- {0x0F007018, 0x01010000}
-};
-
-
-#endif // _USB_BECEEM_DDR_TIMING_H_
-
diff --git
a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDevice.cpp
b/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDevice.cpp
deleted file mode 100644
index 314369f..0000000
--- a/src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDevice.cpp
+++ /dev/null
@@ -1,1299 +0,0 @@
-/*
- * Beceem WiMax USB Driver
- * Copyright (c) 2010 Alexander von Gluck <kallisti5@xxxxxxxxxxx>
- * Distributed under the terms of the GNU General Public License.
- *
- * Based on GPL code developed by: Beceem Communications Pvt. Ltd
- *
- * Authors:
- * Alexander von Gluck, <kallisti5@xxxxxxxxxxx>
- *
- * Partially using:
- * USB Ethernet Control Model devices
- * (c) 2008 by Michael Lotz, <mmlr@xxxxxxxx>
- * ASIX AX88172/AX88772/AX88178 USB 2.0 Ethernet Driver
- * (c) 2008 by S.Zharski, <imker@xxxxxx>
- *
- * This code is the entry point for the operating system to
- * Beceem device communications.
- */
-
-
-#include <sys/ioctl.h>
-#include <unistd.h>
-
-#include "util.h"
-
-#ifdef HAIKU_TARGET_PLATFORM_HAIKU
-#include <lock.h> // for mutex
-#else
-#include "BeOSCompatibility.h" // for pseudo mutex
-#endif
-
-#include "BeceemDevice.h"
-#include "Driver.h"
-#include "Settings.h"
-
-
-mutex gUSBLock;
-
-
-// auto-release helper class
-class USBSmartLock {
-public:
- USBSmartLock() { mutex_lock(&gUSBLock); }
- ~USBSmartLock() { mutex_unlock(&gUSBLock); }
-};
-
-
-status_t
-BeceemDevice::ReadRegister(uint32 reg, size_t size, uint32* buffer)
-{
- USBSmartLock USBSubsystemLock; // released on exit
-
- if (size > 255) {
- TRACE_ALWAYS("Read too big! size = %d\n", size);
- return B_BAD_VALUE;
- }
-
- size_t actualLength = 0;
- int retries = 0;
- status_t result = B_ERROR;
-
- do {
- result = gUSBModule->send_request(fDevice,
- 0xC0 | USB_REQTYPE_ENDPOINT_OUT, 0x02,
- (reg & 0xFFFF),
- ((reg >> 16) & 0xFFFF),
- size, buffer,
- &actualLength);
- retries++ ;
- if (-ENODEV == result) {
- TRACE_ALWAYS("Error: Device was removed during USB
read\n");
- break;
- }
-
- } while (result < 0 && retries < MAX_USB_IO_RETRIES);
-
- if (result < 0) {
- TRACE_ALWAYS("Error: USB read request failure."
- " Result: %d; Attempt: %d.\n", result, retries);
- return result;
- }
-
-
- if (size != actualLength) {
- TRACE_ALWAYS("Error: Size mismatch on USB read request."
- " Asked: %d; Got: %d; Attempt: %d.\n", size,
actualLength, retries);
- }
-
- return result;
-}
-
-
-status_t
-BeceemDevice::WriteRegister(uint32 reg, size_t size, uint32* buffer)
-{
- USBSmartLock USBSubsystemLock; // released on exit
-
- if (size > 255) {
- TRACE_ALWAYS("Write too big! size = %d\n", size);
- return B_BAD_VALUE;
- }
-
- size_t actualLength = 0;
- int retries = 0;
- status_t result;
-
- do {
- result = gUSBModule->send_request(fDevice,
- 0x40 | USB_REQTYPE_ENDPOINT_OUT, 0x01,
- (reg & 0xFFFF),
- ((reg >> 16) & 0xFFFF),
- size, buffer,
- &actualLength);
- retries++ ;
- if (-ENODEV == result) {
- TRACE_ALWAYS("Error: Device was removed during USB
write\n");
- break;
- }
-
- } while (result < 0 && retries < MAX_USB_IO_RETRIES);
-
- if (result < 0) {
- TRACE_ALWAYS("Error: USB write request failure."
- " Result: %d; Attempt: %d.\n",
- result, retries);
-
- return result;
- }
-
- if (size != actualLength) {
- TRACE_ALWAYS("Error: Size mismatch on USB write request."
- " Provided: %d; Took: %d; Attempt: %d.\n",
- size, actualLength, retries);
- }
-
- return result;
-}
-
-
-status_t
-BeceemDevice::BizarroReadRegister(uint32 reg, size_t size,
- uint32* buffer)
-{
- // NET_TO_HOST long
-
- // Read then flip
- status_t status = ReadRegister(reg, size, buffer);
-
- convertEndian(false, size, buffer);
-
- return status;
-}
-
-
-status_t
-BeceemDevice::BizarroWriteRegister(uint32 reg, size_t size,
- uint32* buffer)
-{
- // HOST_TO_NET long
-
- volatile uint32 reload = *buffer;
-
- convertEndian(true, size, buffer);
-
- status_t status = WriteRegister(reg, size, buffer);
- // Flip then write
-
- // as we modified the input data, and other things
- // outside this function may need it, restore the original val.
- *buffer = reload;
-
- return status;
-}
-
-
-BeceemDevice::BeceemDevice(usb_device device, const char *description)
- :
- fStatus(B_ERROR),
- fOpen(false),
- fInsideNotify(0),
- fDevice(device),
- fDescription(description),
- fNonBlocking(false),
- fNotifyEndpoint(0),
- fReadEndpoint(0),
- fWriteEndpoint(0),
- fNotifyReadSem(-1),
- fNotifyWriteSem(-1),
- fNotifyBuffer(NULL),
- fNotifyBufferLength(0),
- fLinkStateChangeSem(-1),
- fHasConnection(false)
-{
- const usb_device_descriptor
- *deviceDescriptor = gUSBModule->get_device_descriptor(device);
-
- if (deviceDescriptor == NULL) {
- TRACE_ALWAYS("Error of getting USB device descriptor.\n");
- return;
- }
-
- fVendorID = deviceDescriptor->vendor_id;
- fProductID = deviceDescriptor->product_id;
-
- fNotifyReadSem = create_sem(0, DRIVER_NAME"_notify_read");
- if (fNotifyReadSem < B_OK) {
- TRACE_ALWAYS("Error of creating read notify semaphore:%#010x\n",
- fNotifyReadSem);
- return;
- }
-
- fNotifyWriteSem = create_sem(0, DRIVER_NAME"_notify_write");
- if (fNotifyWriteSem < B_OK) {
- TRACE_ALWAYS("Error of creating write notify
semaphore:%#010x\n",
- fNotifyWriteSem);
- return;
- }
-
- mutex_init(&gUSBLock, DRIVER_NAME"_usbsubsys");
-
- // TODO : Investigate possible Notify Buffer sizes
- fNotifyBufferLength = 8;
- fNotifyBuffer = (uint8*)malloc(fNotifyBufferLength);
- if (fNotifyBuffer == NULL) {
- TRACE_ALWAYS("Error allocating notify buffer\n");
- return;
- }
-
- if ((pwmxdevice = (WIMAX_DEVICE*)malloc(sizeof(WIMAX_DEVICE))) == NULL)
- TRACE_ALWAYS("Error allocating Wimax device configuration
buffer\n");
-
- if ((pwmxdevice->nvmFlashCSInfo
- = (PFLASH_CS_INFO)malloc(sizeof(FLASH_CS_INFO))) ==
NULL)
- TRACE_ALWAYS("Error allocating Flash CS info structure.\n");
-
- // set initial states
- pwmxdevice->LEDThreadID = 0;
- pwmxdevice->driverDDRinit = false;
- pwmxdevice->driverHalt = false;
- pwmxdevice->driverFwPushed = false;
-
- if (_SetupEndpoints() != B_OK) {
- return;
- }
-
- fStatus = B_OK;
-}
-
-
-BeceemDevice::~BeceemDevice()
-{
- pwmxdevice->driverHalt = true;
-
- snooze(500);
-
- // Terminate LED thread cleanly
- if (pwmxdevice->LEDThreadID > 0) {
- LEDThreadTerminate();
- // Turn lights out
- LightsOut();
- }
-
- gUSBModule->cancel_queued_transfers(fNotifyEndpoint);
- gUSBModule->cancel_queued_transfers(fReadEndpoint);
- gUSBModule->cancel_queued_transfers(fWriteEndpoint);
-
- if (fNotifyReadSem >= B_OK)
- delete_sem(fNotifyReadSem);
- if (fNotifyWriteSem >= B_OK)
- delete_sem(fNotifyWriteSem);
-
- free(fNotifyBuffer);
- // Free notification buffer
- free(pwmxdevice->nvmFlashCSInfo);
- // Free flash configuration structure
- free(pwmxdevice);
- // Free malloc of wimax device struct
-
- mutex_destroy(&gUSBLock);
-
- TRACE("Debug: BeceemDevice deconstruction complete\n");
-}
-
-
-status_t
-BeceemDevice::Open(uint32 flags)
-{
- if (fOpen)
- return B_BUSY;
- if (pwmxdevice->driverHalt)
- return B_ERROR;
-
- status_t result = StartDevice();
- if (result != B_OK)
- return result;
-
- // setup state notifications
- result = gUSBModule->queue_interrupt(fNotifyEndpoint, fNotifyBuffer,
- fNotifyBufferLength, _NotifyCallback, this);
- if (result != B_OK) {
- TRACE_ALWAYS("Error of requesting notify interrupt:%#010x\n",
result);
- return result;
- }
-
- fNonBlocking = (flags & O_NONBLOCK) == O_NONBLOCK;
- fOpen = true;
- return result;
-}
-
-
-status_t
-BeceemDevice::Close()
-{
- if (pwmxdevice->driverHalt) {
- fOpen = false;
- return B_OK;
- }
-
- // wait until possible notification handling finished...
- while (atomic_add(&fInsideNotify, 0) != 0)
- snooze(100);
-
- gUSBModule->cancel_queued_transfers(fNotifyEndpoint);
- gUSBModule->cancel_queued_transfers(fReadEndpoint);
- gUSBModule->cancel_queued_transfers(fWriteEndpoint);
-
- fOpen = false;
-
- return StopDevice();
-}
-
-
-status_t
-BeceemDevice::Free()
-{
- return B_OK;
-}
-
-
-// Network device Rx
-status_t
-BeceemDevice::Read(uint8 *buffer, size_t *numBytes)
-{
- size_t numBytesToRead = *numBytes;
- *numBytes = 0;
-
- TRACE_FLOW("Request %d bytes.\n", numBytesToRead);
-
- if (pwmxdevice->driverHalt) {
- TRACE_ALWAYS("Error receiving %d bytes from removed device.\n",
- numBytesToRead);
- return B_DEVICE_NOT_FOUND;
- }
-
- uint8 header[kRXHeaderSize];
- iovec rxData[] = {
- { &header, kRXHeaderSize },
- { buffer, numBytesToRead }
- };
-
- status_t result = gUSBModule->queue_bulk_v(fReadEndpoint,
- rxData, 1, _ReadCallback, this);
- if (result != B_OK) {
- TRACE_ALWAYS("Error of queue_bulk_v request:%#010x\n", result);
- return result;
- }
-
- uint32 flags = B_CAN_INTERRUPT | (fNonBlocking ? B_TIMEOUT : 0);
- result = acquire_sem_etc(fNotifyReadSem, 1, flags, 0);
- if (result < B_OK) {
- TRACE_ALWAYS("Error of acquiring notify semaphore:%#010x.\n",
result);
- return result;
- }
-
- // Safely tidy up after a major device hiccup
- if (fStatusRead != B_OK && fStatusRead != B_CANCELED
- && !pwmxdevice->driverHalt) {
- TRACE_ALWAYS("Error: Device status error:%#010x\n",
fStatusRead);
- result = gUSBModule->clear_feature(fReadEndpoint,
- USB_FEATURE_ENDPOINT_HALT);
- if (result != B_OK) {
- TRACE_ALWAYS("Error: Problem during clearing of HALT
state: "
- "%#010x.\n", result);
- return result;
- }
- }
-
- if (fActualLengthRead < kRXHeaderSize) {
- TRACE_ALWAYS("Error: no place for TRXHeader:only %d of %d
bytes.\n",
- fActualLengthRead, kRXHeaderSize);
- return B_ERROR; // TODO: ???
- }
-
- /*
- * TODO :see what the first byte holds ?
- if (!header.IsValid()) {
- TRACE_ALWAYS("Error:TRX Header is invalid: len:%#04x;
ilen:%#04x\n",
- header.fLength, header.fInvertedLength);
- return B_ERROR; // TODO: ???
- }
- */
-
- *numBytes = header[1] | (header[2] << 8);
-
- if ((header[0] & 0xBF) != 0) {
- TRACE_ALWAYS("RX error %d occured !\n", header[0]);
- }
-
- if (fActualLengthRead - kRXHeaderSize > *numBytes) {
- TRACE_ALWAYS("MISMATCH of the frame length: hdr %d;
received:%d\n",
- *numBytes, fActualLengthRead - kRXHeaderSize);
- }
-
- TRACE_FLOW("Read %d bytes.\n", *numBytes);
- return B_OK;
-}
-
-
-// Network device Tx
-status_t
-BeceemDevice::Write(const uint8 *buffer, size_t *numBytes)
-{
- size_t numBytesToWrite = *numBytes;
- *numBytes = 0;
-
- if (pwmxdevice->driverHalt) {
- TRACE_ALWAYS("Error writing %d bytes to removed device.\n",
- numBytesToWrite);
- return B_DEVICE_NOT_FOUND;
- }
-
- if (!fHasConnection) {
- TRACE_ALWAYS("Error writing %d bytes to device"
- " while WiMAX connection down.\n",
- numBytesToWrite);
- return B_ERROR;
- }
-
- if (fTXBufferFull) {
- TRACE_ALWAYS("Error writing %d bytes to device"
- " while TX buffer full.\n",
- numBytesToWrite);
- return B_ERROR;
- }
-
- TRACE_FLOW("Write %d bytes.\n", numBytesToWrite);
-
- uint8 header[kTXHeaderSize];
- header[0] = *numBytes & 0xFF;
- header[1] = *numBytes >> 8;
-
- iovec txData[] = {
- { &header, kTXHeaderSize },
- { (uint8*)buffer, numBytesToWrite }
- };
-
- status_t result = gUSBModule->queue_bulk_v(fWriteEndpoint,
- txData, 2, _WriteCallback, this);
- if (result != B_OK) {
- TRACE_ALWAYS("Error of queue_bulk_v request:%#010x\n", result);
- return result;
- }
-
- result = acquire_sem_etc(fNotifyWriteSem, 1, B_CAN_INTERRUPT, 0);
-
- if (result < B_OK) {
- TRACE_ALWAYS("Error of acquiring notify semaphore:%#010x.\n",
result);
- return result;
- }
-
- // Safely tidy up after a major device hiccup
- if (fStatusWrite != B_OK && fStatusWrite != B_CANCELED
- && !pwmxdevice->driverHalt) {
-
- TRACE_ALWAYS("Device status error:%#010x\n", fStatusWrite);
- result = gUSBModule->clear_feature(fWriteEndpoint,
- USB_FEATURE_ENDPOINT_HALT);
-
- if (result != B_OK) {
- TRACE_ALWAYS("Error during clearing of HALT state:"
- " %#010x\n", result);
- return result;
- }
- }
-
- *numBytes = fActualLengthWrite - kTXHeaderSize;;
-
- TRACE_FLOW("Written %d bytes.\n", *numBytes);
- return B_OK;
-}
-
-
-status_t
-BeceemDevice::Control(uint32 op, void *buffer, size_t length)
-{
- switch (op) {
- case ETHER_INIT:
- return B_OK;
-
- case ETHER_GETADDR:
- memcpy(buffer, &fMACAddress, sizeof(fMACAddress));
- return B_OK;
-
- case ETHER_GETFRAMESIZE:
- *(uint32 *)buffer = 1518 /* fFrameSize */;
- return B_OK;
-
- case ETHER_NONBLOCK:
- TRACE("ETHER_NONBLOCK\n");
- fNonBlocking = *((uint8*)buffer);
- return B_OK;
-
- case ETHER_SETPROMISC:
- TRACE("ETHER_SETPROMISC\n");
- return SetPromiscuousMode(*((uint8*)buffer));
-
- case ETHER_ADDMULTI:
- TRACE("ETHER_ADDMULTI\n");
- return ModifyMulticastTable(true, *((uint8*)buffer));
-
- case ETHER_REMMULTI:
- TRACE("ETHER_REMMULTI\n");
- return ModifyMulticastTable(false, *((uint8*)buffer));
-
-#if HAIKU_TARGET_PLATFORM_HAIKU
- case ETHER_SET_LINK_STATE_SEM:
- fLinkStateChangeSem = *(sem_id *)buffer;
- return B_OK;
-
- case ETHER_GET_LINK_STATE:
- return GetLinkState((ether_link_state *)buffer);
-#endif
-
- default:
- TRACE_ALWAYS("Error: Unhandled IOCTL catched:
%#010x\n", op);
- }
-
- return B_DEV_INVALID_IOCTL;
-}
-
-
-void
-BeceemDevice::Removed()
-{
- fHasConnection = false;
- pwmxdevice->driverHalt = true;
-
- TRACE("Debug: Pre InsideNotify\n");
-
- // the notify hook is different from the read and write hooks as it does
- // itself schedule traffic (while the other hooks only release a
semaphore
- // to notify another thread which in turn safly checks for the removed
- // case) - so we must ensure that we are not inside the notify hook
anymore
- // before returning, as we would otherwise violate the promise not to
use
- // any of the pipes after returning from the removed hook
- while (atomic_add(&fInsideNotify, 0) != 0)
- snooze(100);
-
- TRACE("Debug: Post InsideNotify\n");
-
- TRACE("Debug: Canceling queued USB transfers... [NotifyEndpoint]\n");
- gUSBModule->cancel_queued_transfers(fNotifyEndpoint);
- TRACE("Debug: Canceling queued USB transfers... [ReadEndpoint]\n");
- gUSBModule->cancel_queued_transfers(fReadEndpoint);
- TRACE("Debug: Canceling queued USB transfers... [WriteEndpoint]\n");
- gUSBModule->cancel_queued_transfers(fWriteEndpoint);
-
- if (fLinkStateChangeSem >= B_OK)
- release_sem_etc(fLinkStateChangeSem, 1, B_DO_NOT_RESCHEDULE);
-}
-
-
-/*! Identify Beceem Baseband chip and populate deviceChipID with it
- */
-status_t
-BeceemDevice::IdentifyChipset()
-{
-
- if (BizarroReadRegister(CHIP_ID_REG, sizeof(uint32),
- &pwmxdevice->deviceChipID) != B_OK)
- {
- TRACE_ALWAYS("Error: Beceem device identification read
failure\n");
- return B_ERROR;
- }
-
- switch(pwmxdevice->deviceChipID) {
- case T3:
- TRACE_ALWAYS(
- "Info: Identified Beceem T3 baseband chipset
(0x%x)\n",
- pwmxdevice->deviceChipID);
- break;
- case T3B:
- TRACE_ALWAYS(
- "Info: Identified Beceem T3B baseband chipset
(0x%x)\n",
- pwmxdevice->deviceChipID);
- break;
- case T3LPB:
- TRACE_ALWAYS(
- "Info: Identified Beceem T3LPB baseband chipset
(0x%x)\n",
- pwmxdevice->deviceChipID);
- break;
- case BCS250_BC:
- TRACE_ALWAYS(
- "Info: Identified Beceem BC250_BC baseband
chipset (0x%x)\n",
- pwmxdevice->deviceChipID);
- break;
- case BCS220_2:
- TRACE_ALWAYS(
- "Info: Identified Beceem BCS220_2 baseband
chipset (0x%x)\n",
- pwmxdevice->deviceChipID);
- break;
- case BCS220_2BC:
- TRACE_ALWAYS(
- "Info: Identified Beceem BCS220_2BC baseband
chipset (0x%x)\n",
- pwmxdevice->deviceChipID);
- break;
- case BCS220_3:
- TRACE_ALWAYS(
- "Info: Identified Beceem BCS220_3 baseband
chipset (0x%x)\n",
- pwmxdevice->deviceChipID);
- break;
- default:
- TRACE_ALWAYS(
- "Warning: Unknown Beceem chipset detected
(0x%x)\n",
- pwmxdevice->deviceChipID);
- break;
- }
-
- return B_OK;
-}
-
-
-status_t
-BeceemDevice::SetupDevice(bool deviceReplugged)
-{
- pwmxdevice->driverState = STATE_INIT;
-
- // ID the Beceem chipset
- IdentifyChipset();
-
- // init the CPU subsystem
- CPUInit(pwmxdevice);
-
- // Parse vendor config and put into struct
- if (LoadConfig() != B_OK)
- return B_ERROR;
-
- if (pwmxdevice->deviceChipID >= T3LPB) {
- uint32 value = 0;
- BizarroReadRegister(SYS_CFG, sizeof(value), &value);
- pwmxdevice->syscfgBefFw = value;
- if ((value & 0x60) == 0) {
- TRACE("Debug: CPU is FlashBoot\n");
- pwmxdevice->CPUFlashBoot = true;
- }
- }
-
- // take a quick break to let things settle
- snooze(100);
-
- CPUReset();
-
- // Initilize non-volatile memory
- if (NVMInit(pwmxdevice) != B_OK) {
- TRACE_ALWAYS("Error: Non-volatile memory initialization
failure.\n");
- return B_ERROR;
- }
-
- // Initilize device DDR memory
- if (DDRInit(pwmxdevice) != B_OK) {
- TRACE_ALWAYS("Error: DDR Initialization failed\n");
- return B_ERROR;
- } else {
- TRACE("Debug: DDR Initialization successful.\n");
- pwmxdevice->driverDDRinit = true;
- }
-
- // Push vendor configuration to device
- // Each bcm chip has a custom binary config
- // telling the device about itself (how it was designed)
- if (PushConfig(CONF_BEGIN_ADDR) != B_OK) {
- TRACE_ALWAYS("Vendor configuration push failed."
- " Aborting device setup.\n");
- return B_ERROR;
- }
-
- // Set up GPIO (nvmVer 5+ is double sized)
- if (pwmxdevice->nvmVerMajor < 5) {
- TRACE("Debug: VerMajor < 5 PARAM pointer\n");
- NVMRead(GPIO_PARAM_POINTER, 2,
- (uint32*)&pwmxdevice->hwParamPtr);
- pwmxdevice->hwParamPtr = ntohs(pwmxdevice->hwParamPtr);
- } else {
- TRACE("Debug: VerMajor 5+ PARAM pointer\n");
- NVMRead(GPIO_PARAM_POINTER_MAP5, 4,
- (uint32*)&pwmxdevice->hwParamPtr);
- // TODO : NVM : validate v5+ nvm params a-la
ValidateDSDParamsChecksum
- pwmxdevice->hwParamPtr = ntohl(pwmxdevice->hwParamPtr);
- }
-
- TRACE("Debug: Raw PARAM pointer: 0x%x\n", pwmxdevice->hwParamPtr);
-
- if (pwmxdevice->hwParamPtr < DSD_START_OFFSET
- || pwmxdevice->hwParamPtr > pwmxdevice->nvmDSDSize -
DSD_START_OFFSET) {
- TRACE_ALWAYS("Error: DSD Status checksum mismatch\n");
- return B_ERROR;
- }
-
- unsigned long dwReadValue = pwmxdevice->hwParamPtr;
- // hw paramater pointer
- dwReadValue = dwReadValue + DSD_START_OFFSET;
- // add DSD start offset
- dwReadValue = dwReadValue + GPIO_START_OFFSET;
- // add GPIO start offset
-
- NVMRead(dwReadValue, 32, (uint32*)&pwmxdevice->gpioInfo);
- // populate for LED information
-
- ValidateDSD(pwmxdevice->hwParamPtr);
- // validate the hardware DSD0 we calculated
-
- LEDInit(pwmxdevice);
- // Initilize LED on GPIO subsystem and spawn thread
-
- pwmxdevice->driverState = STATE_FWPUSH;
-
- status_t firm_push_result = PushFirmware(FIRM_BEGIN_ADDR);
- // Push firmware to device
-
- if (firm_push_result != B_OK) {
- TRACE_ALWAYS("Firmware push failed, aborting device setup.\n");
- pwmxdevice->driverFwPushed = false;
- return B_ERROR;
- } else {
- pwmxdevice->driverFwPushed = true;
- pwmxdevice->driverState = STATE_FWPUSH_OK;
- CPURun();
- }
-
- ether_address address;
-
- if (ReadMACFromNVM(&address) != B_OK)
- return B_ERROR;
-
- TRACE("MAC address is: %02x:%02x:%02x:%02x:%02x:%02x\n",
- address.ebyte[0], address.ebyte[1], address.ebyte[2],
- address.ebyte[3], address.ebyte[4], address.ebyte[5]);
-
- if (deviceReplugged) {
- // this might be the same device that was replugged - read the
- // mac address (which should be at the same index) to make sure
- if (memcmp(&address, &fMACAddress, sizeof(address)) != 0) {
- TRACE_ALWAYS("Cannot replace device with MAC address:"
- "%02x:%02x:%02x:%02x:%02x:%02x\n",
- fMACAddress.ebyte[0], fMACAddress.ebyte[1],
- fMACAddress.ebyte[2], fMACAddress.ebyte[3],
- fMACAddress.ebyte[4], fMACAddress.ebyte[5]);
- return B_BAD_VALUE; // is not the same
- }
- } else
- fMACAddress = address;
-
- pwmxdevice->driverState = STATE_NONET;
-
- // TODO : init Urb a-la StartInterruptUrb
- // TODO : wait for StartInterruptUrb
- // TODO : register_control_device_interface
-
-
- // TODO : Preserve stability
- // Things will break past this point until the ethernet interface is
more
- // complete. Prevent completion of device initilization to preseve
system
- // and network stack stability.
-
- #if 1
- TRACE_ALWAYS("A Beceem WiMax device was attached, "
- "however the Beceem driver is incomplete.\n");
- return B_ERROR;
- #endif
-
- return B_OK;
-}
-
-
-status_t
-BeceemDevice::CompareAndReattach(usb_device device)
-{
- const usb_device_descriptor *deviceDescriptor
- = gUSBModule->get_device_descriptor(device);
-
- if (deviceDescriptor == NULL) {
- TRACE_ALWAYS("Error getting USB device descriptor.\n");
- return B_ERROR;
- }
-
- if (deviceDescriptor->vendor_id != fVendorID
- && deviceDescriptor->product_id != fProductID) {
- // this certainly isn't the same device
- return B_BAD_VALUE;
- }
-
- // this is the same device that was replugged - clear the removed state,
- // resetup the endpoints and transfers and open the device if it was
- // previously opened
- fDevice = device;
- pwmxdevice->driverHalt = false;
-
- status_t result = _SetupEndpoints();
- if (result != B_OK) {
- pwmxdevice->driverHalt = true;
- return result;
- }
-
- // we need to setup hardware on device replug
- result = SetupDevice(true);
- if (result != B_OK) {
- return result;
- }
-
- if (fOpen) {
- fOpen = false;
- result = Open(fNonBlocking ? O_NONBLOCK : 0);
- }
-
- return result;
-}
-
-
-status_t
-BeceemDevice::_SetupEndpoints()
-{
- const usb_configuration_info *config
- = gUSBModule->get_nth_configuration(fDevice, 0);
-
- if (config == NULL) {
- TRACE_ALWAYS("Error: Failed to get USB"
- " device configuration.\n");
- return B_ERROR;
- }
-
- if (config->interface_count <= 0) {
- TRACE_ALWAYS("Error: No interfaces found"
- " in USB device configuration\n");
- return B_ERROR;
- }
-
- usb_interface_info *interface = config->interface[0].active;
- if (interface == 0) {
- TRACE_ALWAYS("Error:invalid active interface in "
- "USB device configuration\n");
- return B_ERROR;
- }
-
- int notifyEndpoint = -1;
- int readEndpoint = -1;
- int writeEndpoint = -1;
-
- for (size_t ep = 0; ep < interface->endpoint_count; ep++) {
- usb_endpoint_descriptor *epd = interface->endpoint[ep].descr;
-
- if ((epd->attributes & USB_ENDPOINT_ATTR_MASK)
- == USB_ENDPOINT_ATTR_INTERRUPT) {
- // Interrupt endpoint
- notifyEndpoint = ep;
- } else if ((epd->attributes & USB_ENDPOINT_ATTR_MASK)
- == USB_ENDPOINT_ATTR_BULK) {
-
- // Bulk data endpoint
- if ((epd->endpoint_address & USB_ENDPOINT_ADDR_DIR_IN)
- == USB_ENDPOINT_ADDR_DIR_IN)
- readEndpoint = ep;
- else if ((epd->endpoint_address &
USB_ENDPOINT_ADDR_DIR_OUT)
- == USB_ENDPOINT_ADDR_DIR_OUT)
- writeEndpoint = ep;
- else
- TRACE_ALWAYS("Warning: BULK USB Endpoint"
- " %d (%#04x) is unknown.\n", ep,
epd->attributes);
- } else if ((epd->attributes & USB_ENDPOINT_ATTR_MASK)
- == USB_ENDPOINT_ATTR_ISOCHRONOUS) {
- // Isochronous endpoint
- // TODO : do we need the Isochronous USB endpoints?
- //
http://www.beyondlogic.org/usbnutshell/usb4.shtml#Isochronous
- } else {
- // Strange...
- TRACE_ALWAYS("Warning: USB Endpoint %d (%#04x) doesn't
match known "
- "attribute mask.\n", ep, epd->attributes);
- }
-
- }
-
- if (notifyEndpoint == -1 || readEndpoint == -1 || writeEndpoint == -1) {
- TRACE_ALWAYS("Error: not all USB endpoints were found: "
- "notify:%d; read:%d; write:%d\n",
- notifyEndpoint, readEndpoint, writeEndpoint);
- return B_ERROR;
- }
-
- TRACE("Debug: USB Endpoints configured: notify %d; read %d; write %d\n",
- notifyEndpoint, readEndpoint, writeEndpoint);
-
- gUSBModule->set_configuration(fDevice, config);
-
- fNotifyEndpoint = interface->endpoint[notifyEndpoint].handle;
- fReadEndpoint = interface->endpoint[readEndpoint].handle;
- fWriteEndpoint = interface->endpoint[writeEndpoint].handle;
-
- return B_OK;
-}
-
-
-status_t
-BeceemDevice::StopDevice()
-{
- TRACE_ALWAYS("Stop device not implemented\n");
- return B_ERROR;
-}
-
-
-status_t
-BeceemDevice::SetPromiscuousMode(bool on)
-{
- // TODO : SetPromiscuousMode
-
- return B_OK;
-}
-
-
-status_t
-BeceemDevice::ModifyMulticastTable(bool add, uint8 address)
-{
- // TODO : ModifyMulticastTable
- TRACE_ALWAYS("Call for (%d, %#02x) is not implemented\n", add, address);
- return B_OK;
-}
-
-
-void
-BeceemDevice::_ReadCallback(void *cookie, int32 status, void *data,
- uint32 actualLength)
-{
- TRACE_FLOW("ReadCB: %d bytes; status:%#010x\n", actualLength, status);
- BeceemDevice *device = (BeceemDevice *)cookie;
- device->fActualLengthRead = actualLength;
- device->fStatusRead = status;
- release_sem_etc(device->fNotifyReadSem, 1, B_DO_NOT_RESCHEDULE);
-}
-
-
-void
[ *** diff truncated: 3298 lines dropped *** ]
