hrev51562 adds 2 changesets to branch 'master'
old head: dcdad04383dd2a5ee386805667f5c767138d1130
new head: f6c47144a6ef88ae23bb64b983ed9824518104c8
overview:
http://cgit.haiku-os.org/haiku/log/?qt=range&q=f6c47144a6ef+%5Edcdad04383dd
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dc9cdc37d07d: dtb/rpi2: Correct UART base frequency.
* https://github.com/raspberrypi/firmware/issues/643
* Mimics what the RaspberryPi guys adjusted it to in
the firmware.
* Solves corrupted UART serial on the RaspberryPi 2
* I think linux live-probes this frequency via dt-bindings.
f6c47144a6ef: kernel/uart: Refinements to irq and FIFO management
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
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2 files changed, 9 insertions(+), 4 deletions(-)
src/data/dts/arch/arm/bcm2836.dtsi | 2 +-
src/system/kernel/arch/arm/arch_uart_pl011.cpp | 11 ++++++++---
############################################################################
Commit: dc9cdc37d07d5e08d102e34be643954a114bf99f
URL: http://cgit.haiku-os.org/haiku/commit/?id=dc9cdc37d07d
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Sat Nov 18 19:19:26 2017 UTC
dtb/rpi2: Correct UART base frequency.
* https://github.com/raspberrypi/firmware/issues/643
* Mimics what the RaspberryPi guys adjusted it to in
the firmware.
* Solves corrupted UART serial on the RaspberryPi 2
* I think linux live-probes this frequency via dt-bindings.
----------------------------------------------------------------------------
diff --git a/src/data/dts/arch/arm/bcm2836.dtsi
b/src/data/dts/arch/arm/bcm2836.dtsi
index d777437..3c996b1 100644
--- a/src/data/dts/arch/arm/bcm2836.dtsi
+++ b/src/data/dts/arch/arm/bcm2836.dtsi
@@ -471,7 +471,7 @@
interrupts = <65>;
interrupt-parent = <&intc>;
- clock-frequency = <3000000>; /* Set by VideoCore */
+ clock-frequency = <48000000>; /* Set by VideoCore */
reg-shift = <2>;
};
############################################################################
Revision: hrev51562
Commit: f6c47144a6ef88ae23bb64b983ed9824518104c8
URL: http://cgit.haiku-os.org/haiku/commit/?id=f6c47144a6ef
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Sat Nov 18 19:20:25 2017 UTC
kernel/uart: Refinements to irq and FIFO management
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diff --git a/src/system/kernel/arch/arm/arch_uart_pl011.cpp
b/src/system/kernel/arch/arm/arch_uart_pl011.cpp
index 5bcec42..b95ed0d 100644
--- a/src/system/kernel/arch/arm/arch_uart_pl011.cpp
+++ b/src/system/kernel/arch/arm/arch_uart_pl011.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright 2011-2012 Haiku, Inc. All rights reserved.
+ * Copyright 2011-2017 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
@@ -115,6 +115,7 @@
#define PL011_DCDMIM (1 << 2) // DCD interrupt mask
#define PL011_CTSMIM (1 << 1) // CTS interrupt mask
#define PL011_RIMIM (1 << 0) // RI interrupt mask
+#define PL011_MSKIM 0x7ff // Mask all interrupts
#define PL011_OEIS (1 << 10) // overrun error interrupt state
#define PL011_BEIS (1 << 9) // break error interrupt state
@@ -179,7 +180,7 @@ ArchUARTPL011::ArchUARTPL011(addr_t base, int64 clock)
| PL011_PEIS | PL011_FEIS);
// ** Disable interrupts
- Out32(PL011_IMSC, 0);
+ Out32(PL011_IMSC, In32(PL011_IMSC) & ~PL011_MSKIM);
}
@@ -226,7 +227,11 @@ ArchUARTPL011::InitPort(uint32 baud)
Out32(PL011_FBRD, baudFractional);
// Set LCR 8n1, enable fifo
- Out32(PL011_LCRH, PL01x_LCRH_WLEN_8 | PL01x_LCRH_FEN);
+ Out32(PL011_LCRH, (In32(PL011_LCRH) & ~0xff)
+ | PL01x_LCRH_WLEN_8 | PL01x_LCRH_FEN);
+
+ // Set FIFO levels
+ Out32(PL011_IFLS, PL011_IFLS_RX4_8 | PL011_IFLS_TX4_8);
// Enable UART
Enable();
