hrev51450 adds 1 changeset to branch 'master'
old head: db68ff23c6506fa5b0871c594c46043342de3fae
new head: 9d8a58ea462729f2578a8f96f6a6b554869b2397
overview:
http://cgit.haiku-os.org/haiku/log/?qt=range&q=9d8a58ea4627+%5Edb68ff23c650
----------------------------------------------------------------------------
9d8a58ea4627: nvidia_gpgpu: Remove from tree.
Was nothing but a slightly-stripped version of the nvidia driver,
not touched substantially in nearly 10 years, and the cards it was
originally going to support (but never got anywhere near so) have long since
been deprecated.
[ Augustin Cavalier <waddlesplash@xxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev51450
Commit: 9d8a58ea462729f2578a8f96f6a6b554869b2397
URL: http://cgit.haiku-os.org/haiku/commit/?id=9d8a58ea4627
Author: Augustin Cavalier <waddlesplash@xxxxxxxxx>
Date: Sun Oct 1 01:27:47 2017 UTC
----------------------------------------------------------------------------
38 files changed, 12998 deletions(-)
.../graphics/nvidia_gpgpu/DriverInterface.h | 369 ---
headers/private/graphics/nvidia_gpgpu/nv_acc.h | 51 -
.../private/graphics/nvidia_gpgpu/nv_macros.h | 912 ------
src/add-ons/accelerants/Jamfile | 1 -
.../accelerants/nvidia_gpgpu/Acceleration.c | 18 -
src/add-ons/accelerants/nvidia_gpgpu/Cursor.c | 194 --
.../accelerants/nvidia_gpgpu/EngineManagment.c | 73 -
.../accelerants/nvidia_gpgpu/GetAccelerantHook.c | 176 --
.../accelerants/nvidia_gpgpu/GetDeviceInfo.c | 25 -
.../accelerants/nvidia_gpgpu/GetModeInfo.c | 163 --
.../nvidia_gpgpu/GetTimingConstraints.c | 33 -
.../accelerants/nvidia_gpgpu/InitAccelerant.c | 348 ---
src/add-ons/accelerants/nvidia_gpgpu/Jamfile | 25 -
.../nvidia_gpgpu/ProposeDisplayMode.c | 546 ----
.../accelerants/nvidia_gpgpu/SetDisplayMode.c | 490 ----
src/add-ons/accelerants/nvidia_gpgpu/acc_std.h | 17 -
.../accelerants/nvidia_gpgpu/be_driver_proto.h | 72 -
.../accelerants/nvidia_gpgpu/engine/Jamfile | 19 -
.../accelerants/nvidia_gpgpu/engine/nv_acc_dma.c | 1297 ---------
.../accelerants/nvidia_gpgpu/engine/nv_crtc.c | 826 ------
.../accelerants/nvidia_gpgpu/engine/nv_crtc2.c | 825 ------
.../accelerants/nvidia_gpgpu/engine/nv_dac.c | 527 ----
.../accelerants/nvidia_gpgpu/engine/nv_dac2.c | 384 ---
.../accelerants/nvidia_gpgpu/engine/nv_general.c | 901 ------
.../accelerants/nvidia_gpgpu/engine/nv_globals.c | 36 -
.../accelerants/nvidia_gpgpu/engine/nv_globals.h | 69 -
.../accelerants/nvidia_gpgpu/engine/nv_i2c.c | 344 ---
.../accelerants/nvidia_gpgpu/engine/nv_info.c | 2692 ------------------
.../accelerants/nvidia_gpgpu/engine/nv_proto.h | 116 -
.../accelerants/nvidia_gpgpu/engine/nv_std.h | 10 -
.../accelerants/nvidia_gpgpu/engine/nv_support.c | 38 -
.../accelerants/nvidia_gpgpu/valid_mode_list | 34 -
src/add-ons/kernel/drivers/graphics/Jamfile | 1 -
.../kernel/drivers/graphics/nvidia_gpgpu/Jamfile | 10 -
.../drivers/graphics/nvidia_gpgpu/README.html | 33 -
.../drivers/graphics/nvidia_gpgpu/UPDATE.html | 20 -
.../drivers/graphics/nvidia_gpgpu/driver.c | 1237 --------
.../graphics/nvidia_gpgpu/nvidia_gpgpu.settings | 66 -
----------------------------------------------------------------------------
diff --git a/headers/private/graphics/nvidia_gpgpu/DriverInterface.h
b/headers/private/graphics/nvidia_gpgpu/DriverInterface.h
deleted file mode 100644
index 33c21f3..0000000
--- a/headers/private/graphics/nvidia_gpgpu/DriverInterface.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- Copyright 1999, Be Incorporated. All Rights Reserved.
- This file may be used under the terms of the Be Sample Code License.
-
- Other authors:
- Mark Watson;
- Apsed;
- Rudolf Cornelissen 10/2002-6/2008.
-*/
-
-#ifndef DRIVERINTERFACE_H
-#define DRIVERINTERFACE_H
-
-#include <Accelerant.h>
-#include "video_overlay.h"
-#include <Drivers.h>
-#include <PCI.h>
-#include <OS.h>
-
-#define DRIVER_PREFIX "nvidia_gpgpu"
-#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x"
-
-/*
- Internal driver state (also for sharing info between driver and
accelerant)
-*/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-typedef struct {
- sem_id sem;
- int32 ben;
-} benaphore;
-
-#define INIT_BEN(x) x.sem = create_sem(0, "NV_GPGPU "#x"
benaphore"); x.ben = 0;
-#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
-#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
-#define DELETE_BEN(x) delete_sem(x.sem);
-
-
-#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */
-
-/* dualhead extensions to flags */
-#define DUALHEAD_OFF (0<<6)
-#define DUALHEAD_CLONE (1<<6)
-#define DUALHEAD_ON (2<<6)
-#define DUALHEAD_SWITCH (3<<6)
-#define DUALHEAD_BITS (3<<6)
-#define DUALHEAD_CAPABLE (1<<8)
-#define TV_BITS (3<<9)
-#define TV_MON (0<<9
-#define TV_PAL (1<<9)
-#define TV_NTSC (2<<9)
-#define TV_CAPABLE (1<<11)
-#define TV_VIDEO (1<<12)
-#define TV_PRIMARY (1<<13)
-
-#define SKD_MOVE_CURSOR 0x00000001
-#define SKD_PROGRAM_CLUT 0x00000002
-#define SKD_SET_START_ADDR 0x00000004
-#define SKD_SET_CURSOR 0x00000008
-#define SKD_HANDLER_INSTALLED 0x80000000
-
-enum {
- NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
- NV_GET_PCI,
- NV_SET_PCI,
- NV_DEVICE_NAME,
- NV_RUN_INTERRUPTS,
- NV_ISA_OUT,
- NV_ISA_IN
-};
-
-/* card_type in order of date of NV chip design */
-enum {
- NV40 = 0,
- NV41,
- NV43,
- NV44,
- NV45,
- G70,
- G71,
- G72,
- G73,
- G80,
- G84,
- G86
-};
-
-/* card_arch in order of date of NV chip design */
-enum {
- NV40A = 0,
- NV50A
-};
-
-/* handles to pre-defined engine commands */
-#define NV_ROP5_SOLID 0x00000000 /* 2D */
-#define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */
-#define NV_IMAGE_PATTERN 0x00000002 /* 2D */
-#define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */
-#define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */
//2007
-#define NV4_SURFACE 0x00000010 /*
2D */
-#define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */
-#define NV_IMAGE_BLIT 0x00000011 /* 2D */
-#define NV12_IMAGE_BLIT 0x00000011 /*
2D */
-/* fixme:
- * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration:
- * There's a hardware fault in the input->output colorspace conversion here.
- * Besides, in NV40 and up this command nolonger exists. Both 'facts' are
confirmed
- * by testing.
- */
-//#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */
-#define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */
-#define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */
-
-//-----------------------------------------------------------------------------------
-/* safety byte-offset from end of cardRAM for preventing acceleration engine
crashes
- * caused by the existance of DMA engine command buffers in cardRAM and/or fifo
- * channel engine command re-assigning on-the-fly */
-
-/* NV40 and higher notes:
- * - we need at least 416kB distance from the DMA command buffer:
- * If you get too close to the DMA command buffer on NV40 and NV43 at least
(both
- * confirmed), the source DMA instance will mess-up for at least engine
command
- * NV_IMAGE_BLIT and NV12_IMAGE_BLIT;
- * - we need at least ???kB distance from the end of RAM for fifo-reassigning
'bug'
- * (fixme: unknown yet because fifo assignment switching isn't used here
atm);
- * - keep extra failsafe room to prevent malfunctioning apps from crashing
engine. */
-#define NV40_PLUS_OFFSET 512 * 1024
-
-/* fifo re-assigning bug definition:
- * if the fifo assignment is changed while at the same time card memory in the
- * dangerous region is being accessed by some application, the engine will
crash.
- * This bug applies for both PIO and DMA mode acceleration! */
-
-/* source-DMA instance bug definition:
- * if card memory in the dangerous region is being accessed by some
application while
- * a DMA command buffer exists in the same memory (though in a different
place),
- * the engine will crash. */
-//-----------------------------------------------------------------------------------
-
-/* internal used info on overlay buffers */
-typedef struct {
- uint16 slopspace;
- uint32 size;
-} int_buf_info;
-
-typedef struct { // apsed, see comments in nv.settings
- // for driver
- char accelerant[B_FILE_NAME_LENGTH];
- char primary[B_FILE_NAME_LENGTH];
- bool dumprom;
- // for accelerant
- uint32 logmask;
- uint32 memory;
- bool usebios;
- bool hardcursor;
- bool switchhead;
- bool pgm_panel;
- bool force_sync;
- bool force_ws;
- uint32 gpu_clk;
- uint32 ram_clk;
-} nv_settings;
-
-/* shared info */
-typedef struct {
- /* a few ID things */
- uint16 vendor_id; /* PCI vendor ID, from pci_info */
- uint16 device_id; /* PCI device ID, from pci_info */
- uint8 revision; /* PCI device revsion, from pci_info */
- uint8 bus; /* PCI bus number, from pci_info */
- uint8 device; /* PCI device number on bus, from pci_info */
- uint8 function; /* PCI function number in device, from pci_info
*/
-
- /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */
- bool accelerant_in_use;
-
- /* bug workaround for 4.5.0 */
- uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory
does not work*/
- uint32 * clone_bugfix_regs;
-
- /*memory mappings*/
- area_id regs_area; /* Kernel's area_id for the memory mapped
registers.
- It will be cloned into
the accelerant's address
- space. */
-
- area_id fb_area; /* Frame buffer's area_id. The addresses are
shared with all teams. */
- area_id unaligned_dma_area; /* Area assigned for DMA. It will be
(partially) mapped to an
- aligned
area using MTRR-WC. */
- area_id dma_area; /* Aligned area assigned for DMA. The addresses
are shared with all teams. */
-
- void *framebuffer; /* As viewed from virtual memory */
- void *framebuffer_pci; /* As viewed from the PCI bus (for DMA)
*/
- void *dma_buffer; /* As viewed from virtual memory */
- void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA)
*/
-
- /*screenmode list*/
- area_id mode_area; /* Contains the list of display modes
the driver supports */
- uint32 mode_count; /* Number of display modes in the list
*/
-
- /*flags - used by driver*/
- uint32 flags;
-
- /*vblank semaphore*/
- sem_id vblank; /* The vertical blank semaphore.
Ownership will be
- transfered to the team opening
the device first */
- /*cursor information*/
- struct {
- uint16 hot_x; /* Cursor hot spot. The top left corner
of the cursor */
- uint16 hot_y; /* is 0,0 */
- uint16 x; /* The location of the cursor hot spot
on the */
- uint16 y; /* desktop */
- uint16 width; /* Width and height of the cursor shape
(always 16!) */
- uint16 height;
- bool is_visible; /* Is the cursor currently displayed? */
- bool dh_right; /* Is cursor on right side of stretched
screen? */
- } cursor;
-
- /*colour lookup table*/
- uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC
*/
-
- /*more display mode stuff*/
- display_mode dm; /* current display mode configuration:
head1 */
- uint32 dpms_flags; /* current DPMS mode */
- bool acc_mode; /* signals (non)accelerated mode */
- bool crtc_switch_mode; /* signals dualhead switch mode if panels are
used */
-
- /*frame buffer config - for BDirectScreen*/
- frame_buffer_config fbc; /* bytes_per_row and start of frame
buffer: head1 */
- accelerant_device_info adi; /* as returned by hook
GET_ACCELERANT_DEVICE_INFO */
-
- /*acceleration engine*/
- struct {
- uint32 count; /* last dwgsync slot used */
- uint32 last_idle; /* last dwgsync slot we *know*
the engine was idle after */
- benaphore lock; /* for serializing access to
the acc engine */
- struct {
- uint32 handle[0x08]; /* FIFO channel's cmd handle
for the owning cmd */
- uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's
assigned FIFO ch (if any) */
- } fifo;
- struct {
- uint32 put; /* last 32-bit-word
adress given to engine to exec. to */
- uint32 current; /* first free 32-bit-word
adress in buffer */
- uint32 free; /* nr. of useable free 32-bit
words remaining in buffer */
- uint32 max; /* command buffer's
useable size in 32-bit words */
- } dma;
- struct {
- uint32 clones; /* clone 'number' (mask, slot)
(one bit per clone) */
- uint32 reload; /* reload state and surfaces
(one bit per clone) */
- uint32 newmode; /* re-allocate all buffers (one
bit per clone) */
- //fixme: memory stuff needs to be expanded (shared
texture allocation?)
- uint32 mem_low; /* ptr to first free mem
adress: cardmem local offset */
- uint32 mem_high; /* ptr to last free mem adress:
cardmem local offset */
- bool mode_changing; /* a mode-change is in progress
(set/clear by 2D drv) */
- } threeD;
- } engine;
-
- struct
- {
- /* specialised registers for card initialisation read from NV
BIOS (pins) */
-
- /* general card information */
- uint32 card_type; /* see card_type enum above */
- uint32 card_arch; /* see card_arch enum above */
- bool laptop; /* mobile chipset or not
('internal' flatpanel!) */
- bool slaved_tmds1; /* external TMDS
encoder active on CRTC1 */
- bool slaved_tmds2; /* external TMDS
encoder active on CRTC2 */
- bool master_tmds1; /* on die TMDS encoder
active on CRTC1 */
- bool master_tmds2; /* on die TMDS encoder
active on CRTC2 */
- bool tmds1_active; /* found panel on CRTC1
that is active */
- bool tmds2_active; /* found panel on CRTC2
that is active */
- display_timing p1_timing; /* 'modeline' fetched for panel
1 */
- display_timing p2_timing; /* 'modeline' fetched for panel
2 */
- float panel1_aspect; /* panel's aspect ratio */
- float panel2_aspect; /* panel's aspect ratio */
- bool crtc2_prim; /* using CRTC2 as
primary CRTC */
- bool i2c_bus0; /* we have a wired I2C
bus 0 on board */
- bool i2c_bus1; /* we have a wired I2C
bus 1 on board */
- bool i2c_bus2; /* we have a wired I2C
bus 2 on board */
- bool i2c_bus3; /* we have a wired I2C
bus 3 on board */
- uint8 monitors; /* output devices
connection matrix */
- bool int_assigned; /* card has a useable
INT assigned to it */
- status_t pins_status; /* B_OK if read correctly,
B_ERROR if faked */
-
- /* PINS */
- float f_ref; /* PLL
reference-oscillator frequency (Mhz) */
- bool ext_pll; /* the extended PLL
contains more dividers */
- uint32 max_system_vco; /* graphics engine PLL VCO
limits (Mhz) */
- uint32 min_system_vco;
- uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */
- uint32 min_pixel_vco;
- uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */
- uint32 min_video_vco;
- uint32 std_engine_clock; /* graphics engine clock speed
needed (Mhz) */
- uint32 std_memory_clock; /* card memory clock speed
needed (Mhz) */
- uint32 max_dac1_clock; /* dac1 limits (Mhz) */
- uint32 max_dac1_clock_8; /* dac1 limits correlated to
RAMspeed limits (Mhz) */
- uint32 max_dac1_clock_16;
- uint32 max_dac1_clock_24;
- uint32 max_dac1_clock_32;
- uint32 max_dac1_clock_32dh;
- uint32 max_dac2_clock; /* dac2 limits (Mhz) */
- uint32 max_dac2_clock_8; /* dac2, maven limits
correlated to RAMspeed limits (Mhz) */
- uint32 max_dac2_clock_16;
- uint32 max_dac2_clock_24;
- uint32 max_dac2_clock_32;
- uint32 max_dac2_clock_32dh;
- bool secondary_head; /* presence of functions */
- bool primary_dvi;
- bool secondary_dvi;
- uint32 memory_size; /* memory (in bytes) */
- } ps;
-
- /* mirror of the ROM (copied in driver, because may not be mapped
permanently) */
- uint8 rom_mirror[65536];
-
- /* some configuration settings from
~/config/settings/kernel/drivers/nv.settings if exists */
- nv_settings settings;
-
-} shared_info;
-
-/* Read or write a value in PCI configuration space */
-typedef struct {
- uint32 magic; /* magic number to make sure the caller groks
us */
- uint32 offset; /* Offset to read/write */
- uint32 size; /* Number of bytes to transfer */
- uint32 value; /* The value read or written */
-} nv_get_set_pci;
-
-/* Enable or Disable CRTC (1,2) interrupts */
-typedef struct {
- uint32 magic; /* magic number to make sure the caller groks
us */
- bool crtc; /* adressed CRTC */
- bool do_it; /* state to set */
-} nv_set_vblank_int;
-
-/* Retrieve the area_id of the kernel/accelerant shared info */
-typedef struct {
- uint32 magic; /* magic number to make sure the caller groks
us */
- area_id shared_info_area; /* area_id containing the shared
information */
-} nv_get_private_data;
-
-/* Retrieve the device name. Usefull for when we have a file handle, but want
-to know the device name (like when we are cloning the accelerant) */
-typedef struct {
- uint32 magic; /* magic number to make sure the caller groks
us */
- char *name; /* The name of the device, less the /dev root */
-} nv_device_name;
-
-/* Read or write a value in ISA I/O space */
-typedef struct {
- uint32 magic; /* magic number to make sure the caller groks
us */
- uint16 adress; /* Offset to read/write */
- uint8 size; /* Number of bytes to transfer */
- uint16 data; /* The value read or written */
-} nv_in_out_isa;
-
-enum {
-
- _WAIT_FOR_VBLANK = (1 << 0)
-};
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif
diff --git a/headers/private/graphics/nvidia_gpgpu/nv_acc.h
b/headers/private/graphics/nvidia_gpgpu/nv_acc.h
deleted file mode 100644
index 7724b9f..0000000
--- a/headers/private/graphics/nvidia_gpgpu/nv_acc.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- definitions for used nVidia acceleration engine commands.
-
- Written by Rudolf Cornelissen 12/2004-6/2008
-*/
-
-#ifndef NV_ACC_H
-#define NV_ACC_H
-
-/************ DMA command defines ***********/
-
-/* FIFO channels */
-#define NV_GENERAL_FIFO_CH0 0x0000
-#define NV_GENERAL_FIFO_CH1 0x2000
-#define NV_GENERAL_FIFO_CH2 0x4000
-#define NV_GENERAL_FIFO_CH3 0x6000
-#define NV_GENERAL_FIFO_CH4 0x8000
-#define NV_GENERAL_FIFO_CH5 0xa000
-#define NV_GENERAL_FIFO_CH6 0xc000
-#define NV_GENERAL_FIFO_CH7 0xe000
-
-/* sub-command offsets within FIFO channels */
-#define NV_GENERAL_DMAPUT
0x0040
-#define NV_GENERAL_DMAGET
0x0044
-#define NV_ROP5_SOLID_SETROP5 0x0300
-#define NV_IMAGE_BLACK_RECTANGLE_TOPLEFT 0x0300
-#define NV_IMAGE_PATTERN_SETCOLORFORMAT 0x0300
-#define NV_IMAGE_PATTERN_SETSHAPE 0x0308
-#define NV_IMAGE_PATTERN_SETCOLOR0 0x0310
-#define NV_IMAGE_BLIT_SOURCEORG
0x0300
-//fixme note: non-DMA acc is still using NV3_GDI_RECTANGLE_TEXT...
-//which is just as fast as NV4_GDI_RECTANGLE_TEXT, but has a hardware fault
for DMA!
-#define NV4_GDI_RECTANGLE_TEXT_SETCOLORFORMAT 0x0300
-#define NV4_GDI_RECTANGLE_TEXT_COLOR1A 0x03fc
-#define NV4_GDI_RECTANGLE_TEXT_UCR0_LEFTTOP 0x0400
-#define NV4_SURFACE_FORMAT
0x0300
-#define NV_SCALED_IMAGE_FROM_MEMORY_SETCOLORFORMAT 0x0300
-#define NV_SCALED_IMAGE_FROM_MEMORY_SOURCEORG 0x0308
-#define NV_SCALED_IMAGE_FROM_MEMORY_SOURCESIZE 0x0400
-
-
-/************************
- * 3D specific commands *
- ************************/
-
-#define NV4_DX5_TEXTURE_TRIANGLE_COLORKEY 0x0300
-#define NV4_DX5_TEXTURE_TRIANGLE_TLVERTEX(i) 0x0400 + (i << 5)
-#define NV4_DX5_TEXTURE_TRIANGLE_TLVDRAWPRIM(i) 0x0600 + (i <<
2)
-#define NV4_CONTEXT_SURFACES_ARGB_ZS_PITCH 0x0308
-
-#endif
diff --git a/headers/private/graphics/nvidia_gpgpu/nv_macros.h
b/headers/private/graphics/nvidia_gpgpu/nv_macros.h
deleted file mode 100644
index 8e93afd..0000000
--- a/headers/private/graphics/nvidia_gpgpu/nv_macros.h
+++ /dev/null
@@ -1,912 +0,0 @@
-/* NV registers definitions and macros for access to them */
-
-/* PCI_config_space */
-#define NVCFG_DEVID 0x00
-#define NVCFG_DEVCTRL 0x04
-#define NVCFG_CLASS 0x08
-#define NVCFG_HEADER 0x0c
-#define NVCFG_BASE1REGS 0x10
-#define NVCFG_BASE2FB 0x14
-#define NVCFG_BASE3 0x18
-#define NVCFG_BASE4 0x1c //unknown if used
-#define NVCFG_BASE5 0x20 //unknown if used
-#define NVCFG_BASE6 0x24 //unknown if used
-#define NVCFG_BASE7 0x28 //unknown if used
-#define NVCFG_SUBSYSID1 0x2c
-#define NVCFG_ROMBASE 0x30
-#define NVCFG_CAPPTR 0x34
-#define NVCFG_CFG_1 0x38 //unknown if used
-#define NVCFG_INTERRUPT 0x3c
-#define NVCFG_SUBSYSID2 0x40
-#define NVCFG_AGPREF 0x44
-#define NVCFG_AGPSTAT 0x48
-#define NVCFG_AGPCMD 0x4c
-#define NVCFG_ROMSHADOW 0x50
-#define NVCFG_VGA 0x54
-#define NVCFG_SCHRATCH 0x58
-#define NVCFG_CFG_10 0x5c
-#define NVCFG_CFG_11 0x60
-#define NVCFG_CFG_12 0x64
-#define NVCFG_CFG_13 0x68 //unknown if used
-#define NVCFG_CFG_14 0x6c //unknown if used
-#define NVCFG_CFG_15 0x70 //unknown if used
-#define NVCFG_CFG_16 0x74 //unknown if used
-#define NVCFG_PCIEREF 0x78
-#define NVCFG_PCIEDCAP 0x7c
-#define NVCFG_PCIEDCTST 0x80
-#define NVCFG_PCIELCAP 0x84
-#define NVCFG_PCIELCTST 0x88
-#define NVCFG_CFG_22 0x8c //unknown if used
-#define NVCFG_CFG_23 0x90 //unknown if used
-#define NVCFG_CFG_24 0x94 //unknown if used
-#define NVCFG_CFG_25 0x98 //unknown if used
-#define NVCFG_CFG_26 0x9c //unknown if used
-#define NVCFG_CFG_27 0xa0 //unknown if used
-#define NVCFG_CFG_28 0xa4 //unknown if used
-#define NVCFG_CFG_29 0xa8 //unknown if used
-#define NVCFG_CFG_30 0xac //unknown if used
-#define NVCFG_CFG_31 0xb0 //unknown if used
-#define NVCFG_CFG_32 0xb4 //unknown if used
-#define NVCFG_CFG_33 0xb8 //unknown if used
-#define NVCFG_CFG_34 0xbc //unknown if used
-#define NVCFG_CFG_35 0xc0 //unknown if used
-#define NVCFG_CFG_36 0xc4 //unknown if used
-#define NVCFG_CFG_37 0xc8 //unknown if used
-#define NVCFG_CFG_38 0xcc //unknown if used
-#define NVCFG_CFG_39 0xd0 //unknown if used
-#define NVCFG_CFG_40 0xd4 //unknown if used
-#define NVCFG_CFG_41 0xd8 //unknown if used
-#define NVCFG_CFG_42 0xdc //unknown if used
-#define NVCFG_CFG_43 0xe0 //unknown if used
-#define NVCFG_CFG_44 0xe4 //unknown if used
-#define NVCFG_CFG_45 0xe8 //unknown if used
-#define NVCFG_CFG_46 0xec //unknown if used
-#define NVCFG_CFG_47 0xf0 //unknown if used
-#define NVCFG_CFG_48 0xf4 //unknown if used
-#define NVCFG_CFG_49 0xf8 //unknown if used
-#define NVCFG_CFG_50 0xfc //unknown if used
-
-/* used NV INT registers for vblank */
-#define NV32_MAIN_INTE 0x00000140
-#define NV32_CRTC_INTS 0x00600100
-#define NV32_CRTC_INTE 0x00600140
-#define NV32_CRTC2_INTS 0x00602100
-#define NV32_CRTC2_INTE 0x00602140
-
-/* NV ACCeleration registers */
-/* engine initialisation registers */
-#define NVACC_ABS_UCLP_XMIN 0x0040053c
-#define NVACC_ABS_UCLP_YMIN 0x00400540
-#define NVACC_ABS_UCLP_XMAX 0x00400544
-#define NVACC_ABS_UCLP_YMAX 0x00400548
-#define NVACC_BETA_AND_VAL 0x00400608
-#define NVACC_FORMATS 0x00400618
-#define NVACC_OFFSET0 0x00400640
-#define NVACC_OFFSET1 0x00400644
-#define NVACC_OFFSET2 0x00400648
-#define NVACC_OFFSET3 0x0040064c
-#define NVACC_OFFSET4 0x00400650
-#define NVACC_OFFSET5 0x00400654
-#define NVACC_BBASE0 0x00400658
-#define NVACC_BBASE1 0x0040065c
-#define NVACC_BBASE2 0x00400660
-#define NVACC_BBASE3 0x00400664
-#define NVACC_NV10_BBASE4 0x00400668
-#define NVACC_NV10_BBASE5 0x0040066c
-#define NVACC_PITCH0 0x00400670
-#define NVACC_PITCH1 0x00400674
-#define NVACC_PITCH2 0x00400678
-#define NVACC_PITCH3 0x0040067c
-#define NVACC_PITCH4 0x00400680
-#define NVACC_BLIMIT0 0x00400684
-#define NVACC_BLIMIT1 0x00400688
-#define NVACC_BLIMIT2 0x0040068c
-#define NVACC_BLIMIT3 0x00400690
-#define NVACC_NV10_BLIMIT4 0x00400694
-#define NVACC_NV10_BLIMIT5 0x00400698
-#define NVACC_BPIXEL 0x00400724
-#define NVACC_NV20_OFFSET0 0x00400820
-#define NVACC_NV20_OFFSET1 0x00400824
-#define NVACC_NV20_OFFSET2 0x00400828
-#define NVACC_NV20_OFFSET3 0x0040082c
-#define NVACC_STRD_FMT 0x00400830
-#define NVACC_NV20_PITCH0 0x00400850
-#define NVACC_NV20_PITCH1 0x00400854
-#define NVACC_NV20_PITCH2 0x00400858
-#define NVACC_NV20_PITCH3 0x0040085c
-#define NVACC_NV20_BLIMIT6 0x00400864
-#define NVACC_NV20_BLIMIT7 0x00400868
-#define NVACC_NV20_BLIMIT8 0x0040086c
-#define NVACC_NV20_BLIMIT9 0x00400870
-#define NVACC_NV25_WHAT1 0x00400890
-
-/* specials */
-#define NVACC_DEBUG0 0x00400080
-#define NVACC_DEBUG1 0x00400084
-#define NVACC_DEBUG2 0x00400088
-#define NVACC_DEBUG3 0x0040008c
-#define NVACC_NV10_DEBUG4 0x00400090
-#define NVACC_NV10_DEBUG5 0x00400094
-#define NVACC_NV20_WHAT5 0x00400098
-#define NVACC_NV20_WHAT1 0x0040009c
-#define NVACC_ACC_INTS 0x00400100
-#define NVACC_ACC_INTE 0x00400140
-#define NVACC_NV10_CTX_CTRL 0x00400144
-#define NVACC_NV4X_DMA_SRC 0x00400220
-#define NVACC_NV4X_WHAT1 0x0040032c
-#define NVACC_NV4X_WHAT2 0x00405000
-#define NVACC_NV25_WHAT0 0x00400610
-#define NVACC_STATUS 0x00400700
-#define NVACC_NV04_SURF_TYP 0x0040070c
-#define NVACC_NV10_SURF_TYP 0x00400710
-#define NVACC_NV04_ACC_STAT 0x00400710
-#define NVACC_NV10_ACC_STAT 0x00400714
-#define NVACC_FIFO_EN 0x00400720
-#define NVACC_RDI_INDEX 0x00400750
-#define NVACC_RDI_DATA 0x00400754
-#define NVACC_PAT_SHP 0x00400810
-#define NVACC_NV40P_WHAT0 0x00400820
-#define NVACC_NV40P_WHAT1 0x00400824
-#define NVACC_NV40P_WHAT2 0x00400828
-#define NVACC_NV40P_WHAT3 0x0040082c
-#define NVACC_NV40P_OFFSET0 0x00400840
-#define NVACC_NV40P_OFFSET1 0x00400844
-#define NVACC_NV44_WHAT2 0x00400860
-#define NVACC_NV44_WHAT3 0x00400864
-//fixme? (guessed)
-#define NVACC_NV40P_PITCH0 0x00400870
-#define NVACC_NV40P_PITCH1 0x00400874
-#define NVACC_NV20_WHAT2 0x00400880
-//end fixme.
-#define NVACC_NV40P_BLIMIT6 0x004008a0
-#define NVACC_NV40P_BLIMIT7 0x004008a4
-#define NVACC_NV20_WHAT0 0x00400900
-#define NVACC_NV41_WHAT0 0x00400d00
-#define NVACC_NV20_2_WHAT0 0x00406900
-#define NVACC_NV40_WHAT0 0x004009b0
-#define NVACC_NV40_WHAT1 0x004009b4
-#define NVACC_NV40_WHAT2 0x004009b8
-#define NVACC_NV40_WHAT3 0x004009bc
-#define NVACC_NV20_WHAT3 0x00400b80
-#define NVACC_NV20_WHAT4 0x00400b84
-#define NVACC_NV25_WHAT2 0x00400b88
-#define NVACC_WINCLIP_H_0 0x00400f00
-#define NVACC_WINCLIP_H_1 0x00400f04
-#define NVACC_WINCLIP_H_2 0x00400f08
-#define NVACC_WINCLIP_H_3 0x00400f0c
-#define NVACC_WINCLIP_H_4 0x00400f10
-#define NVACC_WINCLIP_H_5 0x00400f14
-#define NVACC_WINCLIP_H_6 0x00400f18
-#define NVACC_WINCLIP_H_7 0x00400f1c
-#define NVACC_WINCLIP_V_0 0x00400f20
-#define NVACC_WINCLIP_V_1 0x00400f24
-#define NVACC_WINCLIP_V_2 0x00400f28
-#define NVACC_WINCLIP_V_3 0x00400f2c
-#define NVACC_WINCLIP_V_4 0x00400f30
-#define NVACC_WINCLIP_V_5 0x00400f34
-#define NVACC_WINCLIP_V_6 0x00400f38
-#define NVACC_WINCLIP_V_7 0x00400f3c
-#define NVACC_NV10_XFMOD0 0x00400f40
-#define NVACC_NV10_XFMOD1 0x00400f44
-#define NVACC_GLOB_STAT_0 0x00400f48
-#define NVACC_GLOB_STAT_1 0x00400f4c
-#define NVACC_NV10_PIPEADR 0x00400f50
-#define NVACC_NV10_PIPEDAT 0x00400f54
-/* PGRAPH unknown registers */
-#define NVACC_PGWHAT_00 0x00400e00
-#define NVACC_PGWHAT_01 0x00400e04
-#define NVACC_PGWHAT_02 0x00400e08
-#define NVACC_PGWHAT_03 0x00400e0c
-#define NVACC_PGWHAT_04 0x00400e10
-#define NVACC_PGWHAT_05 0x00400e14
-#define NVACC_PGWHAT_06 0x00400e18
-#define NVACC_PGWHAT_07 0x00400e1c
-#define NVACC_PGWHAT_08 0x00400e20
-#define NVACC_PGWHAT_09 0x00400e24
-#define NVACC_PGWHAT_0A 0x00400e28
-#define NVACC_PGWHAT_0B 0x00400e2c
-#define NVACC_PGWHAT_0C 0x00400e30
-#define NVACC_PGWHAT_0D 0x00400e34
-#define NVACC_PGWHAT_0E 0x00400e38
-#define NVACC_PGWHAT_0F 0x00400e3c
-#define NVACC_PGWHAT_10 0x00400e40
-#define NVACC_PGWHAT_11 0x00400e44
-#define NVACC_PGWHAT_12 0x00400e48
-#define NVACC_PGWHAT_13 0x00400e4c
-#define NVACC_PGWHAT_14 0x00400e50
-#define NVACC_PGWHAT_15 0x00400e54
-#define NVACC_PGWHAT_16 0x00400e58
-#define NVACC_PGWHAT_17 0x00400e5c
-#define NVACC_PGWHAT_18 0x00400e60
-#define NVACC_PGWHAT_19 0x00400e64
-#define NVACC_PGWHAT_1A 0x00400e68
-#define NVACC_PGWHAT_1B 0x00400e6c
-#define NVACC_PGWHAT_1C 0x00400e70
-#define NVACC_PGWHAT_1D 0x00400e74
-#define NVACC_PGWHAT_1E 0x00400e78
-#define NVACC_PGWHAT_1F 0x00400e7c
-#define NVACC_PGWHAT_20 0x00400e80
-#define NVACC_PGWHAT_21 0x00400e84
-#define NVACC_PGWHAT_22 0x00400e88
-#define NVACC_PGWHAT_23 0x00400e8c
-#define NVACC_PGWHAT_24 0x00400e90
-#define NVACC_PGWHAT_25 0x00400e94
-#define NVACC_PGWHAT_26 0x00400e98
-#define NVACC_PGWHAT_27 0x00400e9c
-#define NVACC_PGWHAT_28 0x00400ea0
-#define NVACC_PGWHAT_29 0x00400ea4
-#define NVACC_PGWHAT_2A 0x00400ea8
-/* PGRAPH cache registers */
-#define NVACC_CACHE1_1 0x00400160
-#define NVACC_CACHE1_2 0x00400180
-#define NVACC_CACHE1_3 0x004001a0
-#define NVACC_CACHE1_4 0x004001c0
-#define NVACC_CACHE1_5 0x004001e0
-#define NVACC_CACHE2_1 0x00400164
-#define NVACC_CACHE2_2 0x00400184
-#define NVACC_CACHE2_3 0x004001a4
-#define NVACC_CACHE2_4 0x004001c4
-#define NVACC_CACHE2_5 0x004001e4
-#define NVACC_CACHE3_1 0x00400168
-#define NVACC_CACHE3_2 0x00400188
-#define NVACC_CACHE3_3 0x004001a8
-#define NVACC_CACHE3_4 0x004001c8
-#define NVACC_CACHE3_5 0x004001e8
-#define NVACC_CACHE4_1 0x0040016c
-#define NVACC_CACHE4_2 0x0040018c
-#define NVACC_CACHE4_3 0x004001ac
-#define NVACC_CACHE4_4 0x004001cc
-#define NVACC_CACHE4_5 0x004001ec
-#define NVACC_NV10_CACHE5_1 0x00400170
-#define NVACC_NV04_CTX_CTRL 0x00400170
-#define NVACC_CACHE5_2 0x00400190
-#define NVACC_CACHE5_3 0x004001b0
-#define NVACC_CACHE5_4 0x004001d0
-#define NVACC_CACHE5_5 0x004001f0
-#define NVACC_NV10_CACHE6_1 0x00400174
-#define NVACC_CACHE6_2 0x00400194
-#define NVACC_CACHE6_3 0x004001b4
-#define NVACC_CACHE6_4 0x004001d4
-#define NVACC_CACHE6_5 0x004001f4
-#define NVACC_NV10_CACHE7_1 0x00400178
-#define NVACC_CACHE7_2 0x00400198
-#define NVACC_CACHE7_3 0x004001b8
-#define NVACC_CACHE7_4 0x004001d8
-#define NVACC_CACHE7_5 0x004001f8
-#define NVACC_NV10_CACHE8_1 0x0040017c
-#define NVACC_CACHE8_2 0x0040019c
-#define NVACC_CACHE8_3 0x004001bc
-#define NVACC_CACHE8_4 0x004001dc
-#define NVACC_CACHE8_5 0x004001fc
-#define NVACC_NV10_CTX_SW1 0x0040014c
-#define NVACC_NV10_CTX_SW2 0x00400150
-#define NVACC_NV10_CTX_SW3 0x00400154
-#define NVACC_NV10_CTX_SW4 0x00400158
-#define NVACC_NV10_CTX_SW5 0x0040015c
-/* engine tile registers src */
-#define NVACC_NV10_FBTIL0AD 0x00100240
-#define NVACC_NV10_FBTIL0ED 0x00100244
-#define NVACC_NV10_FBTIL0PT 0x00100248
-#define NVACC_NV10_FBTIL0ST 0x0010024c
-#define NVACC_NV10_FBTIL1AD 0x00100250
-#define NVACC_NV10_FBTIL1ED 0x00100254
-#define NVACC_NV10_FBTIL1PT 0x00100258
-#define NVACC_NV10_FBTIL1ST 0x0010025c
-#define NVACC_NV10_FBTIL2AD 0x00100260
-#define NVACC_NV10_FBTIL2ED 0x00100264
-#define NVACC_NV10_FBTIL2PT 0x00100268
-#define NVACC_NV10_FBTIL2ST 0x0010026c
-#define NVACC_NV10_FBTIL3AD 0x00100270
-#define NVACC_NV10_FBTIL3ED 0x00100274
-#define NVACC_NV10_FBTIL3PT 0x00100278
-#define NVACC_NV10_FBTIL3ST 0x0010027c
-#define NVACC_NV10_FBTIL4AD 0x00100280
-#define NVACC_NV10_FBTIL4ED 0x00100284
-#define NVACC_NV10_FBTIL4PT 0x00100288
-#define NVACC_NV10_FBTIL4ST 0x0010028c
-#define NVACC_NV10_FBTIL5AD 0x00100290
-#define NVACC_NV10_FBTIL5ED 0x00100294
-#define NVACC_NV10_FBTIL5PT 0x00100298
-#define NVACC_NV10_FBTIL5ST 0x0010029c
-#define NVACC_NV10_FBTIL6AD 0x001002a0
-#define NVACC_NV10_FBTIL6ED 0x001002a4
-#define NVACC_NV10_FBTIL6PT 0x001002a8
-#define NVACC_NV10_FBTIL6ST 0x001002ac
-#define NVACC_NV10_FBTIL7AD 0x001002b0
-#define NVACC_NV10_FBTIL7ED 0x001002b4
-#define NVACC_NV10_FBTIL7PT 0x001002b8
-#define NVACC_NV10_FBTIL7ST 0x001002bc
-#define NVACC_NV41_FBTIL0AD 0x00100600
-#define NVACC_NV41_FBTIL0ED 0x00100604
-#define NVACC_NV41_FBTIL0PT 0x00100608
-#define NVACC_NV41_FBTIL0ST 0x0010060c
-#define NVACC_NV41_FBTIL1AD 0x00100610
-#define NVACC_NV41_FBTIL1ED 0x00100614
-#define NVACC_NV41_FBTIL1PT 0x00100618
-#define NVACC_NV41_FBTIL1ST 0x0010061c
-#define NVACC_NV41_FBTIL2AD 0x00100620
-#define NVACC_NV41_FBTIL2ED 0x00100624
-#define NVACC_NV41_FBTIL2PT 0x00100628
-#define NVACC_NV41_FBTIL2ST 0x0010062c
-#define NVACC_NV41_FBTIL3AD 0x00100630
-#define NVACC_NV41_FBTIL3ED 0x00100634
-#define NVACC_NV41_FBTIL3PT 0x00100638
-#define NVACC_NV41_FBTIL3ST 0x0010063c
-#define NVACC_NV41_FBTIL4AD 0x00100640
-#define NVACC_NV41_FBTIL4ED 0x00100644
-#define NVACC_NV41_FBTIL4PT 0x00100648
-#define NVACC_NV41_FBTIL4ST 0x0010064c
-#define NVACC_NV41_FBTIL5AD 0x00100650
-#define NVACC_NV41_FBTIL5ED 0x00100654
-#define NVACC_NV41_FBTIL5PT 0x00100658
-#define NVACC_NV41_FBTIL5ST 0x0010065c
-#define NVACC_NV41_FBTIL6AD 0x00100660
-#define NVACC_NV41_FBTIL6ED 0x00100664
-#define NVACC_NV41_FBTIL6PT 0x00100668
-#define NVACC_NV41_FBTIL6ST 0x0010066c
-#define NVACC_NV41_FBTIL7AD 0x00100670
-#define NVACC_NV41_FBTIL7ED 0x00100674
-#define NVACC_NV41_FBTIL7PT 0x00100678
-#define NVACC_NV41_FBTIL7ST 0x0010067c
-#define NVACC_NV41_FBTIL8AD 0x00100680
-#define NVACC_NV41_FBTIL8ED 0x00100684
-#define NVACC_NV41_FBTIL8PT 0x00100688
-#define NVACC_NV41_FBTIL8ST 0x0010068c
-#define NVACC_NV41_FBTIL9AD 0x00100690
-#define NVACC_NV41_FBTIL9ED 0x00100694
-#define NVACC_NV41_FBTIL9PT 0x00100698
-#define NVACC_NV41_FBTIL9ST 0x0010069c
-#define NVACC_NV41_FBTILAAD 0x001006a0
-#define NVACC_NV41_FBTILAED 0x001006a4
-#define NVACC_NV41_FBTILAPT 0x001006a8
-#define NVACC_NV41_FBTILAST 0x001006ac
-#define NVACC_NV41_FBTILBAD 0x001006b0
-#define NVACC_NV41_FBTILBED 0x001006b4
-#define NVACC_NV41_FBTILBPT 0x001006b8
-#define NVACC_NV41_FBTILBST 0x001006bc
-#define NVACC_G70_FBTILCAD 0x001006c0
-#define NVACC_G70_FBTILCED 0x001006c4
-#define NVACC_G70_FBTILCPT 0x001006c8
-#define NVACC_G70_FBTILCST 0x001006cc
-#define NVACC_G70_FBTILDAD 0x001006d0
-#define NVACC_G70_FBTILDED 0x001006d4
-#define NVACC_G70_FBTILDPT 0x001006d8
-#define NVACC_G70_FBTILDST 0x001006dc
-#define NVACC_G70_FBTILEAD 0x001006e0
-#define NVACC_G70_FBTILEED 0x001006e4
-#define NVACC_G70_FBTILEPT 0x001006e8
-#define NVACC_G70_FBTILEST 0x001006ec
-/* engine tile registers dst */
-#define NVACC_NV20_WHAT_T0 0x004009a4
-#define NVACC_NV20_WHAT_T1 0x004009a8
-#define NVACC_NV40_WHAT_T2 0x004069a4
-#define NVACC_NV40_WHAT_T3 0x004069a8
-#define NVACC_NV40P_WHAT_T0 0x004009f0
-#define NVACC_NV40P_WHAT_T1 0x004009f4
-#define NVACC_G70_WHAT_T0 0x00400df0
-#define NVACC_G70_WHAT_T1 0x00400df4
-#define NVACC_NV40P_WHAT_T2 0x004069f0
-#define NVACC_NV40P_WHAT_T3 0x004069f4
-#define NVACC_NV10_TIL0AD 0x00400b00
-#define NVACC_NV10_TIL0ED 0x00400b04
-#define NVACC_NV10_TIL0PT 0x00400b08
-#define NVACC_NV10_TIL0ST 0x00400b0c
-#define NVACC_NV10_TIL1AD 0x00400b10
-#define NVACC_NV10_TIL1ED 0x00400b14
-#define NVACC_NV10_TIL1PT 0x00400b18
-#define NVACC_NV10_TIL1ST 0x00400b1c
-#define NVACC_NV10_TIL2AD 0x00400b20
-#define NVACC_NV10_TIL2ED 0x00400b24
-#define NVACC_NV10_TIL2PT 0x00400b28
-#define NVACC_NV10_TIL2ST 0x00400b2c
-#define NVACC_NV10_TIL3AD 0x00400b30
-#define NVACC_NV10_TIL3ED 0x00400b34
-#define NVACC_NV10_TIL3PT 0x00400b38
-#define NVACC_NV10_TIL3ST 0x00400b3c
-#define NVACC_NV10_TIL4AD 0x00400b40
-#define NVACC_NV10_TIL4ED 0x00400b44
-#define NVACC_NV10_TIL4PT 0x00400b48
-#define NVACC_NV10_TIL4ST 0x00400b4c
-#define NVACC_NV10_TIL5AD 0x00400b50
-#define NVACC_NV10_TIL5ED 0x00400b54
-#define NVACC_NV10_TIL5PT 0x00400b58
-#define NVACC_NV10_TIL5ST 0x00400b5c
-#define NVACC_NV10_TIL6AD 0x00400b60
-#define NVACC_NV10_TIL6ED 0x00400b64
-#define NVACC_NV10_TIL6PT 0x00400b68
-#define NVACC_NV10_TIL6ST 0x00400b6c
-#define NVACC_NV10_TIL7AD 0x00400b70
-#define NVACC_NV10_TIL7ED 0x00400b74
-#define NVACC_NV10_TIL7PT 0x00400b78
-#define NVACC_NV10_TIL7ST 0x00400b7c
-/* cache setup registers */
-#define NVACC_PF_INTSTAT 0x00002100
-#define NVACC_PF_INTEN 0x00002140
-#define NVACC_PF_RAMHT 0x00002210
-#define NVACC_PF_RAMFC 0x00002214
-#define NVACC_PF_RAMRO 0x00002218
-#define NVACC_PF_CACHES 0x00002500
-#define NVACC_PF_MODE 0x00002504
-#define NVACC_PF_SIZE 0x0000250c
-#define NVACC_PF_CACH0_PSH0 0x00003000
-#define NVACC_PF_CACH0_PUL0 0x00003050
-#define NVACC_PF_CACH0_PUL1 0x00003054
-#define NVACC_PF_CACH1_PSH0 0x00003200
-#define NVACC_PF_CACH1_PSH1 0x00003204
-#define NVACC_PF_CACH1_DMAS 0x00003220
-#define NVACC_PF_CACH1_DMAF 0x00003224
-#define NVACC_PF_CACH1_DMAI 0x0000322c
-#define NVACC_PF_CACH1_DMAC 0x00003230
-#define NVACC_PF_CACH1_DMAP 0x00003240
-#define NVACC_PF_CACH1_DMAG 0x00003244
-#define NVACC_PF_CACH1_PUL0 0x00003250
-#define NVACC_PF_CACH1_PUL1 0x00003254
-#define NVACC_PF_CACH1_HASH 0x00003258
-#define NVACC_PF_CACH1_ENG 0x00003280
-/* Ptimer registers */
-#define NVACC_PT_INTSTAT 0x00009100
-#define NVACC_PT_INTEN 0x00009140
-#define NVACC_PT_NUMERATOR 0x00009200
-#define NVACC_PT_DENOMINATR 0x00009210
-/* used PRAMIN registers */
-#define NVACC_PR_CTX0_R 0x00711400
-#define NVACC_PR_CTX1_R 0x00711404
-#define NVACC_PR_CTX2_R 0x00711408
-#define NVACC_PR_CTX3_R 0x0071140c
-#define NVACC_PR_CTX0_0 0x00711420
-#define NVACC_PR_CTX1_0 0x00711424
-#define NVACC_PR_CTX2_0 0x00711428
-#define NVACC_PR_CTX3_0 0x0071142c
-#define NVACC_PR_CTX0_1 0x00711430
-#define NVACC_PR_CTX1_1 0x00711434
-#define NVACC_PR_CTX2_1 0x00711438
-#define NVACC_PR_CTX3_1 0x0071143c
-#define NVACC_PR_CTX0_2 0x00711440
-#define NVACC_PR_CTX1_2 0x00711444
-#define NVACC_PR_CTX2_2 0x00711448
-#define NVACC_PR_CTX3_2 0x0071144c
-#define NVACC_PR_CTX0_3 0x00711450
-#define NVACC_PR_CTX1_3 0x00711454
-#define NVACC_PR_CTX2_3 0x00711458
-#define NVACC_PR_CTX3_3 0x0071145c
-#define NVACC_PR_CTX0_4 0x00711460
-#define NVACC_PR_CTX1_4 0x00711464
-#define NVACC_PR_CTX2_4 0x00711468
-#define NVACC_PR_CTX3_4 0x0071146c
-#define NVACC_PR_CTX0_5 0x00711470
-#define NVACC_PR_CTX1_5 0x00711474
-#define NVACC_PR_CTX2_5 0x00711478
-#define NVACC_PR_CTX3_5 0x0071147c
-#define NVACC_PR_CTX0_6 0x00711480
-#define NVACC_PR_CTX1_6 0x00711484
-#define NVACC_PR_CTX2_6 0x00711488
-#define NVACC_PR_CTX3_6 0x0071148c
-#define NVACC_PR_CTX0_7 0x00711490
-#define NVACC_PR_CTX1_7 0x00711494
-#define NVACC_PR_CTX2_7 0x00711498
-#define NVACC_PR_CTX3_7 0x0071149c
-#define NVACC_PR_CTX0_8 0x007114a0
-#define NVACC_PR_CTX1_8 0x007114a4
-#define NVACC_PR_CTX2_8 0x007114a8
-#define NVACC_PR_CTX3_8 0x007114ac
-#define NVACC_PR_CTX0_9 0x007114b0
-#define NVACC_PR_CTX1_9 0x007114b4
-#define NVACC_PR_CTX2_9 0x007114b8
-#define NVACC_PR_CTX3_9 0x007114bc
-#define NVACC_PR_CTX0_A 0x007114c0
-#define NVACC_PR_CTX1_A 0x007114c4 /* not used */
-#define NVACC_PR_CTX2_A 0x007114c8
-#define NVACC_PR_CTX3_A 0x007114cc
-#define NVACC_PR_CTX0_B 0x007114d0
-#define NVACC_PR_CTX1_B 0x007114d4
-#define NVACC_PR_CTX2_B 0x007114d8
-#define NVACC_PR_CTX3_B 0x007114dc
-#define NVACC_PR_CTX0_C 0x007114e0
-#define NVACC_PR_CTX1_C 0x007114e4
-#define NVACC_PR_CTX2_C 0x007114e8
-#define NVACC_PR_CTX3_C 0x007114ec
-#define NVACC_PR_CTX0_D 0x007114f0
-#define NVACC_PR_CTX1_D 0x007114f4
-#define NVACC_PR_CTX2_D 0x007114f8
-#define NVACC_PR_CTX3_D 0x007114fc
-#define NVACC_PR_CTX0_E 0x00711500
-#define NVACC_PR_CTX1_E 0x00711504
-#define NVACC_PR_CTX2_E 0x00711508
-#define NVACC_PR_CTX3_E 0x0071150c
-#define NVACC_PR_CTX0_F 0x00711510
-#define NVACC_PR_CTX1_F 0x00711514
-#define NVACC_PR_CTX2_F 0x00711518
-#define NVACC_PR_CTX3_F 0x0071151c
-#define NVACC_PR_CTX0_10 0x00711520
-#define NVACC_PR_CTX1_10 0x00711524
-#define NVACC_PR_CTX2_10 0x00711528
-#define NVACC_PR_CTX3_10 0x0071152c
-/* used RAMHT registers (hash-table) */
-#define NVACC_HT_HANDL_00 0x00710000
-#define NVACC_HT_VALUE_00 0x00710004
-#define NVACC_HT_HANDL_01 0x00710008
-#define NVACC_HT_VALUE_01 0x0071000c
-#define NVACC_HT_HANDL_02 0x00710010
-#define NVACC_HT_VALUE_02 0x00710014
-#define NVACC_HT_HANDL_03 0x00710018
-#define NVACC_HT_VALUE_03 0x0071001c
-#define NVACC_HT_HANDL_04 0x00710020
-#define NVACC_HT_VALUE_04 0x00710024
-#define NVACC_HT_HANDL_05 0x00710028
-#define NVACC_HT_VALUE_05 0x0071002c
-#define NVACC_HT_HANDL_06 0x00710030
-#define NVACC_HT_VALUE_06 0x00710034
-#define NVACC_HT_HANDL_10 0x00710080
-#define NVACC_HT_VALUE_10 0x00710084
-#define NVACC_HT_HANDL_11 0x00710088
-#define NVACC_HT_VALUE_11 0x0071008c
-#define NVACC_HT_HANDL_12 0x00710090
-#define NVACC_HT_VALUE_12 0x00710094
-#define NVACC_HT_HANDL_13 0x00710098
-#define NVACC_HT_VALUE_13 0x0071009c
-#define NVACC_HT_HANDL_14 0x007100a0
-#define NVACC_HT_VALUE_14 0x007100a4
-#define NVACC_HT_HANDL_15 0x007100a8
-#define NVACC_HT_VALUE_15 0x007100ac
-#define NVACC_HT_HANDL_16 0x007100b0
-#define NVACC_HT_VALUE_16 0x007100b4
-#define NVACC_HT_HANDL_17 0x007100b8
-#define NVACC_HT_VALUE_17 0x007100bc
-
-/* acc engine fifo setup registers (for function_register 'mappings') */
-#define NVACC_FIFO 0x00800000
-#define NVACC_FIFO_CH0 0x00800000
-#define NVACC_FIFO_CH1 0x00802000
-#define NVACC_FIFO_CH2 0x00804000
-#define NVACC_FIFO_CH3 0x00806000
-#define NVACC_FIFO_CH4 0x00808000
-#define NVACC_FIFO_CH5 0x0080a000
-#define NVACC_FIFO_CH6 0x0080c000
-#define NVACC_FIFO_CH7 0x0080e000
-
-/* Nvidia PCI direct registers */
-#define NV32_PWRUPCTRL 0x00000200
-#define NV32_DUALHEAD_CTRL 0x000010f0//verify!!!
-#define NV8_MISCW 0x000c03c2
-#define NV8_MISCR 0x000c03cc
-#define NV8_VSE2 0x000c03c3
-#define NV8_SEQIND 0x000c03c4
-#define NV16_SEQIND 0x000c03c4
-#define NV8_SEQDAT 0x000c03c5
-#define NV8_GRPHIND 0x000c03ce
-#define NV16_GRPHIND 0x000c03ce
-#define NV8_GRPHDAT 0x000c03cf
-
-/* bootstrap info registers */
-#define NV32_NV4STRAPINFO 0x00100000
-#define NV32_PFB_CONFIG_0 0x00100200
-#define NV32_PFB_CONFIG_1 0x00100204
-#define NV32_NV10STRAPINFO 0x0010020c
-#define NV32_FB_MRS1 0x001002c0
-#define NV32_FB_MRS2 0x001002c8
-#define NV32_PFB_CLS_PAGE2 0x0010033c
-#define NV32_NVSTRAPINFO2 0x00101000
-
-/* registers needed for 'coldstart' */
-#define NV32_PFB_DEBUG_0 0x00100080
-#define NV32_PFB_REFCTRL 0x00100210
-#define NV32_COREPLL 0x00680500
-#define NV32_MEMPLL 0x00680504
-#define NV32_PLL_CTRL 0x00680510
-#define NV32_COREPLL2 0x00680570 /* NV31, NV36 only */
-#define NV32_MEMPLL2 0x00680574 /* NV31, NV36 only */
-#define NV32_CONFIG 0x00600804
-
-/* primary head */
-#define NV8_ATTRINDW 0x006013c0
-#define NV8_ATTRDATW 0x006013c0
-#define NV8_ATTRDATR 0x006013c1
-#define NV8_CRTCIND 0x006013d4
-#define NV16_CRTCIND 0x006013d4
-#define NV8_CRTCDAT 0x006013d5
-#define NV8_INSTAT1 0x006013da
-#define NV32_NV10FBSTADD32 0x00600800
-#define NV32_RASTER 0x00600808
-#define NV32_NV10CURADD32 0x0060080c
-#define NV32_CURCONF 0x00600810
-#define NV32_PANEL_PWR 0x0060081c
-#define NV32_FUNCSEL 0x00600860
-
-/* secondary head */
-#define NV8_ATTR2INDW 0x006033c0
-#define NV8_ATTR2DATW 0x006033c0
-#define NV8_ATTR2DATR 0x006033c1
-#define NV8_CRTC2IND 0x006033d4
-#define NV16_CRTC2IND 0x006033d4
-#define NV8_CRTC2DAT 0x006033d5
-#define NV8_2INSTAT1 0x006033da//verify!!!
-#define NV32_NV10FB2STADD32 0x00602800
-#define NV32_RASTER2 0x00602808
-#define NV32_NV10CUR2ADD32 0x0060280c
-#define NV32_2CURCONF 0x00602810
-#define NV32_2PANEL_PWR 0x0060281c//verify!!!
-#define NV32_2FUNCSEL 0x00602860
-
-/* both heads */
-#define NVACC_NV11_CRTC_LO 0x00600830
-#define NVACC_NV11_CRTC_HI 0x00600834
-
-/* Nvidia DAC direct registers (standard VGA palette RAM registers) */
-/* primary head */
-#define NV8_PALMASK 0x006813c6
-#define NV8_PALINDR 0x006813c7
-#define NV8_PALINDW 0x006813c8
-#define NV8_PALDATA 0x006813c9
-/* secondary head */
-#define NV8_PAL2MASK 0x006833c6
-#define NV8_PAL2INDR 0x006833c7
-#define NV8_PAL2INDW 0x006833c8
-#define NV8_PAL2DATA 0x006833c9
-
-/* Nvidia PCI direct DAC registers (32bit) */
-/* primary head */
-#define NVDAC_CURPOS 0x00680300
-#define NVDAC_NV10_CURSYNC 0x00680404
-#define NVDAC_PIXPLLC 0x00680508
-#define NVDAC_PLLSEL 0x0068050c
-#define NVDAC_OUTPUT 0x0068052c
-#define NVDAC_PIXPLLC2 0x00680578
-#define NVDAC_GENCTRL 0x00680600
-#define NVDAC_TSTCTRL 0x00680608
-#define NVDAC_TSTDATA 0x00680610
-#define NVDAC_TV_SETUP 0x00680700
-/* (flatpanel registers: confirmed for TNT2 and up) */
-#define NVDAC_FP_VDISPEND 0x00680800
-#define NVDAC_FP_VTOTAL 0x00680804
-#define NVDAC_FP_VCRTC 0x00680808
-#define NVDAC_FP_VSYNC_S 0x0068080c
-#define NVDAC_FP_VSYNC_E 0x00680810
-#define NVDAC_FP_VVALID_S 0x00680814
-#define NVDAC_FP_VVALID_E 0x00680818
-#define NVDAC_FP_HDISPEND 0x00680820
-#define NVDAC_FP_HTOTAL 0x00680824
-#define NVDAC_FP_HCRTC 0x00680828
-#define NVDAC_FP_HSYNC_S 0x0068082c
-#define NVDAC_FP_HSYNC_E 0x00680830
-#define NVDAC_FP_HVALID_S 0x00680834
-#define NVDAC_FP_HVALID_E 0x00680838
-#define NVDAC_FP_CHKSUM 0x00680840
-#define NVDAC_FP_TST_CTRL 0x00680844
-#define NVDAC_FP_TG_CTRL 0x00680848
-#define NVDAC_FP_DEBUG0 0x00680880
-#define NVDAC_FP_DEBUG1 0x00680884
-#define NVDAC_FP_DEBUG2 0x00680888
-#define NVDAC_FP_DEBUG3 0x0068088c
-#define NVDAC_FP_TMDS_CTRL 0x006808b0
-#define NVDAC_FP_TMDS_DATA 0x006808b4
-/* secondary head */
-#define NVDAC2_CURPOS 0x00682300
-#define NVDAC2_NV10_CURSYNC 0x00682404
-#define NVDAC2_PIXPLLC 0x00680520
-#define NVDAC2_OUTPUT 0x0068252c
-#define NVDAC2_PIXPLLC2 0x0068057c
-#define NVDAC2_GENCTRL 0x00682600
-#define NVDAC2_TSTCTRL 0x00682608
-#define NVDAC2_TV_SETUP 0x00682700
-/* (flatpanel registers) */
-#define NVDAC2_FP_VDISPEND 0x00682800
-#define NVDAC2_FP_VTOTAL 0x00682804
-#define NVDAC2_FP_VCRTC 0x00682808
-#define NVDAC2_FP_VSYNC_S 0x0068280c
-#define NVDAC2_FP_VSYNC_E 0x00682810
-#define NVDAC2_FP_VVALID_S 0x00682814
-#define NVDAC2_FP_VVALID_E 0x00682818
-#define NVDAC2_FP_HDISPEND 0x00682820
-#define NVDAC2_FP_HTOTAL 0x00682824
-#define NVDAC2_FP_HCRTC 0x00682828
-#define NVDAC2_FP_HSYNC_S 0x0068282c
-#define NVDAC2_FP_HSYNC_E 0x00682830
-#define NVDAC2_FP_HVALID_S 0x00682834
-#define NVDAC2_FP_HVALID_E 0x00682838
-#define NVDAC2_FP_CHKSUM 0x00682840
-#define NVDAC2_FP_TST_CTRL 0x00682844
-#define NVDAC2_FP_TG_CTRL 0x00682848
-#define NVDAC2_FP_DEBUG0 0x00682880
-#define NVDAC2_FP_DEBUG1 0x00682884
-#define NVDAC2_FP_DEBUG2 0x00682888
-#define NVDAC2_FP_DEBUG3 0x0068288c
-#define NVDAC2_FP_TMDS_CTRL 0x006828b0//verify!!!
-#define NVDAC2_FP_TMDS_DATA 0x006828b4//verify!!!
-
-/* Nvidia CRTC indexed registers */
-/* VGA standard registers: */
-#define NVCRTCX_HTOTAL 0x00
-#define NVCRTCX_HDISPE 0x01
-#define NVCRTCX_HBLANKS 0x02
-#define NVCRTCX_HBLANKE 0x03
-#define NVCRTCX_HSYNCS 0x04
-#define NVCRTCX_HSYNCE 0x05
-#define NVCRTCX_VTOTAL 0x06
-#define NVCRTCX_OVERFLOW 0x07
-#define NVCRTCX_PRROWSCN 0x08
-#define NVCRTCX_MAXSCLIN 0x09
-#define NVCRTCX_VGACURCTRL 0x0a
-#define NVCRTCX_FBSTADDH 0x0c
-#define NVCRTCX_FBSTADDL 0x0d
-#define NVCRTCX_VSYNCS 0x10
-#define NVCRTCX_VSYNCE 0x11
-#define NVCRTCX_VDISPE 0x12
-#define NVCRTCX_PITCHL 0x13
-#define NVCRTCX_VBLANKS 0x15
-#define NVCRTCX_VBLANKE 0x16
-#define NVCRTCX_MODECTL 0x17
-#define NVCRTCX_LINECOMP 0x18
-/* Nvidia specific registers: */
-#define NVCRTCX_REPAINT0 0x19
-#define NVCRTCX_REPAINT1 0x1a
-#define NVCRTCX_FIFO 0x1b
-#define NVCRTCX_LOCK 0x1f
-#define NVCRTCX_FIFO_LWM 0x20
-#define NVCRTCX_BUFFER 0x21
-#define NVCRTCX_LSR 0x25
-#define NVCRTCX_PIXEL 0x28
-#define NVCRTCX_HEB 0x2d
-#define NVCRTCX_CURCTL2 0x2f
-#define NVCRTCX_CURCTL1 0x30
-#define NVCRTCX_CURCTL0 0x31
-#define NVCRTCX_LCD 0x33
-#define NVCRTCX_RD_I2CBUS_1 0x36
-#define NVCRTCX_WR_I2CBUS_1 0x37
-#define NVCRTCX_RMA 0x38
-#define NVCRTCX_INTERLACE 0x39
-#define NVCRTCX_TREG 0x3d
-#define NVCRTCX_RD_I2CBUS_0 0x3e
-#define NVCRTCX_WR_I2CBUS_0 0x3f
-#define NVCRTCX_EXTRA 0x41
-#define NVCRTCX_OWNER 0x44
-#define NVCRTCX_FP_HTIMING 0x53
-#define NVCRTCX_FP_VTIMING 0x54
-#define NVCRTCX_0x59 0x59
-#define NVCRTCX_0x9f 0x9f
-
-/* Nvidia ATTRIBUTE indexed registers */
-/* VGA standard registers: */
-#define NVATBX_MODECTL 0x10
-#define NVATBX_OSCANCOLOR 0x11
-#define NVATBX_COLPLANE_EN 0x12
-#define NVATBX_HORPIXPAN 0x13
-#define NVATBX_COLSEL 0x14
-
-/* Nvidia SEQUENCER indexed registers */
-/* VGA standard registers: */
-#define NVSEQX_RESET 0x00
-#define NVSEQX_CLKMODE 0x01
-#define NVSEQX_MEMMODE 0x04
-
-/* Nvidia GRAPHICS indexed registers */
-/* VGA standard registers: */
-#define NVGRPHX_ENSETRESET 0x01
-#define NVGRPHX_DATAROTATE 0x03
-#define NVGRPHX_READMAPSEL 0x04
-#define NVGRPHX_MODE 0x05
-#define NVGRPHX_MISC 0x06
-#define NVGRPHX_BITMASK 0x08
-
-/* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so
RIVA128(ZX)) */
-#define NVBES_NV04_INTE 0x00680140
-#define NVBES_NV04_ISCALVH 0x00680200
-#define NVBES_NV04_CTRL_V 0x00680204
-#define NVBES_NV04_CTRL_H 0x00680208
-#define NVBES_NV04_OE_STATE 0x00680224
-#define NVBES_NV04_SU_STATE 0x00680228
-#define NVBES_NV04_RM_STATE 0x0068022c
-#define NVBES_NV04_DSTREF 0x00680230
-#define NVBES_NV04_DSTSIZE 0x00680234
-#define NVBES_NV04_FIFOTHRS 0x00680238
-#define NVBES_NV04_FIFOBURL 0x0068023c
-#define NVBES_NV04_COLKEY 0x00680240
-#define NVBES_NV04_GENCTRL 0x00680244
-#define NVBES_NV04_RED_AMP 0x00680280
-#define NVBES_NV04_GRN_AMP 0x00680284
-#define NVBES_NV04_BLU_AMP 0x00680288
-#define NVBES_NV04_SAT 0x0068028c
-/* buffer 0 */
-#define NVBES_NV04_0BUFADR 0x0068020c
-#define NVBES_NV04_0SRCPTCH 0x00680214
-#define NVBES_NV04_0OFFSET 0x0068021c
-/* buffer 1 */
-#define NVBES_NV04_1BUFADR 0x00680210
-#define NVBES_NV04_1SRCPTCH 0x00680218
-#define NVBES_NV04_1OFFSET 0x00680220
-
-/* Nvidia BES (Back End Scaler) registers (>= NV10) */
-#define NVBES_NV10_INTE 0x00008140
-#define NVBES_NV10_BUFSEL 0x00008700
-#define NVBES_NV10_GENCTRL 0x00008704
-#define NVBES_NV10_COLKEY 0x00008b00
-/* buffer 0 */
-#define NVBES_NV10_0BUFADR 0x00008900
-#define NVBES_NV10_0MEMMASK 0x00008908
-#define NVBES_NV10_0BRICON 0x00008910
-#define NVBES_NV10_0SAT 0x00008918
-#define NVBES_NV10_0OFFSET 0x00008920
-#define NVBES_NV10_0SRCSIZE 0x00008928
-#define NVBES_NV10_0SRCREF 0x00008930
-#define NVBES_NV10_0ISCALH 0x00008938
-#define NVBES_NV10_0ISCALV 0x00008940
-#define NVBES_NV10_0DSTREF 0x00008948
-#define NVBES_NV10_0DSTSIZE 0x00008950
-#define NVBES_NV10_0SRCPTCH 0x00008958
-/* buffer 1 */
-#define NVBES_NV10_1BUFADR 0x00008904
-#define NVBES_NV10_1MEMMASK 0x0000890c
-#define NVBES_NV10_1BRICON 0x00008914
-#define NVBES_NV10_1SAT 0x0000891c
-#define NVBES_NV10_1OFFSET 0x00008924
-#define NVBES_NV10_1SRCSIZE 0x0000892c
-#define NVBES_NV10_1SRCREF 0x00008934
-#define NVBES_NV10_1ISCALH 0x0000893c
-#define NVBES_NV10_1ISCALV 0x00008944
-#define NVBES_NV10_1DSTREF 0x0000894c
-#define NVBES_NV10_1DSTSIZE 0x00008954
-#define NVBES_NV10_1SRCPTCH 0x0000895c
-/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */
-#define NVBES_DEC_GENCTRL 0x00001588
-/* LVDS panel related registers */
-#define NV32_LVDS_PWR 0x0000130c
-/* unknown registers */
-#define NV32_NV4X_WHAT0 0x00001540
-#define NV32_NV44_WHAT10 0x00001700
-#define NV32_NV44_WHAT11 0x00001704
-#define NV32_NV44_WHAT12 0x00001708
-#define NV32_NV44_WHAT13 0x0000170c
-
-/* Macros for convenient accesses to the NV chips */
-#define NV_REG8(r_) ((vuint8 *)regs)[(r_)]
-#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]
-#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
-
-/* read and write to PCI config space */
-#define CFGR(A) (*(nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI,
&nv_pci_access,sizeof(nv_pci_access)), &nv_pci_access.value))
-#define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B,
ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access)))
-
-/* read and write from ISA I/O space */
-#define ISAWB(A,B)(nv_isa_access.adress=A, nv_isa_access.data = (uint8)B,
nv_isa_access.size = 1, ioctl(fd,NV_ISA_OUT,
&nv_isa_access,sizeof(nv_isa_access)))
-#define ISAWW(A,B)(nv_isa_access.adress=A, nv_isa_access.data = B,
nv_isa_access.size = 2, ioctl(fd,NV_ISA_OUT,
&nv_isa_access,sizeof(nv_isa_access)))
-#define ISARB(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN,
&nv_isa_access,sizeof(nv_isa_access)), (uint8)nv_isa_access.data)
-#define ISARW(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN,
&nv_isa_access,sizeof(nv_isa_access)), nv_isa_access.data)
-
-/* read and write from the dac registers */
-#define DACR(A) (NV_REG32(NVDAC_##A))
-#define DACW(A,B) (NV_REG32(NVDAC_##A)=B)
-
-/* read and write from the secondary dac registers */
-#define DAC2R(A) (NV_REG32(NVDAC2_##A))
-#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B)
-
-/* read and write from the backend scaler registers */
-#define BESR(A) (NV_REG32(NVBES_##A))
-#define BESW(A,B) (NV_REG32(NVBES_##A)=B)
-
-/* read and write from CRTC indexed registers */
-#define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8)))
-#define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT))
-
-/* read and write from second CRTC indexed registers */
-#define CRTC2W(A,B)(NV_REG16(NV16_CRTC2IND) = ((NVCRTCX_##A) | ((B) << 8)))
-#define CRTC2R(A) (NV_REG8(NV8_CRTC2IND) = (NVCRTCX_##A),
NV_REG8(NV8_CRTC2DAT))
-
-/* read and write from ATTRIBUTE indexed registers */
-#define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A)
| 0x20), NV_REG8(NV8_ATTRDATW) = (B))
-#define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A)
| 0x20), NV_REG8(NV8_ATTRDATR))
-
-/* read and write from ATTRIBUTE indexed registers */
-#define ATB2W(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) =
((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATW) = (B))
-#define ATB2R(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) =
((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATR))
-
-/* read and write from SEQUENCER indexed registers */
-#define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8)))
-#define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT))
-
-/* read and write from PCI GRAPHICS indexed registers */
-#define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8)))
-#define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT))
-
-/* read and write from the acceleration engine registers */
-#define ACCR(A) (NV_REG32(NVACC_##A))
-#define ACCW(A,B) (NV_REG32(NVACC_##A)=B)
diff --git a/src/add-ons/accelerants/Jamfile b/src/add-ons/accelerants/Jamfile
index a709cb2..805d6ed 100644
--- a/src/add-ons/accelerants/Jamfile
+++ b/src/add-ons/accelerants/Jamfile
@@ -8,7 +8,6 @@ SubInclude HAIKU_TOP src add-ons accelerants intel_810 ;
SubInclude HAIKU_TOP src add-ons accelerants intel_extreme ;
SubInclude HAIKU_TOP src add-ons accelerants matrox ;
SubInclude HAIKU_TOP src add-ons accelerants neomagic ;
-SubInclude HAIKU_TOP src add-ons accelerants nvidia_gpgpu ;
SubInclude HAIKU_TOP src add-ons accelerants nvidia ;
SubInclude HAIKU_TOP src add-ons accelerants radeon ;
SubInclude HAIKU_TOP src add-ons accelerants radeon_hd ;
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/Acceleration.c
b/src/add-ons/accelerants/nvidia_gpgpu/Acceleration.c
deleted file mode 100644
index b872990..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/Acceleration.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- Copyright 1999, Be Incorporated. All Rights Reserved.
- This file may be used under the terms of the Be Sample Code License.
-
- Other authors:
- Rudolf Cornelissen 9/2003-6/2008.
-*/
-
-/*
- note:
- moved DMA acceleration 'top-level' routines to be integrated in the
engine:
- it is costly to call the engine for every single function within a loop!
- (measured with BeRoMeter 1.2.6: upto 15% speed increase on all CPU's.)
-*/
-
-#define MODULE_BIT 0x40000000
-
-#include "acc_std.h"
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/Cursor.c
b/src/add-ons/accelerants/nvidia_gpgpu/Cursor.c
deleted file mode 100644
index f738027..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/Cursor.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- Copyright 1999, Be Incorporated. All Rights Reserved.
- This file may be used under the terms of the Be Sample Code License.
-
- Other authors:
- Mark Watson,
- Rudolf Cornelissen 4/2003-6/2008
-*/
-
-#define MODULE_BIT 0x20000000
-
-#include "acc_std.h"
-
-status_t SET_CURSOR_SHAPE(uint16 width, uint16 height, uint16 hot_x, uint16
hot_y, uint8 *andMask, uint8 *xorMask)
-{
- LOG(4,("SET_CURSOR_SHAPE: width %d, height %d, hot_x %d, hot_y %d\n",
- width, height, hot_x, hot_y));
-
- if ((width != 16) || (height != 16))
- {
- return B_ERROR;
- }
- else if ((hot_x >= width) || (hot_y >= height))
- {
- return B_ERROR;
- }
- else
- {
- head1_cursor_define(andMask,xorMask);
- if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF)
- head2_cursor_define(andMask,xorMask);
-
- /* Update cursor variables appropriately. */
- si->cursor.width = width;
- si->cursor.height = height;
- si->cursor.hot_x = hot_x;
- si->cursor.hot_y = hot_y;
- }
-
- return B_OK;
-}
-
-/* Move the cursor to the specified position on the desktop, taking account of
virtual/dual issues */
-void MOVE_CURSOR(uint16 x, uint16 y)
-{
- uint16 hds = si->dm.h_display_start; /* the current horizontal
starting pixel */
- uint16 vds = si->dm.v_display_start; /* the current vertical
starting line */
- uint16 h_adjust;
-
- /* clamp cursor to display */
- if (x >= si->dm.virtual_width) x = si->dm.virtual_width - 1;
- if (y >= si->dm.virtual_height) y = si->dm.virtual_height - 1;
-
- /* store, for our info */
- si->cursor.x = x;
- si->cursor.y = y;
-
- /* setting up minimum amount to scroll not needed:
- * Nvidia cards can always do pixelprecise panning on both heads */
- h_adjust = 0x00;
-
- /* adjust h/v_display_start to move cursor onto screen */
- switch (si->dm.flags & DUALHEAD_BITS)
- {
- case DUALHEAD_ON:
- case DUALHEAD_SWITCH:
- if (x >= ((si->dm.timing.h_display * 2) + hds))
- {
- hds = ((x - (si->dm.timing.h_display * 2)) + 1 +
h_adjust) & ~h_adjust;
- /* make sure we stay within the display! */
- if ((hds + (si->dm.timing.h_display * 2)) >
si->dm.virtual_width)
- hds -= (h_adjust + 1);
- }
- else if (x < hds)
- hds = x & ~h_adjust;
- break;
- default:
- if (x >= (si->dm.timing.h_display + hds))
- {
- hds = ((x - si->dm.timing.h_display) + 1 + h_adjust) &
~h_adjust;
- /* make sure we stay within the display! */
- if ((hds + si->dm.timing.h_display) >
si->dm.virtual_width)
- hds -= (h_adjust + 1);
- }
- else if (x < hds)
- hds = x & ~h_adjust;
- break;
- }
-
- if (y >= (si->dm.timing.v_display + vds))
- vds = y - si->dm.timing.v_display + 1;
- else if (y < vds)
- vds = y;
-
- /* reposition the desktop _and_ the overlay on the display if required
*/
- if ((hds!=si->dm.h_display_start) || (vds!=si->dm.v_display_start))
- {
- MOVE_DISPLAY(hds,vds);
- }
-
- /* put cursor in correct physical position, so stay onscreen (rel. to
CRTC) */
- if (x > (hds + si->cursor.hot_x)) x -= (hds + si->cursor.hot_x);
- else x = 0;
- if (y > (vds + si->cursor.hot_y)) y -= (vds + si->cursor.hot_y);
- else y = 0;
-
- /* position the cursor on the display */
- switch (si->dm.flags & DUALHEAD_BITS)
- {
- case DUALHEAD_CLONE:
- head1_cursor_position(x,y);
- head2_cursor_position(x,y);
- break;
- case DUALHEAD_ON:
- case DUALHEAD_SWITCH:
- if (x < si->dm.timing.h_display)
- {
- if (si->cursor.dh_right)
- {
- LOG(4,("MOVE_CURSOR: now on left side\n"));
- head2_cursor_hide();
- head1_cursor_show();
- si->cursor.dh_right = false;
- }
- head1_cursor_position(x, y);
- }
- else
- {
- if (!si->cursor.dh_right)
- {
- LOG(4,("MOVE_CURSOR: now on right side\n"));
- head1_cursor_hide();
- head2_cursor_show();
- si->cursor.dh_right = true;
- }
- head2_cursor_position((x - si->dm.timing.h_display), y);
- }
- break;
- default: /* singlehead mode */
- head1_cursor_position(x,y);
- break;
- }
-}
-
-void SHOW_CURSOR(bool is_visible)
-{
- /* record for our info */
- si->cursor.is_visible = is_visible;
-
- switch (si->dm.flags & DUALHEAD_BITS)
- {
- case DUALHEAD_CLONE:
- if (is_visible)
- {
- head1_cursor_show();
- head2_cursor_show();
- }
- else
- {
- head1_cursor_hide();
- head2_cursor_hide();
- }
- break;
- case DUALHEAD_ON:
- case DUALHEAD_SWITCH:
- if (is_visible)
- {
- if (!si->cursor.dh_right)
- {
- head1_cursor_show();
- }
- else
- {
- head2_cursor_show();
- }
- }
- else
- {
- head1_cursor_hide();
- head2_cursor_hide();
- }
- break;
- default: /* singlehead mode */
- if (is_visible)
- {
- head1_cursor_show();
- }
- else
- {
- head1_cursor_hide();
- }
- break;
- }
-}
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/EngineManagment.c
b/src/add-ons/accelerants/nvidia_gpgpu/EngineManagment.c
deleted file mode 100644
index 7c58473..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/EngineManagment.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- Copyright 1999, Be Incorporated. All Rights Reserved.
- This file may be used under the terms of the Be Sample Code License.
-
- other authors:
- Mark Watson
- Rudolf Cornelissen 3/2004-6/2008
-*/
-
-#define MODULE_BIT 0x10000000
-
-#include "acc_std.h"
-
-
-static engine_token nv_engine_token = { 1, B_2D_ACCELERATION, NULL };
-
-uint32 ACCELERANT_ENGINE_COUNT(void)
-{
- /* we have one acceleration engine */
- return 1;
-}
-
-status_t ACQUIRE_ENGINE_DMA(uint32 capabilities, uint32 max_wait, sync_token
*st, engine_token **et)
-{
- /* acquire the shared benaphore */
- AQUIRE_BEN(si->engine.lock)
- /* sync if required */
- if (st) SYNC_TO_TOKEN(st);
-
- /* make sure all needed engine cmd's are mapped to the FIFO */
- nv_acc_assert_fifo_dma();
-
- /* return an engine token */
- *et = &nv_engine_token;
- return B_OK;
-}
-
-status_t RELEASE_ENGINE(engine_token *et, sync_token *st)
-{
- /* update the sync token, if any */
- if (st) GET_SYNC_TOKEN(et,st);
-
- /* release the shared benaphore */
- RELEASE_BEN(si->engine.lock)
- return B_OK;
-}
-
-void WAIT_ENGINE_IDLE(void)
-{
- /*wait for the engine to be totally idle*/
- nv_acc_wait_idle_dma();
-}
-
-status_t GET_SYNC_TOKEN(engine_token *et, sync_token *st)
-{
- /* engine count will always be zero: we don't support syncing to token
(yet) */
- st->engine_id = et->engine_id;
- st->counter = si->engine.count;
- return B_OK;
-}
-
-status_t SYNC_TO_TOKEN(sync_token *st)
-{
- /* wait until the engine is totally idle: we don't support syncing to
token (yet) */
- /* note:
- * AFAIK in order to be able to setup sync_to_token, we'd need a
circular fifo
- * buffer in (main) memory instead of directly programming the GPU fifo
so we
- * can tell (via a hardware maintained pointer into this circular fifo)
where
- * the acc engine is with executing commands! */
- WAIT_ENGINE_IDLE();
-
- return B_OK;
-}
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/GetAccelerantHook.c
b/src/add-ons/accelerants/nvidia_gpgpu/GetAccelerantHook.c
deleted file mode 100644
index d55042a..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/GetAccelerantHook.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- Copyright 1999, Be Incorporated. All Rights Reserved.
- This file may be used under the terms of the Be Sample Code License.
-
- Other authors:
- Mark Watson,
- Rudolf Cornelissen 10/2002-6/2008
-*/
-
-#define MODULE_BIT 0x08000000
-
-#include "acc_std.h"
-
-/*
-The standard entry point. Given a uint32 feature identifier, this routine
-returns a pointer to the function that implements the feature. Some features
-require more information than just the identifier to select the proper
-function. The extra information (which is specific to the feature) is
-pointed at by the void *data parameter. By default, no extra information
-is available. Any extra information available to choose the function will be
-noted on a case by case below.
-*/
-
-/*
-These definitions are out of pure lazyness.
-*/
-#define CHKA(x) case B_##x: \
- if (check_acc_capability(B_##x) == B_OK) \
- return (void *)x##_DMA; \
- else \
- return (void *)0
-#define CHKS(x) case B_##x: return (void *)x##_DMA
-#define HOOK(x) case B_##x: return (void *)x
-#define ZERO(x) case B_##x: return (void *)0
-#define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void
*)0; // apsed
-
-void * get_accelerant_hook(uint32 feature, void *data)
-{
- switch (feature)
- {
- /*
- One of either B_INIT_ACCELERANT or B_CLONE_ACCELERANT will be
requested and
- subsequently called before any other hook is requested. All
other feature
- hook selections can be predicated on variables assigned during
the accelerant
- initialization process.
- */
-
- /* initialization */
- HOOK(INIT_ACCELERANT);
- HOOK(CLONE_ACCELERANT);
-
- HOOK(ACCELERANT_CLONE_INFO_SIZE);
- HOOK(GET_ACCELERANT_CLONE_INFO);
- HOOK(UNINIT_ACCELERANT);
- HOOK(GET_ACCELERANT_DEVICE_INFO);
- HOOK(ACCELERANT_RETRACE_SEMAPHORE);
-
- /* mode configuration */
- HOOK(ACCELERANT_MODE_COUNT);
- HOOK(GET_MODE_LIST);
- HOOK(PROPOSE_DISPLAY_MODE);
- HOOK(SET_DISPLAY_MODE);
- HOOK(GET_DISPLAY_MODE);
- HOOK(GET_FRAME_BUFFER_CONFIG);
- HOOK(GET_PIXEL_CLOCK_LIMITS);
- HOOK(MOVE_DISPLAY);
- HOOK(SET_INDEXED_COLORS);
- HOOK(GET_TIMING_CONSTRAINTS);
-
- HOOK(DPMS_CAPABILITIES);
- HOOK(DPMS_MODE);
- HOOK(SET_DPMS_MODE);
-
- /* cursor managment */
- //HRDC(SET_CURSOR_SHAPE);
- //HRDC(MOVE_CURSOR);
- //HRDC(SHOW_CURSOR);
-
- /* synchronization */
- HOOK(ACCELERANT_ENGINE_COUNT);
- CHKS(ACQUIRE_ENGINE);
- HOOK(RELEASE_ENGINE);
- HOOK(WAIT_ENGINE_IDLE);
- HOOK(GET_SYNC_TOKEN);
- HOOK(SYNC_TO_TOKEN);
-
- /*
- Depending on the engine architecture, you may choose to provide
a different
- function to be used with each bit-depth for example.
-
- Note: These hooks are re-acquired by the app_server after each
mode switch.
- */
-
- /* video overlay functions are not supported */
-
- /*
- When requesting an acceleration hook, the calling application
provides a
- pointer to the display_mode for which the acceleration function
will be used.
- Depending on the engine architecture, you may choose to provide
a different
- function to be used with each bit-depth. In the sample driver
we return
- the same function all the time.
-
- Note: These hooks are re-acquired by the app_server after each
mode switch.
- */
-
- /* only export 2D acceleration functions in modes that are
capable of it */
- /* used by the app_server and applications (BWindowScreen) */
- //CHKA(SCREEN_TO_SCREEN_BLIT);
- //CHKA(FILL_RECTANGLE);
- //CHKA(INVERT_RECTANGLE);
- //CHKA(FILL_SPAN);
- /* not (yet) used by the app_server:
- * so just for application use (BWindowScreen) */
-// CHKA(SCREEN_TO_SCREEN_TRANSPARENT_BLIT);
- //CHKA(SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT);
- }
-
- /* Return a null pointer for any feature we don't understand. */
- return 0;
-}
-#undef CHKA
-#undef CHKD
-#undef HOOK
-#undef ZERO
-#undef HRDC
-
-status_t check_acc_capability(uint32 feature)
-{
- char *msg = "";
-
- /* setup logmessage text */
- switch (feature)
- {
- case B_SCREEN_TO_SCREEN_BLIT:
- msg = "B_SCREEN_TO_SCREEN_BLIT";
- break;
- case B_FILL_RECTANGLE:
- msg = "B_FILL_RECTANGLE";
- break;
- case B_INVERT_RECTANGLE:
- msg = "B_INVERT_RECTANGLE";
- break;
- case B_FILL_SPAN:
- msg = "B_FILL_SPAN";
- break;
- case B_SCREEN_TO_SCREEN_TRANSPARENT_BLIT:
- msg = "B_SCREEN_TO_SCREEN_TRANSPARENT_BLIT";
- break;
- case B_SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT:
- msg = "B_SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT";
- /* this function doesn't support the B_CMAP8 colorspace */
- //fixme: checkout B_CMAP8 support sometime, as some cards seem
to support it?
- if (si->dm.space == B_CMAP8)
- {
- LOG(4, ("Acc: Not exporting hook %s.\n", msg));
- return B_ERROR;
- }
- break;
- default:
- msg = "UNKNOWN";
- break;
- }
-
- /* hardware acceleration is only supported in modes with upto a certain
- * memory pitch.. */
- if (si->acc_mode)
- {
- LOG(4, ("Acc: Exporting hook %s.\n", msg));
- return B_OK;
- }
- else
- {
- LOG(4, ("Acc: Not exporting hook %s.\n", msg));
- return B_ERROR;
- }
-}
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/GetDeviceInfo.c
b/src/add-ons/accelerants/nvidia_gpgpu/GetDeviceInfo.c
deleted file mode 100644
index dac99cd..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/GetDeviceInfo.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- Author:
- Rudolf Cornelissen 7/2004-01/2006
-*/
-
-#define MODULE_BIT 0x04000000
-
-#include "acc_std.h"
-
-/* Get some info about the device */
-status_t GET_ACCELERANT_DEVICE_INFO(accelerant_device_info * adi)
-{
- LOG(4,("GET_ACCELERANT_DEVICE_INFO: returning info\n"));
-
- /* no info on version is provided, so presumably this is for my info */
- adi->version = 1;
-
- sprintf(adi->name, si->adi.name);
- sprintf(adi->chipset, si->adi.chipset);
- sprintf(adi->serial_no, "unknown");
- adi->memory = si->ps.memory_size;
- adi->dac_speed = si->ps.max_dac1_clock;
-
- return B_OK;
-}
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/GetModeInfo.c
b/src/add-ons/accelerants/nvidia_gpgpu/GetModeInfo.c
deleted file mode 100644
index 5a454d0..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/GetModeInfo.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- Copyright 1999, Be Incorporated. All Rights Reserved.
- This file may be used under the terms of the Be Sample Code License.
-
- Other authors:
- Mark Watson
- Rudolf Cornelissen 9/2002-10/2005
-*/
-
-#define MODULE_BIT 0x02000000
-
-#include "acc_std.h"
-
-/*
- Return the current display mode. The only time you might return an
- error is if a mode hasn't been set. Or if the system hands you a NULL
pointer.
-*/
-status_t GET_DISPLAY_MODE(display_mode *current_mode)
-{
- /* check for NULL pointer */
- if (current_mode == NULL) return B_ERROR;
-
- *current_mode = si->dm;
- return B_OK;
-}
-
-/* Return the frame buffer configuration information. */
-status_t GET_FRAME_BUFFER_CONFIG(frame_buffer_config *afb)
-{
- /* check for NULL pointer */
- if (afb == NULL) return B_ERROR;
-
- *afb = si->fbc;
- return B_OK;
-}
-
-/* Return the maximum and minium pixelclock limits for the specified mode. */
-/* NOTE:
- * Due to BeOS constraints output for all heads will be limited to the head
with
- * the least capabilities. */
-status_t GET_PIXEL_CLOCK_LIMITS(display_mode *dm, uint32 *low, uint32 *high)
-{
- uint32 max_pclk = 0;
- uint32 min_pclk = 0;
-
- /* check for NULL pointers */
- if ((dm == NULL) || (low == NULL) || (high == NULL)) return B_ERROR;
-
- /* specify requested info */
- if (dm->flags & DUALHEAD_BITS)
- {
- /* dualhead mode */
- /* find min. value */
- switch (si->ps.card_type)
- {
- default:
- *low = ((si->ps.min_video_vco * 1000) / 16);
- break;
- }
- /* find max. value:
- * using decondary DAC specs because they could be narrower
(twinview) */
- switch (dm->space)
- {
- case B_CMAP8:
- max_pclk = si->ps.max_dac2_clock_8;
- break;
- case B_RGB15_LITTLE:
- case B_RGB16_LITTLE:
- max_pclk = si->ps.max_dac2_clock_16;
- break;
- case B_RGB24_LITTLE:
- max_pclk = si->ps.max_dac2_clock_24;
- break;
- case B_RGB32_LITTLE:
- /* specially noted because of RAM speed
constraints! */
- max_pclk = si->ps.max_dac2_clock_32dh;
- break;
- default:
- /* use fail-safe value */
- max_pclk = si->ps.max_dac2_clock_32dh;
- break;
- }
- /* return values in kHz */
- *high = max_pclk * 1000;
- }
- else
- {
- /* singlehead mode */
- /* find min. value */
- switch (si->ps.card_type)
- {
- default:
- *low = ((si->ps.min_pixel_vco * 1000) / 16);
- break;
- }
- /* find max. value: depends on which head is used as primary
head */
- if (!si->ps.crtc2_prim)
- {
- switch (dm->space)
- {
- case B_CMAP8:
- max_pclk = si->ps.max_dac1_clock_8;
- break;
- case B_RGB15_LITTLE:
- case B_RGB16_LITTLE:
- max_pclk = si->ps.max_dac1_clock_16;
- break;
- case B_RGB24_LITTLE:
- max_pclk = si->ps.max_dac1_clock_24;
- break;
- case B_RGB32_LITTLE:
- max_pclk = si->ps.max_dac1_clock_32;
- break;
- default:
- /* use fail-safe value */
- max_pclk = si->ps.max_dac1_clock_32;
- break;
- }
- }
- else
- {
- switch (dm->space)
- {
- case B_CMAP8:
- max_pclk = si->ps.max_dac2_clock_8;
- break;
- case B_RGB15_LITTLE:
- case B_RGB16_LITTLE:
- max_pclk = si->ps.max_dac2_clock_16;
- break;
- case B_RGB24_LITTLE:
- max_pclk = si->ps.max_dac2_clock_24;
- break;
- case B_RGB32_LITTLE:
- max_pclk = si->ps.max_dac2_clock_32;
- break;
- default:
- /* use fail-safe value */
- max_pclk = si->ps.max_dac2_clock_32;
- break;
- }
- }
- /* return values in kHz */
- *high = max_pclk * 1000;
- }
-
- /* clamp lower limit to 48Hz vertical refresh for now.
- * Apparantly the BeOS screenprefs app does limit the upper refreshrate
to 90Hz,
- * while it does not limit the lower refreshrate. */
- min_pclk = ((uint32)dm->timing.h_total * (uint32)dm->timing.v_total *
48) / 1000;
- if (min_pclk > *low) *low = min_pclk;
-
- return B_OK;
-}
-
-/* Return the semaphore id that will be used to signal a vertical sync
occured. */
-sem_id ACCELERANT_RETRACE_SEMAPHORE(void)
-{
- if (si->ps.int_assigned)
- return si->vblank;
- else
- return B_ERROR;
-}
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/GetTimingConstraints.c
b/src/add-ons/accelerants/nvidia_gpgpu/GetTimingConstraints.c
deleted file mode 100644
index 2b00bbb..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/GetTimingConstraints.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- Author:
- Rudolf Cornelissen 7/2004
-*/
-
-#define MODULE_BIT 0x01000000
-
-#include "acc_std.h"
-
-/* Used to help generate mode lines */
-status_t GET_TIMING_CONSTRAINTS(display_timing_constraints * dtc)
-{
- LOG(4, ("GET_TIMING_CONSTRAINTS: returning info\n"));
-
- /* specs are identical for all nVidia cards */
- dtc->h_res = 8;
- dtc->h_sync_min = 8;
- dtc->h_sync_max = 248;
- /* Note:
- * h_blank info is used to determine the max. diff. between h_total and
h_display! */
- dtc->h_blank_min = 8;
- dtc->h_blank_max = 1016;
-
- dtc->v_res = 1;
- dtc->v_sync_min = 1;
- dtc->v_sync_max = 15;
- /* Note:
- * v_blank info is used to determine the max. diff. between v_total and
v_display! */
- dtc->v_blank_min = 1;
- dtc->v_blank_max = 255;
-
- return B_OK;
-}
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c
b/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c
deleted file mode 100644
index 4b906a8..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- Copyright 1999, Be Incorporated. All Rights Reserved.
- This file may be used under the terms of the Be Sample Code License.
-
- Other authors:
- Mark Watson,
- Rudolf Cornelissen 10/2002-6/2008.
-*/
-
-#define MODULE_BIT 0x00800000
-
-#include <string.h>
-#include <unistd.h>
-#include "acc_std.h"
-
-static status_t init_common(int the_fd);
-
-/* Initialization code shared between primary and cloned accelerants */
-static status_t init_common(int the_fd) {
- status_t result;
- nv_get_private_data gpd;
-
- // LOG not available from here to next LOG: NULL si
-
- /* memorize the file descriptor */
- fd = the_fd;
- /* set the magic number so the driver knows we're for real */
- gpd.magic = NV_PRIVATE_DATA_MAGIC;
- /* contact driver and get a pointer to the registers and shared data */
- result = ioctl(fd, NV_GET_PRIVATE_DATA, &gpd, sizeof(gpd));
- if (result != B_OK) goto error0;
-
- /* clone the shared area for our use */
- shared_info_area = clone_area(DRIVER_PREFIX " shared", (void **)&si,
B_ANY_ADDRESS,
- B_READ_AREA | B_WRITE_AREA, gpd.shared_info_area);
- if (shared_info_area < 0) {
- result = shared_info_area;
- goto error0;
- }
- // LOG is now available, si !NULL
- LOG(4,("init_common: logmask 0x%08x, memory %dMB, hardcursor %d,
usebios %d, switchhead %d\n",
- si->settings.logmask, si->settings.memory,
si->settings.hardcursor, si->settings.usebios, si->settings.switchhead));
- LOG(4,("init_common: dumprom %d, pgm_panel %d\n",
- si->settings.dumprom, si->settings.pgm_panel));
- LOG(4,("init_common: force_sync %d, gpu_clk %dMhz, ram_clk %dMhz,
force_ws %d\n",
- si->settings.force_sync, si->settings.gpu_clk,
si->settings.ram_clk, si->settings.force_ws));
-
- /*Check for R4.5.0 and if it is running, use work around*/
- {
- if (si->use_clone_bugfix)
- {
- /*check for R4.5.0 bug and attempt to work around*/
- LOG(2,("InitACC: Found R4.5.0 bug - attempting to work
around\n"));
- regs = si->clone_bugfix_regs;
- }
- else
- {
- /* clone the memory mapped registers for our use -
does not work on <4.5.2 (but is better this way)*/
- regs_area = clone_area(DRIVER_PREFIX " regs", (void
**)®s, B_ANY_ADDRESS,
- B_READ_AREA | B_WRITE_AREA, si->regs_area);
- if (regs_area < 0) {
- result = regs_area;
- goto error1;
- }
- }
- }
-
- /* all done */
- goto error0;
-
-error1:
- delete_area(shared_info_area);
-error0:
- return result;
-}
-
-/* Clean up code shared between primary and cloned accelrants */
-static void uninit_common(void) {
- /* release the memory mapped registers */
- delete_area(regs_area);
- /* a little cheap paranoia */
- regs = 0;
- /* release our copy of the shared info from the kernel driver */
- delete_area(shared_info_area);
- /* more cheap paranoia */
- si = 0;
-}
-
-/*
-Initialize the accelerant. the_fd is the file handle of the device (in
-/dev/graphics) that has been opened by the app_server (or some test harness).
-We need to determine if the kernel driver and the accelerant are compatible.
-If they are, get the accelerant ready to handle other hook functions and
-report success or failure.
-*/
-status_t INIT_ACCELERANT(int the_fd)
-{
- status_t result;
- int pointer_reservation; //mem reserved for pointer
-
- if (0) {
- time_t now = time (NULL);
- // LOG not available from here to next LOG: NULL si
- MSG(("INIT_ACCELERANT: %s", ctime (&now)));
- }
-
- /* note that we're the primary accelerant (accelerantIsClone is global)
*/
- accelerantIsClone = 0;
-
- /* do the initialization common to both the primary and the clones */
- result = init_common(the_fd);
-
- /* bail out if the common initialization failed */
- if (result != B_OK) goto error0;
- // LOG now available: !NULL si
-
- /* ensure that INIT_ACCELERANT is executed just once (copies should be
clones) */
- if (si->accelerant_in_use)
- {
- result = B_NOT_ALLOWED;
- goto error1;
- }
-
- /* call the device specific init code */
- result = nv_general_powerup();
-
- /* bail out if it failed */
- if (result != B_OK) goto error1;
-
- /*
- Now would be a good time to figure out what video modes your card
supports.
- We'll place the list of modes in another shared area so all of the
copies
- of the driver can see them. The primary copy of the accelerant (ie the
one
- initialized with this routine) will own the "one true copy" of the list.
- Everybody else get's a read-only clone.
- */
- result = create_mode_list();
- if (result != B_OK)
- {
- goto error1;
- }
-
- /*
- Put the cursor at the start of the frame buffer.
- Nvidia cursor is 32x32 16 color? takes up 4096 bytes of RAM.
- */
- /* Initialize the rest of the cursor information while we're here */
- si->cursor.width = 16;
- si->cursor.height = 16;
- si->cursor.hot_x = 0;
- si->cursor.hot_y = 0;
- si->cursor.x = 0;
- si->cursor.y = 0;
- si->cursor.dh_right = false;
-
- /*
- Put the frame buffer immediately following the cursor data. We store
this
- info in a frame_buffer_config structure to make it convienient to return
- to the app_server later.
- */
- pointer_reservation = 0;
- /* Nvidia hardcursor needs 2kB space */
- if (si->settings.hardcursor) pointer_reservation = 2048;
-
- si->fbc.frame_buffer = (void *)((char
*)si->framebuffer+pointer_reservation);
- si->fbc.frame_buffer_dma = (void *)((char
*)si->framebuffer_pci+pointer_reservation);
-
- /* count of issued parameters or commands */
- si->engine.last_idle = si->engine.count = 0;
- /* no 3D clones are currently loaded */
- si->engine.threeD.clones = 0;
- /* tell 3D add-ons that they should reload their rendering states and
surfaces */
- si->engine.threeD.reload = 0xffffffff;
- INIT_BEN(si->engine.lock);
-
- /* bail out if something failed */
- if (result != B_OK) goto error1;
-
- /* initialise various cursor stuff */
- head1_cursor_init();
- if (si->ps.secondary_head) head2_cursor_init();
-
- /* ensure cursor state */
- head1_cursor_hide();
- if (si->ps.secondary_head) head2_cursor_hide();
-
- /* ensure DPMS state */
- si->dpms_flags = B_DPMS_ON;
-
- /* make sure a possible 3D add-on will block rendering and
re-initialize itself.
- * note: update in _this_ order only */
- /* SET_DISPLAY_MODE will reset this flag when it's done. */
- si->engine.threeD.mode_changing = true;
- /* every 3D add-on will reset this bit-flag when it's done. */
- si->engine.threeD.newmode = 0xffffffff;
-
- /* a winner! */
- result = B_OK;
- /* ensure that INIT_ACCELERANT won't be executed again (copies should
be clones) */
- si->accelerant_in_use = true;
- goto error0;
-
-error1:
- /*
- Initialization failed after init_common() succeeded, so we need to clean
- up before quiting.
- */
- uninit_common();
-
-error0:
- return result;
-}
-
-/*
-Return the number of bytes required to hold the information required
-to clone the device.
-*/
-ssize_t ACCELERANT_CLONE_INFO_SIZE(void) {
- /*
- Since we're passing the name of the device as the only required
- info, return the size of the name buffer
- */
- return B_OS_NAME_LENGTH; // apsed, was MAX_NV_DEVICE_NAME_LENGTH;
-}
-
-
-/*
-Return the info required to clone the device. void *data points to
-a buffer at least ACCELERANT_CLONE_INFO_SIZE() bytes in length.
-*/
-void GET_ACCELERANT_CLONE_INFO(void *data) {
- nv_device_name dn;
- status_t result;
-
- /* call the kernel driver to get the device name */
- dn.magic = NV_PRIVATE_DATA_MAGIC;
- /* store the returned info directly into the passed buffer */
- dn.name = (char *)data;
- result = ioctl(fd, NV_DEVICE_NAME, &dn, sizeof(dn));
-}
-
-/*
-Initialize a copy of the accelerant as a clone. void *data points to
-a copy of the data returned by GET_ACCELERANT_CLONE_INFO().
-*/
-status_t CLONE_ACCELERANT(void *data)
-{
- status_t result;
- char path[MAXPATHLEN];
-
- /* the data is the device name */
- /* Note: the R4 graphics driver kit is in error here (missing trailing
'/') */
- strcpy(path, "/dev/");
- strcat(path, (const char *)data);
- /* open the device, the permissions aren't important */
- fd = open(path, B_READ_WRITE);
- if (fd < 0)
- {
- /* we can't use LOG because we didn't get the shared_info
struct.. */
- char fname[64];
- FILE *myhand = NULL;
-
- sprintf (fname, "/boot/home/" DRIVER_PREFIX
".accelerant.0.log");
- myhand=fopen(fname,"a+");
- fprintf(myhand, "CLONE_ACCELERANT: couldn't open kerneldriver
%s! Aborting.\n", path);
- fclose(myhand);
-
- /* abort with resultcode from open attempt on kerneldriver */
- result = fd;
- goto error0;
- }
-
- /* note that we're a clone accelerant */
- accelerantIsClone = 1;
-
- /* call the shared initialization code */
- result = init_common(fd);
-
- /* bail out if the common initialization failed */
- if (result != B_OK) goto error1;
-
- /* ensure that INIT_ACCELERANT is executed first (i.e. primary
accelerant exists) */
- if (!(si->accelerant_in_use))
- {
- result = B_NOT_ALLOWED;
- goto error2;
- }
-
- /* setup CRTC and DAC functions access */
- //fixme: setup_virtualized_heads is a problem for clones: needs to be
run
- //for each clone if the mode is changed!
- if (si->ps.secondary_head)
- setup_virtualized_heads(si->crtc_switch_mode);
- else
- setup_virtualized_heads(si->ps.crtc2_prim);
-
- /* get shared area for display modes */
- result = my_mode_list_area = clone_area(
- DRIVER_PREFIX " cloned display_modes",
- (void **)&my_mode_list,
- B_ANY_ADDRESS,
- B_READ_AREA,
- si->mode_area
- );
- if (result < B_OK) goto error2;
-
- /* all done */
- LOG(4,("CLONE_ACCELERANT: cloning was succesfull.\n"));
-
- result = B_OK;
- goto error0;
-
-error2:
- /* free up the areas we cloned */
- uninit_common();
-error1:
- /* close the device we opened */
- close(fd);
-error0:
- return result;
-}
-
-void UNINIT_ACCELERANT(void)
-{
- if (accelerantIsClone)
- {
- LOG(4,("UNINIT_ACCELERANT: shutting down clone accelerant.\n"));
- }
- else
- {
- LOG(4,("UNINIT_ACCELERANT: shutting down primary
accelerant.\n"));
-
- /* delete benaphores ONLY if we are the primary accelerant */
- DELETE_BEN(si->engine.lock);
-
- /* ensure that INIT_ACCELERANT can be executed again */
- si->accelerant_in_use = false;
- }
-
- /* free our mode list area */
- delete_area(my_mode_list_area);
- /* paranoia */
- my_mode_list = 0;
- /* release our cloned data */
- uninit_common();
- /* close the file handle ONLY if we're the clone */
- if (accelerantIsClone) close(fd);
-}
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/Jamfile
b/src/add-ons/accelerants/nvidia_gpgpu/Jamfile
deleted file mode 100644
index dfbb1e6..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/Jamfile
+++ /dev/null
@@ -1,25 +0,0 @@
-SubDir HAIKU_TOP src add-ons accelerants nvidia_gpgpu ;
-
-SetSubDirSupportedPlatformsBeOSCompatible ;
-
-UsePrivateHeaders graphics ;
-UsePrivateHeaders [ FDirName graphics nvidia_gpgpu ] ;
-UseHeaders [ FDirName $(SUBDIR) engine ] ;
-
-Addon nvidia_gpgpu.accelerant :
- Acceleration.c
- Cursor.c
- EngineManagment.c
- GetAccelerantHook.c
- GetDeviceInfo.c
- GetModeInfo.c
- GetTimingConstraints.c
- InitAccelerant.c
- ProposeDisplayMode.c
- SetDisplayMode.c
- : libnvidia_gpgpu_engine.a
-;
-
-Depends nvidia_gpgpu.accelerant : nvidia_gpgpu ;
-
-SubInclude HAIKU_TOP src add-ons accelerants nvidia_gpgpu engine ;
diff --git a/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c
b/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c
deleted file mode 100644
index d604822..0000000
--- a/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- Copyright 1999, Be Incorporated. All Rights Reserved.
- This file may be used under the terms of the Be Sample Code License.
-
- Other authors for NV driver:
- Mark Watson,
- Rudolf Cornelissen 9/2002-6/2008
-*/
-
-#define MODULE_BIT 0x00400000
-
-#include "acc_std.h"
-
-#define T_POSITIVE_SYNC (B_POSITIVE_HSYNC | B_POSITIVE_VSYNC)
-/* mode flags will be setup as status info by PROPOSEMODE! */
-#define MODE_FLAGS 0
-#define MODE_COUNT (sizeof (mode_list) / sizeof (display_mode))
-
-/*some monitors only handle a fixed set of modes*/
-#include "valid_mode_list"
-
-/* Standard VESA modes,
- * plus panel specific resolution modes which are internally modified during
run-time depending on the requirements of the actual
[ *** diff truncated: 10736 lines dropped *** ]
