[haiku-commits] haiku: hrev44441 - headers/private/graphics/radeon_hd src/add-ons/accelerants/radeon_hd
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Mon, 30 Jul 2012 22:57:59 +0200 (CEST)
hrev44441 adds 2 changesets to branch 'master'
old head: 7e38f21a04cd60db61de862e654aeb3b027a708a
new head: 93aac98d0a9b8ce27f94eb449cfc742446a50274
----------------------------------------------------------------------------
8ef0a0d: radeon_hd: Card define cleanup
* Trying to do cleanup on the layout of these headers
93aac98: radeon_hd: r5xx to Avivo define cleanup
* Reorganize and clean up card defines
* Fix define spaces
* Unify card naming
* No (real) functional change
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
14 files changed, 1009 insertions(+), 1003 deletions(-)
headers/private/graphics/radeon_hd/avivo.h | 65 --
headers/private/graphics/radeon_hd/avivo_reg.h | 561 ++++++++++++++++
headers/private/graphics/radeon_hd/evergreen_reg.h | 8 +
headers/private/graphics/radeon_hd/r500_reg.h | 511 +-------------
headers/private/graphics/radeon_hd/r600_reg.h | 279 ++++----
headers/private/graphics/radeon_hd/r700_reg.h | 422 ++++++------
headers/private/graphics/radeon_hd/radeon_hd.h | 4 +-
src/add-ons/accelerants/radeon_hd/bios.cpp | 8 +-
src/add-ons/accelerants/radeon_hd/display.cpp | 20 +-
src/add-ons/accelerants/radeon_hd/encoder.cpp | 22 +-
src/add-ons/accelerants/radeon_hd/gpu.cpp | 88 +--
src/add-ons/accelerants/radeon_hd/gpu.h | 6 -
src/add-ons/accelerants/radeon_hd/mode.cpp | 12 +-
.../drivers/graphics/radeon_hd/radeon_hd.cpp | 6 +-
############################################################################
Commit: 8ef0a0d2a6c2dafb2f162c5ae2fbbd55a3ec8f32
URL: http://cgit.haiku-os.org/haiku/commit/?id=8ef0a0d
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Mon Jul 30 19:23:49 2012 UTC
radeon_hd: Card define cleanup
* Trying to do cleanup on the layout of these headers
----------------------------------------------------------------------------
diff --git a/headers/private/graphics/radeon_hd/evergreen_reg.h
b/headers/private/graphics/radeon_hd/evergreen_reg.h
index 0cab355..9183414 100644
--- a/headers/private/graphics/radeon_hd/evergreen_reg.h
+++ b/headers/private/graphics/radeon_hd/evergreen_reg.h
@@ -47,6 +47,14 @@
*/
+#define EVERGREEN_HDP_HOST_PATH_CNTL 0x2C00
+#define EVERGREEN_HDP_NONSURFACE_BASE 0x2C04
+#define EVERGREEN_HDP_NONSURFACE_INFO 0x2C08
+#define EVERGREEN_HDP_NONSURFACE_SIZE 0x2C0C
+#define EVERGREEN_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
+#define EVERGREEN_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+#define EVERGREEN_HDP_TILING_CONFIG
0x2F3C
+
#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
#define EVERGREEN_D3VGA_CONTROL 0x3e0
diff --git a/headers/private/graphics/radeon_hd/r600_reg.h
b/headers/private/graphics/radeon_hd/r600_reg.h
index 2def1ce..5c27c01 100644
--- a/headers/private/graphics/radeon_hd/r600_reg.h
+++ b/headers/private/graphics/radeon_hd/r600_reg.h
@@ -29,164 +29,173 @@
#define __R600_REG_H__
-#define R600_CRTC0_REGISTER_OFFSET 0x0
-#define R600_CRTC1_REGISTER_OFFSET 0x800
-
-
-#define R600_PCIE_PORT_INDEX 0x0038
-#define R600_PCIE_PORT_DATA 0x003c
-
-#define R600_MC_VM_FB_LOCATION 0x2180
-#define R600_MC_FB_BASE_MASK 0x0000FFFF
-#define R600_MC_FB_BASE_SHIFT 0
-#define R600_MC_FB_TOP_MASK 0xFFFF0000
-#define R600_MC_FB_TOP_SHIFT 16
-#define R600_MC_VM_AGP_TOP 0x2184
-#define R600_MC_AGP_TOP_MASK 0x0003FFFF
-#define R600_MC_AGP_TOP_SHIFT 0
-#define R600_MC_VM_AGP_BOT 0x2188
-#define R600_MC_AGP_BOT_MASK 0x0003FFFF
-#define R600_MC_AGP_BOT_SHIFT 0
-#define R600_MC_VM_AGP_BASE 0x218c
-#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
-#define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
-#define R600_LOGICAL_PAGE_NUMBER_SHIFT 0
+/* Scratch Registers */
+#define R600_BIOS_0_SCRATCH 0x1724
+#define R600_BIOS_1_SCRATCH 0x1728
+#define R600_BIOS_2_SCRATCH 0x172c
+#define R600_BIOS_3_SCRATCH 0x1730
+#define R600_BIOS_4_SCRATCH 0x1734
+#define R600_BIOS_5_SCRATCH 0x1738
+#define R600_BIOS_6_SCRATCH 0x173c
+#define R600_BIOS_7_SCRATCH 0x1740
+
+
+#define R600_CRTC0_REGISTER_OFFSET 0x0
+#define R600_CRTC1_REGISTER_OFFSET 0x800
+
+#define R600_PCIE_PORT_INDEX 0x0038
+#define R600_PCIE_PORT_DATA 0x003c
+
+#define R600_MC_VM_FB_LOCATION 0x2180
+#define R600_MC_FB_BASE_MASK 0x0000FFFF
+#define R600_MC_FB_BASE_SHIFT 0
+#define R600_MC_FB_TOP_MASK
0xFFFF0000
+#define R600_MC_FB_TOP_SHIFT 16
+#define R600_MC_VM_AGP_TOP 0x2184
+#define R600_MC_AGP_TOP_MASK 0x0003FFFF
+#define R600_MC_AGP_TOP_SHIFT 0
+#define R600_MC_VM_AGP_BOT 0x2188
+#define R600_MC_AGP_BOT_MASK 0x0003FFFF
+#define R600_MC_AGP_BOT_SHIFT 0
+#define R600_MC_VM_AGP_BASE 0x218c
+#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
+#define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
+#define R600_LOGICAL_PAGE_NUMBER_SHIFT 0
#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
-#define R600_RAMCFG 0x2408
-# define R600_CHANSIZE (1 << 7)
-# define R600_CHANSIZE_OVERRIDE (1 << 10)
-
-#define R600_GENERAL_PWRMGT 0x618
-# define R600_OPEN_DRAIN_PADS (1 << 11)
-
-#define R600_LOWER_GPIO_ENABLE 0x710
-#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
-#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
-#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
-#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
-
-#define R600_D1GRPH_SWAP_CONTROL 0x610C
-# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
-
-#define R600_HDP_NONSURFACE_BASE 0x2c04
-
-#define R600_BUS_CNTL 0x5420
-# define R600_BIOS_ROM_DIS (1 << 1)
-#define R600_CONFIG_CNTL 0x5424
-#define R600_CONFIG_MEMSIZE 0x5428
-#define R600_CONFIG_F0_BASE 0x542C
-#define R600_CONFIG_APER_SIZE 0x5430
-
-#define R600_ROM_CNTL 0x1600
-# define R600_SCK_OVERWRITE (1 << 1)
-# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
-# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
-
-#define R600_CG_SPLL_FUNC_CNTL 0x600
-# define R600_SPLL_BYPASS_EN (1 << 3)
-#define R600_CG_SPLL_STATUS 0x60c
-# define R600_SPLL_CHG_STATUS (1 << 1)
-
-#define R600_BIOS_0_SCRATCH 0x1724
-#define R600_BIOS_1_SCRATCH 0x1728
-#define R600_BIOS_2_SCRATCH 0x172c
-#define R600_BIOS_3_SCRATCH 0x1730
-#define R600_BIOS_4_SCRATCH 0x1734
-#define R600_BIOS_5_SCRATCH 0x1738
-#define R600_BIOS_6_SCRATCH 0x173c
-#define R600_BIOS_7_SCRATCH 0x1740
+#define R600_RAMCFG
0x2408
+#define R600_CHANSIZE (1 << 7)
+#define R600_CHANSIZE_OVERRIDE (1 << 10)
+
+#define R600_GENERAL_PWRMGT 0x618
+#define R600_OPEN_DRAIN_PADS (1 << 11)
+
+#define R600_LOWER_GPIO_ENABLE 0x710
+#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
+#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
+#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
+#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
+
+#define R600_D1GRPH_SWAP_CONTROL 0x610C
+#define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
+#define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
+#define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
+#define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
+
+#define R600_HDP_HOST_PATH_CNTL 0x2C00
+#define R600_HDP_NONSURFACE_BASE 0x2C04
+#define R600_HDP_NONSURFACE_INFO 0x2C08
+#define R600_HDP_NONSURFACE_SIZE 0x2C0C
+#define R600_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+#define R600_HDP_TILING_CONFIG 0x2F3C
+#define R600_HDP_DEBUG1
0x2F34
+
+#define R600_BUS_CNTL 0x5420
+#define R600_BIOS_ROM_DIS (1 << 1)
+#define R600_CONFIG_CNTL 0x5424
+#define R600_CONFIG_MEMSIZE 0x5428
+#define R600_CONFIG_F0_BASE 0x542C
+#define R600_CONFIG_APER_SIZE 0x5430
+
+#define R600_ROM_CNTL 0x1600
+#define R600_SCK_OVERWRITE (1 << 1)
+#define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
+#define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
+
+#define R600_CG_SPLL_FUNC_CNTL 0x600
+#define R600_SPLL_BYPASS_EN (1 << 3)
+#define R600_CG_SPLL_STATUS 0x60c
+#define R600_SPLL_CHG_STATUS (1 << 1)
+
/* Audio, these regs were reverse enginered,
* so the chance is high that the naming is wrong
* R6xx+ ??? */
/* Audio clocks */
-#define R600_AUDIO_PLL1_MUL 0x0514
-#define R600_AUDIO_PLL1_DIV 0x0518
-#define R600_AUDIO_PLL2_MUL 0x0524
-#define R600_AUDIO_PLL2_DIV 0x0528
-#define R600_AUDIO_CLK_SRCSEL 0x0534
+#define R600_AUDIO_PLL1_MUL 0x0514
+#define R600_AUDIO_PLL1_DIV 0x0518
+#define R600_AUDIO_PLL2_MUL 0x0524
+#define R600_AUDIO_PLL2_DIV 0x0528
+#define R600_AUDIO_CLK_SRCSEL 0x0534
/* Audio general */
-#define R600_AUDIO_ENABLE 0x7300
-#define R600_AUDIO_TIMING 0x7344
+#define R600_AUDIO_ENABLE 0x7300
+#define R600_AUDIO_TIMING 0x7344
/* Audio params */
-#define R600_AUDIO_VENDOR_ID 0x7380
-#define R600_AUDIO_REVISION_ID 0x7384
-#define R600_AUDIO_ROOT_NODE_COUNT 0x7388
-#define R600_AUDIO_NID1_NODE_COUNT 0x738c
-#define R600_AUDIO_NID1_TYPE 0x7390
-#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
-#define R600_AUDIO_SUPPORTED_CODEC 0x7398
-#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
-#define R600_AUDIO_NID2_CAPS 0x73a0
-#define R600_AUDIO_NID3_CAPS 0x73a4
-#define R600_AUDIO_NID3_PIN_CAPS 0x73a8
+#define R600_AUDIO_VENDOR_ID 0x7380
+#define R600_AUDIO_REVISION_ID 0x7384
+#define R600_AUDIO_ROOT_NODE_COUNT 0x7388
+#define R600_AUDIO_NID1_NODE_COUNT 0x738c
+#define R600_AUDIO_NID1_TYPE 0x7390
+#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
+#define R600_AUDIO_SUPPORTED_CODEC 0x7398
+#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
+#define R600_AUDIO_NID2_CAPS 0x73a0
+#define R600_AUDIO_NID3_CAPS 0x73a4
+#define R600_AUDIO_NID3_PIN_CAPS 0x73a8
/* Audio conn list */
-#define R600_AUDIO_CONN_LIST_LEN 0x73ac
-#define R600_AUDIO_CONN_LIST 0x73b0
+#define R600_AUDIO_CONN_LIST_LEN 0x73ac
+#define R600_AUDIO_CONN_LIST 0x73b0
/* Audio verbs */
-#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
-#define R600_AUDIO_PLAYING 0x73c4
-#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
-#define R600_AUDIO_CONFIG_DEFAULT 0x73cc
-#define R600_AUDIO_PIN_SENSE 0x73d0
-#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
-#define R600_AUDIO_STATUS_BITS 0x73d8
+#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
+#define R600_AUDIO_PLAYING 0x73c4
+#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
+#define R600_AUDIO_CONFIG_DEFAULT 0x73cc
+#define R600_AUDIO_PIN_SENSE 0x73d0
+#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
+#define R600_AUDIO_STATUS_BITS 0x73d8
/* HDMI base register addresses */
-#define R600_HDMI_BLOCK1 0x7400
-#define R600_HDMI_BLOCK2 0x7700
-#define R600_HDMI_BLOCK3 0x7800
+#define R600_HDMI_BLOCK1 0x7400
+#define R600_HDMI_BLOCK2 0x7700
+#define R600_HDMI_BLOCK3 0x7800
/* HDMI registers */
-#define R600_HDMI_ENABLE 0x00
-#define R600_HDMI_STATUS 0x04
-# define R600_HDMI_INT_PENDING (1 << 29)
-#define R600_HDMI_CNTL 0x08
-# define R600_HDMI_INT_EN (1 << 28)
-# define R600_HDMI_INT_ACK (1 << 29)
-#define R600_HDMI_UNKNOWN_0 0x0C
-#define R600_HDMI_AUDIOCNTL 0x10
-#define R600_HDMI_VIDEOCNTL 0x14
-#define R600_HDMI_VERSION 0x18
-#define R600_HDMI_UNKNOWN_1 0x28
-#define R600_HDMI_VIDEOINFOFRAME_0 0x54
-#define R600_HDMI_VIDEOINFOFRAME_1 0x58
-#define R600_HDMI_VIDEOINFOFRAME_2 0x5c
-#define R600_HDMI_VIDEOINFOFRAME_3 0x60
-#define R600_HDMI_32kHz_CTS 0xac
-#define R600_HDMI_32kHz_N 0xb0
-#define R600_HDMI_44_1kHz_CTS 0xb4
-#define R600_HDMI_44_1kHz_N 0xb8
-#define R600_HDMI_48kHz_CTS 0xbc
-#define R600_HDMI_48kHz_N 0xc0
-#define R600_HDMI_AUDIOINFOFRAME_0 0xcc
-#define R600_HDMI_AUDIOINFOFRAME_1 0xd0
-#define R600_HDMI_IEC60958_1 0xd4
-#define R600_HDMI_IEC60958_2 0xd8
-#define R600_HDMI_UNKNOWN_2 0xdc
-#define R600_HDMI_AUDIO_DEBUG_0 0xe0
-#define R600_HDMI_AUDIO_DEBUG_1 0xe4
-#define R600_HDMI_AUDIO_DEBUG_2 0xe8
-#define R600_HDMI_AUDIO_DEBUG_3 0xec
+#define R600_HDMI_ENABLE 0x00
+#define R600_HDMI_STATUS 0x04
+#define R600_HDMI_INT_PENDING (1 << 29)
+#define R600_HDMI_CNTL 0x08
+#define R600_HDMI_INT_EN (1 <<
28)
+#define R600_HDMI_INT_ACK (1 <<
29)
+#define R600_HDMI_UNKNOWN_0 0x0C
+#define R600_HDMI_AUDIOCNTL 0x10
+#define R600_HDMI_VIDEOCNTL 0x14
+#define R600_HDMI_VERSION 0x18
+#define R600_HDMI_UNKNOWN_1 0x28
+#define R600_HDMI_VIDEOINFOFRAME_0 0x54
+#define R600_HDMI_VIDEOINFOFRAME_1 0x58
+#define R600_HDMI_VIDEOINFOFRAME_2 0x5c
+#define R600_HDMI_VIDEOINFOFRAME_3 0x60
+#define R600_HDMI_32kHz_CTS 0xac
+#define R600_HDMI_32kHz_N 0xb0
+#define R600_HDMI_44_1kHz_CTS 0xb4
+#define R600_HDMI_44_1kHz_N 0xb8
+#define R600_HDMI_48kHz_CTS 0xbc
+#define R600_HDMI_48kHz_N 0xc0
+#define R600_HDMI_AUDIOINFOFRAME_0 0xcc
+#define R600_HDMI_AUDIOINFOFRAME_1 0xd0
+#define R600_HDMI_IEC60958_1 0xd4
+#define R600_HDMI_IEC60958_2 0xd8
+#define R600_HDMI_UNKNOWN_2 0xdc
+#define R600_HDMI_AUDIO_DEBUG_0 0xe0
+#define R600_HDMI_AUDIO_DEBUG_1 0xe4
+#define R600_HDMI_AUDIO_DEBUG_2 0xe8
+#define R600_HDMI_AUDIO_DEBUG_3 0xec
/* HDMI additional config base register addresses */
-#define R600_HDMI_CONFIG1 0x7600
-#define R600_HDMI_CONFIG2 0x7a00
+#define R600_HDMI_CONFIG1 0x7600
+#define R600_HDMI_CONFIG2 0x7a00
/* Thermal information */
-#define R600_CG_THERMAL_STATUS 0x7F4
-#define R600_ASIC_T(x) ((x) << 0)
-#define R600_ASIC_T_MASK 0x1FF
-#define R600_ASIC_T_SHIFT 0
+#define R600_CG_THERMAL_STATUS 0x7F4
+#define R600_ASIC_T(x) ((x) <<
0)
+#define R600_ASIC_T_MASK 0x1FF
+#define R600_ASIC_T_SHIFT 0
+
-#endif
+#endif /* __R600_REG_H__ */
\ No newline at end of file
diff --git a/headers/private/graphics/radeon_hd/r700_reg.h
b/headers/private/graphics/radeon_hd/r700_reg.h
index 2e014df..39ecf49 100644
--- a/headers/private/graphics/radeon_hd/r700_reg.h
+++ b/headers/private/graphics/radeon_hd/r700_reg.h
@@ -24,191 +24,189 @@
* Alex Deucher
* Jerome Glisse
*/
-#ifndef RV770_H
-#define RV770_H
+#ifndef R700_H
+#define R700_H
-#define R7XX_MAX_SH_GPRS 256
-#define R7XX_MAX_TEMP_GPRS 16
-#define R7XX_MAX_SH_THREADS 256
-#define R7XX_MAX_SH_STACK_ENTRIES 4096
-#define R7XX_MAX_BACKENDS 8
-#define R7XX_MAX_BACKENDS_MASK 0xff
-#define R7XX_MAX_SIMDS 16
-#define R7XX_MAX_SIMDS_MASK 0xffff
-#define R7XX_MAX_PIPES 8
-#define R7XX_MAX_PIPES_MASK 0xff
+#define R700_MAX_SH_GPRS 256
+#define R700_MAX_TEMP_GPRS 16
+#define R700_MAX_SH_THREADS 256
+#define R700_MAX_SH_STACK_ENTRIES 4096
+#define R700_MAX_BACKENDS 8
+#define R700_MAX_BACKENDS_MASK 0xff
+#define R700_MAX_SIMDS 16
+#define R700_MAX_SIMDS_MASK 0xffff
+#define R700_MAX_PIPES 8
+#define R700_MAX_PIPES_MASK 0xff
-#if 0
/* Registers */
-#define CB_COLOR0_BASE 0x28040
-#define CB_COLOR1_BASE 0x28044
-#define CB_COLOR2_BASE 0x28048
-#define CB_COLOR3_BASE 0x2804C
-#define CB_COLOR4_BASE 0x28050
-#define CB_COLOR5_BASE 0x28054
-#define CB_COLOR6_BASE 0x28058
-#define CB_COLOR7_BASE 0x2805C
-#define CB_COLOR7_FRAG 0x280FC
+#define R700_CB_COLOR0_BASE 0x28040
+#define R700_CB_COLOR1_BASE 0x28044
+#define R700_CB_COLOR2_BASE 0x28048
+#define R700_CB_COLOR3_BASE 0x2804C
+#define R700_CB_COLOR4_BASE 0x28050
+#define R700_CB_COLOR5_BASE 0x28054
+#define R700_CB_COLOR6_BASE 0x28058
+#define R700_CB_COLOR7_BASE 0x2805C
+#define R700_CB_COLOR7_FRAG 0x280FC
-#define CC_GC_SHADER_PIPE_CONFIG 0x8950
-#define CC_RB_BACKEND_DISABLE 0x98F4
-#define BACKEND_DISABLE(x) ((x) <<
16)
-#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
+#define R700_CC_GC_SHADER_PIPE_CONFIG 0x8950
+#define R700_CC_RB_BACKEND_DISABLE 0x98F4
+#define R700_BACKEND_DISABLE(x) ((x) << 16)
+#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3F88
-#define CGTS_SYS_TCC_DISABLE 0x3F90
-#define CGTS_TCC_DISABLE 0x9148
-#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
-#define CGTS_USER_TCC_DISABLE 0x914C
+#define R700_CGTS_SYS_TCC_DISABLE 0x3F90
+#define R700_CGTS_TCC_DISABLE 0x9148
+#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3F94
+#define R700_CGTS_USER_TCC_DISABLE 0x914C
-#define CP_ME_CNTL 0x86D8
-#define CP_ME_HALT (1<<28)
-#define CP_PFP_HALT (1<<26)
-#define CP_ME_RAM_DATA 0xC160
-#define CP_ME_RAM_RADDR 0xC158
-#define CP_ME_RAM_WADDR 0xC15C
-#define CP_MEQ_THRESHOLDS 0x8764
-#define STQ_SPLIT(x) ((x) <<
0)
-#define CP_PERFMON_CNTL 0x87FC
-#define CP_PFP_UCODE_ADDR 0xC150
-#define CP_PFP_UCODE_DATA 0xC154
-#define CP_QUEUE_THRESHOLDS 0x8760
-#define ROQ_IB1_START(x) ((x) <<
0)
-#define ROQ_IB2_START(x) ((x) <<
8)
-#define CP_DEBUG 0xC1FC
-#define CP_RB_BASE 0xC100
-#define CP_RB_CNTL 0xC104
-#define RB_BUFSZ(x) ((x) <<
0)
-#define RB_BLKSZ(x) ((x) <<
8)
-#define RB_NO_UPDATE (1 <<
27)
-#define RB_RPTR_WR_ENA (1 <<
31)
-#define BUF_SWAP_32BIT (2 <<
16)
-#define CP_RB_RPTR 0x8700
-#define CP_RB_RPTR_ADDR 0xC10C
-#define CP_RB_RPTR_ADDR_HI 0xC110
-#define CP_RB_RPTR_WR 0xC108
-#define CP_RB_WPTR 0xC114
-#define CP_RB_WPTR_ADDR 0xC118
-#define CP_RB_WPTR_ADDR_HI 0xC11C
-#define CP_RB_WPTR_DELAY 0x8704
-#define CP_SEM_WAIT_TIMER 0x85BC
+#define R700_CP_ME_CNTL 0x86D8
+#define R700_CP_ME_HALT (1<<28)
+#define R700_CP_PFP_HALT (1<<26)
+#define R700_CP_ME_RAM_DATA 0xC160
+#define R700_CP_ME_RAM_RADDR 0xC158
+#define R700_CP_ME_RAM_WADDR 0xC15C
+#define R700_CP_MEQ_THRESHOLDS 0x8764
+#define STQ_SPLIT(x) ((x) << 0)
+#define R700_CP_PERFMON_CNTL 0x87FC
+#define R700_CP_PFP_UCODE_ADDR 0xC150
+#define R700_CP_PFP_UCODE_DATA 0xC154
+#define R700_CP_QUEUE_THRESHOLDS 0x8760
+#define R700_ROQ_IB1_START(x) ((x) << 0)
+#define R700_ROQ_IB2_START(x) ((x) << 8)
+#define R700_CP_DEBUG 0xC1FC
+#define R700_CP_RB_BASE 0xC100
+#define R700_CP_RB_CNTL 0xC104
+#define R700_RB_BUFSZ(x) ((x) << 0)
+#define R700_RB_BLKSZ(x) ((x) << 8)
+#define R700_RB_NO_UPDATE (1 << 27)
+#define R700_RB_RPTR_WR_ENA (1 << 31)
+#define R700_BUF_SWAP_32BIT (2 << 16)
+#define R700_CP_RB_RPTR 0x8700
+#define R700_CP_RB_RPTR_ADDR 0xC10C
+#define R700_CP_RB_RPTR_ADDR_HI 0xC110
+#define R700_CP_RB_RPTR_WR 0xC108
+#define R700_CP_RB_WPTR 0xC114
+#define R700_CP_RB_WPTR_ADDR 0xC118
+#define R700_CP_RB_WPTR_ADDR_HI 0xC11C
+#define R700_CP_RB_WPTR_DELAY 0x8704
+#define R700_CP_SEM_WAIT_TIMER 0x85BC
-#define DB_DEBUG3 0x98B0
-#define DB_CLK_OFF_DELAY(x) ((x) <<
11)
-#define DB_DEBUG4 0x9B8C
-#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
+#define R700_DB_DEBUG3 0x98B0
+#define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
+#define R700_DB_DEBUG 0x9B8C
+#define R700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
-#define DCP_TILING_CONFIG 0x6CA0
-#define PIPE_TILING(x) ((x) <<
1)
-#define BANK_TILING(x) ((x) << 4)
-#define GROUP_SIZE(x) ((x) <<
6)
-#define ROW_TILING(x) ((x) <<
8)
-#define BANK_SWAPS(x) ((x) <<
11)
-#define SAMPLE_SPLIT(x) ((x) <<
14)
-#define BACKEND_MAP(x) ((x) <<
16)
+#define R700_DCP_TILING_CONFIG 0x6CA0
+#define R700_PIPE_TILING(x) ((x) << 1)
+#define R700_BANK_TILING(x) ((x) << 4)
+#define R700_GROUP_SIZE(x) ((x) << 6)
+#define R700_ROW_TILING(x) ((x) << 8)
+#define R700_BANK_SWAPS(x) ((x) << 11)
+#define R700_SAMPLE_SPLIT(x) ((x) << 14)
+#define R700_BACKEND_MAP(x) ((x) << 16)
-#define GB_TILING_CONFIG 0x98F0
+#define R700_GB_TILING_CONFIG 0x98F0
-#define GC_USER_SHADER_PIPE_CONFIG 0x8954
-#define INACTIVE_QD_PIPES(x) ((x) <<
8)
-#define INACTIVE_QD_PIPES_MASK
0x0000FF00
-#define INACTIVE_SIMDS(x) ((x) <<
16)
-#define INACTIVE_SIMDS_MASK
0x00FF0000
+#define R700_GC_USER_SHADER_PIPE_CONFIG 0x8954
+#define R700_INACTIVE_QD_PIPES(x) ((x) << 8)
+#define R700_INACTIVE_QD_PIPES_MASK 0x0000FF00
+#define R700_INACTIVE_SIMDS(x) ((x) << 16)
+#define R700_INACTIVE_SIMDS_MASK 0x00FF0000
-#define GRBM_CNTL 0x8000
-#define GRBM_READ_TIMEOUT(x) ((x) <<
0)
-#define GRBM_SOFT_RESET 0x8020
-#define SOFT_RESET_CP (1<<0)
-#define GRBM_STATUS 0x8010
-#define CMDFIFO_AVAIL_MASK
0x0000000F
-#define GUI_ACTIVE (1<<31)
-#define GRBM_STATUS2 0x8014
-#endif
+#define R700_GRBM_CNTL 0x8000
+#define R700_GRBM_READ_TIMEOUT(x) ((x) << 0)
+#define R700_GRBM_SOFT_RESET 0x8020
+#define R700_SOFT_RESET_CP (1<<0)
+#define R700_GRBM_STATUS 0x8010
+#define R700_CMDFIFO_AVAIL_MASK 0x0000000F
+#define R700_GUI_ACTIVE (1<<31)
+#define R700_GRBM_STATUS2 0x8014
-#define R700_CG_MULT_THERMAL_STATUS 0x740
-#define R700_ASIC_T(x) ((x) << 16)
-#define R700_ASIC_T_MASK 0x3FF0000
-#define R700_ASIC_T_SHIFT 16
+#define R700_CG_MULT_THERMAL_STATUS 0x740
+#define R700_ASIC_T(x) ((x) << 16)
+#define R700_ASIC_T_MASK 0x3FF0000
+#define R700_ASIC_T_SHIFT 16
-#define HDP_HOST_PATH_CNTL 0x2C00
-#define HDP_NONSURFACE_BASE 0x2C04
-#define HDP_NONSURFACE_INFO 0x2C08
-#define HDP_NONSURFACE_SIZE 0x2C0C
-#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
-#define HDP_TILING_CONFIG 0x2F3C
-#define HDP_DEBUG1 0x2F34
+#define R700_HDP_HOST_PATH_CNTL 0x2C00
+#define R700_HDP_NONSURFACE_BASE 0x2C04
+#define R700_HDP_NONSURFACE_INFO 0x2C08
+#define R700_HDP_NONSURFACE_SIZE 0x2C0C
+#define R700_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+#define R700_HDP_TILING_CONFIG 0x2F3C
+#define R700_HDP_DEBUG1 0x2F34
#define R700_MC_SHARED_CHMAP 0x2004
-#define NOOFCHAN_SHIFT 12
-#define NOOFCHAN_MASK
0x00003000
+#define R700_NOOFCHAN_SHIFT 12
+#define R700_NOOFCHAN_MASK
0x00003000
#define R700_MC_SHARED_CHREMAP 0x2008
#define R700_MC_ARB_RAMCFG 0x2760
-#define NOOFBANK_SHIFT 0
-#define NOOFBANK_MASK
0x00000003
-#define NOOFRANK_SHIFT 2
-#define NOOFRANK_MASK
0x00000004
-#define NOOFROWS_SHIFT 3
-#define NOOFROWS_MASK
0x00000038
-#define NOOFCOLS_SHIFT 6
-#define NOOFCOLS_MASK
0x000000C0
-#define CHANSIZE_SHIFT 8
-#define CHANSIZE_MASK
0x00000100
-#define BURSTLENGTH_SHIFT 9
-#define BURSTLENGTH_MASK
0x00000200
-#define CHANSIZE_OVERRIDE (1 <<
11)
+#define R700_NOOFBANK_SHIFT 0
+#define R700_NOOFBANK_MASK
0x00000003
+#define R700_NOOFRANK_SHIFT 2
+#define R700_NOOFRANK_MASK
0x00000004
+#define R700_NOOFROWS_SHIFT 3
+#define R700_NOOFROWS_MASK
0x00000038
+#define R700_NOOFCOLS_SHIFT 6
+#define R700_NOOFCOLS_MASK
0x000000C0
+#define R700_CHANSIZE_SHIFT 8
+#define R700_CHANSIZE_MASK
0x00000100
+#define R700_BURSTLENGTH_SHIFT 9
+#define R700_BURSTLENGTH_MASK 0x00000200
+#define R700_CHANSIZE_OVERRIDE (1 << 11)
#define R700_MC_VM_AGP_TOP 0x2028
#define R700_MC_VM_AGP_BOT 0x202C
#define R700_MC_VM_AGP_BASE 0x2030
#define R700_MC_VM_FB_LOCATION 0x2024
-#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
-#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
-#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223C
-#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
-#define ENABLE_L1_TLB (1 << 0)
-#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
-#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
-#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
-#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
-#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
-#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
-#define EFFECTIVE_L1_TLB_SIZE(x)
((x)<<15)
-#define EFFECTIVE_L1_QUEUE_SIZE(x)
((x)<<18)
+#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
+#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
+#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223C
+#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
+#define R700_ENABLE_L1_TLB
(1 << 0)
+#define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
+#define R700_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
+#define R700_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
+#define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
+#define R700_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
+#define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
+#define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
+#define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265C
-#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
-#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
-#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
+#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
+#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
+#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
-#define PA_CL_ENHANCE 0x8A14
-#define CLIP_VTX_REORDER_ENA (1 << 0)
-#define NUM_CLIP_SEQ(x) ((x) <<
1)
-#define PA_SC_AA_CONFIG 0x28C04
-#define PA_SC_CLIPRECT_RULE 0x2820C
-#define PA_SC_EDGERULE 0x28230
-#define PA_SC_FIFO_SIZE 0x8BCC
-#define SC_PRIM_FIFO_SIZE(x) ((x) <<
0)
-#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) <<
12)
-#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
-#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
-#define FORCE_EOV_MAX_REZ_CNT(x)
((x)<<16)
-#define PA_SC_LINE_STIPPLE 0x28A0C
-#define PA_SC_LINE_STIPPLE_STATE 0x8B10
-#define PA_SC_MODE_CNTL 0x28A4C
-#define PA_SC_MULTI_CHIP_CNTL 0x8B20
-#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) <<
20)
+#define R700_PA_CL_ENHANCE
0x8A14
+#define R700_CLIP_VTX_REORDER_ENA (1 << 0)
+#define R700_NUM_CLIP_SEQ(x) ((x) <<
1)
+#define R700_PA_SC_AA_CONFIG 0x28C04
+#define R700_PA_SC_CLIPRECT_RULE 0x2820C
+#define R700_PA_SC_EDGERULE
0x28230
+#define R700_PA_SC_FIFO_SIZE 0x8BCC
+#define R700_SC_PRIM_FIFO_SIZE(x) ((x) <<
0)
+#define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
+#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
+#define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
+#define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
+#define R700_PA_SC_LINE_STIPPLE 0x28A0C
+#define R700_PA_SC_LINE_STIPPLE_STATE 0x8B10
+#define R700_PA_SC_MODE_CNTL 0x28A4C
+#define R700_PA_SC_MULTI_CHIP_CNTL 0x8B20
+#define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
-#define R700_SCRATCH_REG0 0x8500
-#define R700_SCRATCH_REG1 0x8504
-#define R700_SCRATCH_REG2 0x8508
-#define R700_SCRATCH_REG3 0x850C
-#define R700_SCRATCH_REG4 0x8510
-#define R700_SCRATCH_REG5 0x8514
-#define R700_SCRATCH_REG6 0x8518
-#define R700_SCRATCH_REG7 0x851C
-#define R700_SCRATCH_UMSK 0x8540
-#define R700_SCRATCH_ADDR 0x8544
+#define R700_SCRATCH_REG0
0x8500
+#define R700_SCRATCH_REG1
0x8504
+#define R700_SCRATCH_REG2
0x8508
+#define R700_SCRATCH_REG3
0x850C
+#define R700_SCRATCH_REG4
0x8510
+#define R700_SCRATCH_REG5
0x8514
+#define R700_SCRATCH_REG6
0x8518
+#define R700_SCRATCH_REG7
0x851C
+#define R700_SCRATCH_UMSK
0x8540
+#define R700_SCRATCH_ADDR
0x8544
#if 0
#define SMX_DC_CTL0 0xA020
@@ -358,49 +356,50 @@
#define SRBM_STATUS 0x0E50
#endif
-#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
-#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
-#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
-#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
-#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
-#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
+#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
+#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
+#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
+#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
+#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
+#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
/* PCIE link stuff */
-#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
-#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
-# define LC_LINK_WIDTH_SHIFT 0
-# define LC_LINK_WIDTH_MASK 0x7
-# define LC_LINK_WIDTH_X0 0
-# define LC_LINK_WIDTH_X1 1
-# define LC_LINK_WIDTH_X2 2
-# define LC_LINK_WIDTH_X4 3
-# define LC_LINK_WIDTH_X8 4
-# define LC_LINK_WIDTH_X16 6
-# define LC_LINK_WIDTH_RD_SHIFT 4
-# define LC_LINK_WIDTH_RD_MASK 0x70
-# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
-# define LC_RECONFIG_NOW (1 << 8)
-# define LC_RENEGOTIATION_SUPPORT (1 << 9)
-# define LC_RENEGOTIATE_EN (1 << 10)
-# define LC_SHORT_RECONFIG_EN (1 << 11)
-# define LC_UPCONFIGURE_SUPPORT (1 << 12)
-# define LC_UPCONFIGURE_DIS (1 << 13)
-#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
-# define LC_GEN2_EN_STRAP (1 << 0)
-# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
-# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
-# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
-# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
-# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
-# define LC_CURRENT_DATA_RATE (1 << 11)
-# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
-# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
-# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
-# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
-#define MM_CFGREGS_CNTL 0x544c
-# define MM_WR_TO_CFG_EN (1 << 3)
-#define LINK_CNTL2 0x88 /* F0 */
-# define TARGET_LINK_SPEED_MASK (0xf << 0)
-# define SELECTABLE_DEEMPHASIS (1 << 6)
+#define R700_PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P
*/
+#define R700_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
+#define R700_LC_LINK_WIDTH_SHIFT 0
+#define R700_LC_LINK_WIDTH_MASK 0x7
+#define R700_LC_LINK_WIDTH_X0 0
+#define R700_LC_LINK_WIDTH_X1 1
+#define R700_LC_LINK_WIDTH_X2 2
+#define R700_LC_LINK_WIDTH_X4 3
+#define R700_LC_LINK_WIDTH_X8 4
+#define R700_LC_LINK_WIDTH_X16 6
+#define R700_LC_LINK_WIDTH_RD_SHIFT 4
+#define R700_LC_LINK_WIDTH_RD_MASK 0x70
+#define R700_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
+#define R700_LC_RECONFIG_NOW (1 << 8)
+#define R700_LC_RENEGOTIATION_SUPPORT (1 << 9)
+#define R700_LC_RENEGOTIATE_EN (1 << 10)
+#define R700_LC_SHORT_RECONFIG_EN (1 << 11)
+#define R700_LC_UPCONFIGURE_SUPPORT (1 << 12)
+#define R700_LC_UPCONFIGURE_DIS (1 << 13)
+#define R700_PCIE_LC_SPEED_CNTL 0xa4 /*
PCIE_P */
+#define R700_LC_GEN2_EN_STRAP (1 << 0)
+#define R700_LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
+#define R700_LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
+#define R700_LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
+#define R700_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
+#define R700_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
+#define R700_LC_CURRENT_DATA_RATE (1 << 11)
+#define R700_LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
+#define R700_LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
+#define R700_LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
+#define R700_LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
+#define R700_MM_CFGREGS_CNTL 0x544c
+#define R700_MM_WR_TO_CFG_EN (1 << 3)
+#define R700_LINK_CNTL2
0x88 /* F0 */
+#define R700_TARGET_LINK_SPEED_MASK (0xf << 0)
+#define R700_SELECTABLE_DEEMPHASIS (1 << 6)
-#endif
+
+#endif /* R700_H */
\ No newline at end of file
diff --git a/src/add-ons/accelerants/radeon_hd/display.cpp
b/src/add-ons/accelerants/radeon_hd/display.cpp
index 47e8a32..a175adf 100644
--- a/src/add-ons/accelerants/radeon_hd/display.cpp
+++ b/src/add-ons/accelerants/radeon_hd/display.cpp
@@ -116,13 +116,13 @@ init_registers(register_info* regs, uint8 crtcID)
offset = R600_CRTC0_REGISTER_OFFSET;
regs->vgaControl = AVIVO_D1VGA_CONTROL;
regs->grphPrimarySurfaceAddrHigh
- = D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
+ =
R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
break;
case 1:
offset = R600_CRTC1_REGISTER_OFFSET;
regs->vgaControl = AVIVO_D2VGA_CONTROL;
regs->grphPrimarySurfaceAddrHigh
- = D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
+ =
R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
break;
default:
ERROR("%s: Unknown CRTC %" B_PRIu32 "\n",
@@ -137,9 +137,9 @@ init_registers(register_info* regs, uint8 crtcID)
regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset;
regs->grphPrimarySurfaceAddr
- = D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
+ = R700_D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
regs->grphSecondarySurfaceAddr
- = D1GRPH_SECONDARY_SURFACE_ADDRESS + offset;
+ = R700_D1GRPH_SECONDARY_SURFACE_ADDRESS + offset;
regs->grphPitch = AVIVO_D1GRPH_PITCH + offset;
regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X +
offset;
diff --git a/src/add-ons/accelerants/radeon_hd/gpu.cpp
b/src/add-ons/accelerants/radeon_hd/gpu.cpp
index 14afe5f..ecd60a1 100644
--- a/src/add-ons/accelerants/radeon_hd/gpu.cpp
+++ b/src/add-ons/accelerants/radeon_hd/gpu.cpp
@@ -262,7 +262,7 @@ radeon_gpu_mc_setup_r600()
Write32(OUT, (0x2c20 + j), 0x00000000);
Write32(OUT, (0x2c24 + j), 0x00000000);
}
- Write32(OUT, HDP_REG_COHERENCY_FLUSH_CNTL, 0);
+ Write32(OUT, R600_HDP_REG_COHERENCY_FLUSH_CNTL, 0);
// idle the memory controller
struct gpu_state gpuState;
@@ -282,9 +282,9 @@ radeon_gpu_mc_setup_r600()
tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF);
Write32(OUT, R600_MC_VM_FB_LOCATION, tmp);
- Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
- Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7));
- Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
+ Write32(OUT, R600_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
+ Write32(OUT, R600_HDP_NONSURFACE_INFO, (2 << 7));
+ Write32(OUT, R600_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
// is AGP?
// Write32(OUT, R600_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 22);
@@ -322,7 +322,7 @@ radeon_gpu_mc_setup_r700()
}
// On r7xx read from HDP_DEBUG1 vs write HDP_REG_COHERENCY_FLUSH_CNTL
- Read32(OUT, HDP_DEBUG1);
+ Read32(OUT, R700_HDP_DEBUG1);
// idle the memory controller
struct gpu_state gpuState;
@@ -344,9 +344,9 @@ radeon_gpu_mc_setup_r700()
tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF);
Write32(OUT, R700_MC_VM_FB_LOCATION, tmp);
- Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
- Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7));
- Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
+ Write32(OUT, R700_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
+ Write32(OUT, R700_HDP_NONSURFACE_INFO, (2 << 7));
+ Write32(OUT, R700_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
// is AGP?
// Write32(OUT, R700_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 22);
@@ -382,7 +382,7 @@ radeon_gpu_mc_setup_evergreen()
Write32(OUT, (0x2c20 + j), 0x00000000);
Write32(OUT, (0x2c24 + j), 0x00000000);
}
- Write32(OUT, HDP_REG_COHERENCY_FLUSH_CNTL, 0);
+ Write32(OUT, EVERGREEN_HDP_REG_COHERENCY_FLUSH_CNTL, 0);
// idle the memory controller
struct gpu_state gpuState;
@@ -415,9 +415,9 @@ radeon_gpu_mc_setup_evergreen()
tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF);
Write32(OUT, EVERGREEN_MC_VM_FB_LOCATION, tmp);
- Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
- Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
- Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
+ Write32(OUT, EVERGREEN_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
+ Write32(OUT, EVERGREEN_HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
+ Write32(OUT, EVERGREEN_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
// is AGP?
// Write32(OUT, EVERGREEN_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 16);
diff --git a/src/add-ons/accelerants/radeon_hd/gpu.h
b/src/add-ons/accelerants/radeon_hd/gpu.h
index 7377219..d9586c9 100644
--- a/src/add-ons/accelerants/radeon_hd/gpu.h
+++ b/src/add-ons/accelerants/radeon_hd/gpu.h
@@ -14,12 +14,6 @@
#include <video_configuration.h>
-#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
-#define HDP_NONSURFACE_BASE 0x2C04
-#define HDP_NONSURFACE_INFO 0x2C08
-#define HDP_NONSURFACE_SIZE 0x2C0C
-
-
// GPU Control registers. These are combined as
// the registers exist on all models, some flags
// are different though and are commented as such
############################################################################
Revision: hrev44441
Commit: 93aac98d0a9b8ce27f94eb449cfc742446a50274
URL: http://cgit.haiku-os.org/haiku/commit/?id=93aac98
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Mon Jul 30 20:57:00 2012 UTC
radeon_hd: r5xx to Avivo define cleanup
* Reorganize and clean up card defines
* Fix define spaces
* Unify card naming
* No (real) functional change
----------------------------------------------------------------------------
diff --git a/headers/private/graphics/radeon_hd/avivo.h
b/headers/private/graphics/radeon_hd/avivo.h
deleted file mode 100644
index bd4dab7..0000000
--- a/headers/private/graphics/radeon_hd/avivo.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright 2009 Advanced Micro Devices, Inc.
- * Copyright 2009 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- * Alex Deucher
- * Jerome Glisse
- */
-#ifndef AVIVO_H
-#define AVIVO_H
-
-
-#define D1CRTC_CONTROL
0x6080
-#define CRTC_EN
(1 << 0)
-#define D1CRTC_STATUS
0x609c
-#define D1CRTC_UPDATE_LOCK
0x60E8
-#define D1GRPH_SWAP_CNTL 0x610C
-#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
-#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
-
-#define D2CRTC_CONTROL
0x6880
-#define D2CRTC_STATUS
0x689c
-#define D2CRTC_UPDATE_LOCK
0x68E8
-#define D2GRPH_SWAP_CNTL 0x690C
-#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
-#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
-
-#define D1VGA_CONTROL
0x0330
-#define DVGA_CONTROL_MODE_ENABLE (1 << 0)
-#define DVGA_CONTROL_TIMING_SELECT (1 << 8)
-#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
-#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
-#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
-#define DVGA_CONTROL_ROTATE
(1 << 24)
-#define D2VGA_CONTROL 0x0338
-
-#define VGA_HDP_CONTROL
0x328
-#define VGA_MEM_PAGE_SELECT_EN (1 << 0)
-#define VGA_MEMORY_DISABLE
(1 << 4)
-#define VGA_RBBM_LOCK_DISABLE (1 << 8)
-#define VGA_SOFT_RESET
(1 << 16)
-#define VGA_MEMORY_BASE_ADDRESS 0x0310
-#define VGA_RENDER_CONTROL
0x0300
-#define VGA_VSTATUS_CNTL_MASK
0x00030000
-
-
-#endif
diff --git a/headers/private/graphics/radeon_hd/avivo_reg.h
b/headers/private/graphics/radeon_hd/avivo_reg.h
new file mode 100644
index 0000000..6f1aa24
--- /dev/null
+++ b/headers/private/graphics/radeon_hd/avivo_reg.h
@@ -0,0 +1,561 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ * Alexander von Gluck IV
+ */
+#ifndef AVIVO_H
+#define AVIVO_H
+
+
+#define AVIVO_D1CRTC_UPDATE_LOCK
0x60E8
+#define AVIVO_D1GRPH_SWAP_CNTL 0x610C
+#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
+#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
+
+#define AVIVO_D1VGA_CONTROL
0x0330
+#define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0)
+#define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8)
+#define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
+#define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
+#define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
+#define AVIVO_DVGA_CONTROL_ROTATE
(1 << 24)
+#define AVIVO_D2VGA_CONTROL
0x0338
+
+#define AVIVO_VGA_HDP_CONTROL
0x328
+#define AVIVO_VGA_MEM_PAGE_SELECT_EN (1 << 0)
+#define AVIVO_VGA_MEMORY_DISABLE
(1 << 4)
+#define AVIVO_VGA_RBBM_LOCK_DISABLE
(1 << 8)
+#define AVIVO_VGA_SOFT_RESET
(1 << 16)
+#define AVIVO_VGA_MEMORY_BASE_ADDRESS 0x0310
+#define AVIVO_VGA_RENDER_CONTROL
0x0300
+#define AVIVO_VGA_VSTATUS_CNTL_MASK
(3 << 16)
+
+
+#define AVIVO_MC_INDEX
0x0070
+#define AVIVO_MC_DATA
0x0074
+
+#define AVIVO_CP_DYN_CNTL
0x000f /* PLL */
+#define AVIVO_CP_FORCEON
(1 << 0)
+#define AVIVO_E2_DYN_CNTL
0x0011 /* PLL */
+#define AVIVO_E2_FORCEON
(1 << 0)
+#define AVIVO_IDCT_DYN_CNTL
0x0013 /* PLL */
+#define AVIVO_IDCT_FORCEON
(1 << 0)
+
+#define AVIVO_HDP_FB_LOCATION 0x134
+
+#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
+#define AVIVO_EXT1_PPLL_REF_DIV
0x404
+#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
+#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
+
+#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
+#define AVIVO_EXT2_PPLL_REF_DIV
0x414
+#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
+#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
+
+#define AVIVO_EXT1_PPLL_FB_DIV 0x430
+#define AVIVO_EXT2_PPLL_FB_DIV 0x434
+
+#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
+#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
+
+#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
+#define AVIVO_EXT2_PPLL_POST_DIV 0x444
+
+#define AVIVO_EXT1_PPLL_CNTL 0x448
+#define AVIVO_EXT2_PPLL_CNTL 0x44c
+
+#define AVIVO_P1PLL_CNTL
0x450
+#define AVIVO_P2PLL_CNTL
0x454
+#define AVIVO_P1PLL_INT_SS_CNTL
0x458
+#define AVIVO_P2PLL_INT_SS_CNTL
0x45c
+#define AVIVO_P1PLL_TMDSA_CNTL 0x460
+#define AVIVO_P2PLL_LVTMA_CNTL 0x464
+
+#define AVIVO_PCLK_CRTC1_CNTL 0x480
+#define AVIVO_PCLK_CRTC2_CNTL 0x484
+
+/* first crtc */
+#define AVIVO_D1CRTC_H_TOTAL 0x6000
+#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
+#define AVIVO_D1CRTC_H_SYNC_A 0x6008
+#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600C
+#define AVIVO_D1CRTC_H_SYNC_B 0x6010
+#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
+
+#define AVIVO_D1CRTC_V_TOTAL 0x6020
+#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
+#define AVIVO_D1CRTC_V_SYNC_A 0x6028
+#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602C
+#define AVIVO_D1CRTC_V_SYNC_B 0x6030
+#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
+
+#define AVIVO_D1CRTC_CONTROL 0x6080
+#define AVIVO_CRTC_EN
(1 << 0)
+#define AVIVO_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
+#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
+#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
+#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608C
+#define AVIVO_D1CRTC_STATUS
0x609C
+#define AVIVO_D1CRTC_STATUS_POSITION 0x60A0
+#define AVIVO_D1CRTC_FRAME_COUNT 0x60A4
+#define AVIVO_D1CRTC_STEREO_CONTROL 0x60C4
+
+#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
+
+/* master controls */
+#define AVIVO_DC_CRTC_MASTER_EN
0x60f8
+#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
+
+#define AVIVO_D1GRPH_ENABLE
0x6100
+#define AVIVO_D1GRPH_CONTROL 0x6104
+#define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0)
+#define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0)
+#define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0)
+#define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0)
+
+#define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8)
+
+#define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8)
+#define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8)
+#define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8)
+#define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8)
+#define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8)
+
+#define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8)
+#define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8)
+#define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8)
+#define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8)
+
+
+#define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8)
+
+#define AVIVO_D1GRPH_SWAP_RB (1 <<
16)
+#define AVIVO_D1GRPH_TILED
(1 << 20)
+#define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
+
+#define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
+#define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
+#define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)
+#define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20)
+
+/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
+ * block and vice versa. This applies to GRPH, CUR, etc.
+ */
+#define AVIVO_D1GRPH_LUT_SEL
0x6108
+#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
+#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
+#define AVIVO_D1GRPH_PITCH
0x6120
+#define AVIVO_D1GRPH_SURFACE_OFFSET_X
0x6124
+#define AVIVO_D1GRPH_SURFACE_OFFSET_Y
0x6128
+#define AVIVO_D1GRPH_X_START
0x612c
+#define AVIVO_D1GRPH_Y_START
0x6130
+#define AVIVO_D1GRPH_X_END
0x6134
+#define AVIVO_D1GRPH_Y_END
0x6138
+#define AVIVO_D1GRPH_UPDATE
0x6144
+#define AVIVO_D1GRPH_SURFACE_UPDATE_PENDING
(1 << 2)
+#define AVIVO_D1GRPH_UPDATE_LOCK
(1 << 16)
+#define AVIVO_D1GRPH_FLIP_CONTROL
0x6148
+#define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
+
+#define AVIVO_D1CUR_CONTROL
0x6400
+#define AVIVO_D1CURSOR_EN
(1 << 0)
+#define AVIVO_D1CURSOR_MODE_SHIFT
8
+#define AVIVO_D1CURSOR_MODE_MASK
(3 << 8)
+#define AVIVO_D1CURSOR_MODE_24BPP
2
+#define AVIVO_D1CUR_SURFACE_ADDRESS
0x6408
+#define R700_D1CUR_SURFACE_ADDRESS_HIGH
0x6c0c
+#define R700_D2CUR_SURFACE_ADDRESS_HIGH
0x640c
+#define AVIVO_D1CUR_SIZE
0x6410
+#define AVIVO_D1CUR_POSITION
0x6414
+#define AVIVO_D1CUR_HOT_SPOT
0x6418
+#define AVIVO_D1CUR_UPDATE
0x6424
+#define AVIVO_D1CURSOR_UPDATE_LOCK
(1 << 16)
+
+#define AVIVO_DC_LUT_RW_SELECT
0x6480
+#define AVIVO_DC_LUT_RW_MODE
0x6484
+#define AVIVO_DC_LUT_RW_INDEX
0x6488
+#define AVIVO_DC_LUT_SEQ_COLOR
0x648c
+#define AVIVO_DC_LUT_PWL_DATA
0x6490
+#define AVIVO_DC_LUT_30_COLOR
0x6494
+#define AVIVO_DC_LUT_READ_PIPE_SELECT
0x6498
+#define AVIVO_DC_LUT_WRITE_EN_MASK
0x649c
+#define AVIVO_DC_LUT_AUTOFILL
0x64a0
+
+#define AVIVO_DC_LUTA_CONTROL
0x64c0
+#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
0x64c4
+#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
0x64c8
+#define AVIVO_DC_LUTA_BLACK_OFFSET_RED
0x64cc
+#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
0x64d0
+#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
0x64d4
+#define AVIVO_DC_LUTA_WHITE_OFFSET_RED
0x64d8
+
+#define AVIVO_DC_LB_MEMORY_SPLIT
0x6520
+#define AVIVO_DC_LB_MEMORY_SPLIT_MASK
0x3
+#define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
+#define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
+#define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
+#define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY
2
+#define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
+#define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE
(1 << 2)
+#define AVIVO_DC_LB_DISP1_END_ADR_SHIFT
4
+#define AVIVO_DC_LB_DISP1_END_ADR_MASK
0x7ff
+
+#define AVIVO_D1MODE_DATA_FORMAT
0x6528
+#define AVIVO_D1MODE_INTERLEAVE_EN
(1 << 0)
+#define AVIVO_D1MODE_DESKTOP_HEIGHT
0x652C
+#define AVIVO_D1MODE_VBLANK_STATUS
0x6534
+#define AVIVO_VBLANK_ACK
(1 << 4)
+#define AVIVO_D1MODE_VLINE_START_END
0x6538
+#define AVIVO_D1MODE_VLINE_STATUS
0x653c
+#define AVIVO_D1MODE_VLINE_STAT
(1 << 12)
+#define AVIVO_DxMODE_INT_MASK
0x6540
+#define AVIVO_D1MODE_INT_MASK
(1 << 0)
+#define AVIVO_D2MODE_INT_MASK
(1 << 8)
+#define AVIVO_D1MODE_VIEWPORT_START
0x6580
+#define AVIVO_D1MODE_VIEWPORT_SIZE
0x6584
+#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
+#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
+
+#define AVIVO_D1SCL_SCALER_ENABLE
0x6590
+#define AVIVO_D1SCL_SCALER_TAP_CONTROL
0x6594
+#define AVIVO_D1SCL_UPDATE
0x65cc
+#define AVIVO_D1SCL_UPDATE_LOCK
(1 << 16)
+
+/* second crtc */
+#define AVIVO_D2CRTC_H_TOTAL
0x6800
+#define AVIVO_D2CRTC_H_BLANK_START_END
0x6804
+#define AVIVO_D2CRTC_H_SYNC_A
0x6808
+#define AVIVO_D2CRTC_H_SYNC_A_CNTL
0x680c
+#define AVIVO_D2CRTC_H_SYNC_B
0x6810
+#define AVIVO_D2CRTC_H_SYNC_B_CNTL
0x6814
+
+#define AVIVO_D2CRTC_V_TOTAL
0x6820
+#define AVIVO_D2CRTC_V_BLANK_START_END
0x6824
+#define AVIVO_D2CRTC_V_SYNC_A
0x6828
+#define AVIVO_D2CRTC_V_SYNC_A_CNTL
0x682c
+#define AVIVO_D2CRTC_V_SYNC_B
0x6830
+#define AVIVO_D2CRTC_V_SYNC_B_CNTL
0x6834
+
+#define AVIVO_D2CRTC_CONTROL
0x6880
+#define AVIVO_D2CRTC_BLANK_CONTROL
0x6884
+#define AVIVO_D2CRTC_INTERLACE_CONTROL
0x6888
+#define AVIVO_D2CRTC_INTERLACE_STATUS
0x688C
+#define AVIVO_D2CRTC_STATUS
0x689C
+#define AVIVO_D2CRTC_STATUS_POSITION
0x68A0
+#define AVIVO_D2CRTC_FRAME_COUNT
0x68A4
+#define AVIVO_D2CRTC_STEREO_CONTROL
0x68C4
+#define AVIVO_D2CRTC_UPDATE_LOCK
0x68E8
+
+#define AVIVO_D2GRPH_ENABLE
0x6900
+#define AVIVO_D2GRPH_CONTROL
0x6904
+#define AVIVO_D2GRPH_LUT_SEL
0x6908
+#define AVIVO_D2GRPH_SWAP_CNTL
0x690C
+#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
+#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
+#define AVIVO_D2GRPH_PITCH
0x6920
+#define AVIVO_D2GRPH_SURFACE_OFFSET_X
0x6924
+#define AVIVO_D2GRPH_SURFACE_OFFSET_Y
0x6928
+#define AVIVO_D2GRPH_X_START
0x692c
+#define AVIVO_D2GRPH_Y_START
0x6930
+#define AVIVO_D2GRPH_X_END
0x6934
+#define AVIVO_D2GRPH_Y_END
0x6938
+#define AVIVO_D2GRPH_UPDATE
0x6944
+#define AVIVO_D2GRPH_FLIP_CONTROL
0x6948
+
+#define AVIVO_D2CUR_CONTROL
0x6c00
+#define AVIVO_D2CUR_SURFACE_ADDRESS
0x6c08
+#define AVIVO_D2CUR_SIZE
0x6c10
+#define AVIVO_D2CUR_POSITION
0x6c14
+
+#define AVIVO_D2MODE_VBLANK_STATUS
0x6d34
+#define AVIVO_D2MODE_VLINE_START_END
0x6d38
+#define AVIVO_D2MODE_VLINE_STATUS
0x6d3c
+#define AVIVO_D2MODE_VIEWPORT_START
0x6d80
+#define AVIVO_D2MODE_VIEWPORT_SIZE
0x6d84
+#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
+#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
+
+#define AVIVO_D2SCL_SCALER_ENABLE
0x6d90
+#define AVIVO_D2SCL_SCALER_TAP_CONTROL
0x6d94
+
+#define AVIVO_DDIA_BIT_DEPTH_CONTROL
0x7214
+
+#define AVIVO_DACA_ENABLE
0x7800
+#define AVIVO_DAC_ENABLE
(1 << 0)
+#define AVIVO_DACA_SOURCE_SELECT
0x7804
+#define AVIVO_DAC_SOURCE_CRTC1
(0 << 0)
+#define AVIVO_DAC_SOURCE_CRTC2
(1 << 0)
+#define AVIVO_DAC_SOURCE_TV
(2 << 0)
+
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL
0x783c
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
+#define AVIVO_DACA_POWERDOWN
0x7850
+#define AVIVO_DACA_POWERDOWN_POWERDOWN
(1 << 0)
+#define AVIVO_DACA_POWERDOWN_BLUE
(1 << 8)
+#define AVIVO_DACA_POWERDOWN_GREEN
(1 << 16)
+#define AVIVO_DACA_POWERDOWN_RED
(1 << 24)
+
+#define AVIVO_DACB_ENABLE
0x7a00
+#define AVIVO_DACB_SOURCE_SELECT
0x7a04
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL
0x7a3c
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
+#define AVIVO_DACB_POWERDOWN
0x7a50
+#define AVIVO_DACB_POWERDOWN_POWERDOWN
(1 << 0)
+#define AVIVO_DACB_POWERDOWN_BLUE
(1 << 8)
+#define AVIVO_DACB_POWERDOWN_GREEN
(1 << 16)
+#define AVIVO_DACB_POWERDOWN_RED
(1 << 24)
+
+#define AVIVO_TMDSA_CNTL
0x7880
+#define AVIVO_TMDSA_CNTL_ENABLE
(1 << 0)
+#define AVIVO_TMDSA_CNTL_HPD_MASK
(1 << 4)
+#define AVIVO_TMDSA_CNTL_HPD_SELECT
(1 << 8)
+#define AVIVO_TMDSA_CNTL_SYNC_PHASE
(1 << 12)
+#define AVIVO_TMDSA_CNTL_PIXEL_ENCODING
(1 << 16)
+#define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE
(1 << 24)
+#define AVIVO_TMDSA_CNTL_SWAP
(1 << 28)
+#define AVIVO_TMDSA_SOURCE_SELECT
0x7884
+/* 78a8 appears to be some kind of (reasonably tolerant) clock?
+ * 78d0 definitely hits the transmitter, definitely clock. */
+/* MYSTERY1 This appears to control dithering? */
+#define AVIVO_TMDSA_BIT_DEPTH_CONTROL
0x7894
+#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN
(1 << 0)
+#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH
(1 << 4)
+#define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
+#define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 <<
12)
+#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 <<
16)
+#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 <<
20)
+#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL
(1 << 24)
+#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 <<
26)
+#define AVIVO_TMDSA_DCBALANCER_CONTROL
0x78d0
+#define AVIVO_TMDSA_DCBALANCER_CONTROL_EN
(1 << 0)
+#define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN
(1 << 8)
+#define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
+#define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE
(1 << 24)
+#define AVIVO_TMDSA_DATA_SYNCHRONIZATION
0x78d8
+#define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL
(1 << 0)
+#define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG
(1 << 8)
+#define AVIVO_TMDSA_CLOCK_ENABLE
0x7900
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE
0x7904
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE
(1 << 0)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN
(1 << 1)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN
(1 << 2)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN
(1 << 3)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN
(1 << 4)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE
(1 << 8)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN
(1 << 10)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN
(1 << 11)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN
(1 << 12)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 <<
16)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 <<
17)
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 <<
18)
+
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL
0x7910
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE
(1 << 0)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET
(1 << 1)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL
(1 << 4)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP
(1 << 5)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK
(1 << 8)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 <<
13)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK
(1 << 14)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 <<
15)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL
(1 << 28)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 <<
29)
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 <<
31)
+
+#define AVIVO_LVTMA_CNTL
0x7a80
+#define AVIVO_LVTMA_CNTL_ENABLE
(1 << 0)
+#define AVIVO_LVTMA_CNTL_HPD_MASK
(1 << 4)
+#define AVIVO_LVTMA_CNTL_HPD_SELECT
(1 << 8)
+#define AVIVO_LVTMA_CNTL_SYNC_PHASE
(1 << 12)
+#define AVIVO_LVTMA_CNTL_PIXEL_ENCODING
(1 << 16)
+#define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE
(1 << 24)
+#define AVIVO_LVTMA_CNTL_SWAP
(1 << 28)
+#define AVIVO_LVTMA_SOURCE_SELECT
0x7a84
+#define AVIVO_LVTMA_COLOR_FORMAT
0x7a88
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL
0x7a94
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
(1 << 0)
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 <<
12)
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 <<
16)
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 <<
20)
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 <<
24)
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 <<
26)
+
+
+
+#define AVIVO_LVTMA_DCBALANCER_CONTROL
0x7ad0
+#define AVIVO_LVTMA_DCBALANCER_CONTROL_EN
(1 << 0)
+#define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN
(1 << 8)
+#define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
+#define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE
(1 << 24)
+
+#define AVIVO_LVTMA_DATA_SYNCHRONIZATION
0x78d8
+#define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL
(1 << 0)
+#define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG
(1 << 8)
+#define R500_LVTMA_CLOCK_ENABLE
0x7b00
+#define R600_LVTMA_CLOCK_ENABLE
0x7b04
+
+#define R500_LVTMA_TRANSMITTER_ENABLE
0x7b04
+#define R600_LVTMA_TRANSMITTER_ENABLE
0x7b08
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN
(1 << 1)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN
(1 << 2)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN
(1 << 3)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN
(1 << 4)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN
(1 << 5)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN
(1 << 9)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN
(1 << 10)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN
(1 << 11)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN
(1 << 12)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 <<
17)
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 <<
18)
+
+#define R500_LVTMA_TRANSMITTER_CONTROL
0x7b10
+#define R600_LVTMA_TRANSMITTER_CONTROL
0x7b14
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE
(1 << 0)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET
(1 << 1)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL
(1 << 4)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP
(1 << 5)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK
(1 << 8)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 <<
13)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK
(1 << 14)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 <<
15)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL
(1 << 28)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 <<
29)
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 <<
31)
+
+#define R500_LVTMA_PWRSEQ_CNTL
0x7af0
+#define R600_LVTMA_PWRSEQ_CNTL
0x7af4
+#define AVIVO_LVTMA_PWRSEQ_EN
(1 << 0)
+#define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK
(1 << 2)
+#define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK
(1 << 3)
+#define AVIVO_LVTMA_PWRSEQ_TARGET_STATE
(1 << 4)
+#define AVIVO_LVTMA_SYNCEN
(1 << 8)
+#define AVIVO_LVTMA_SYNCEN_OVRD
(1 << 9)
+#define AVIVO_LVTMA_SYNCEN_POL
(1 << 10)
+#define AVIVO_LVTMA_DIGON
(1 << 16)
+#define AVIVO_LVTMA_DIGON_OVRD
(1 << 17)
+#define AVIVO_LVTMA_DIGON_POL
(1 << 18)
+#define AVIVO_LVTMA_BLON
(1 << 24)
+#define AVIVO_LVTMA_BLON_OVRD
(1 << 25)
+#define AVIVO_LVTMA_BLON_POL
(1 << 26)
+
+#define R500_LVTMA_PWRSEQ_STATE
0x7af4
+#define R600_LVTMA_PWRSEQ_STATE
0x7af8
+#define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
+#define AVIVO_LVTMA_PWRSEQ_STATE_DIGON
(1 << 1)
+#define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN
(1 << 2)
+#define AVIVO_LVTMA_PWRSEQ_STATE_BLON
(1 << 3)
+#define AVIVO_LVTMA_PWRSEQ_STATE_DONE
(1 << 4)
+#define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
+
+#define AVIVO_LVDS_BACKLIGHT_CNTL
0x7af8
+#define AVIVO_LVDS_BACKLIGHT_CNTL_EN
(1 << 0)
+#define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK
0x0000ff00
+#define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT
8
+
+#define AVIVO_DVOA_BIT_DEPTH_CONTROL
0x7988
+
+#define AVIVO_DC_GPIO_HPD_A
0x7e94
+#define AVIVO_DC_GPIO_HPD_Y
0x7e9c
+
+#define AVIVO_DC_I2C_STATUS1
0x7d30
+#define AVIVO_DC_I2C_DONE
(1 << 0)
+#define AVIVO_DC_I2C_NACK
(1 << 1)
+#define AVIVO_DC_I2C_HALT
(1 << 2)
+#define AVIVO_DC_I2C_GO
(1 << 3)
+#define AVIVO_DC_I2C_RESET
0x7d34
+#define AVIVO_DC_I2C_SOFT_RESET
(1 << 0)
+#define AVIVO_DC_I2C_ABORT
(1 << 8)
+#define AVIVO_DC_I2C_CONTROL1
0x7d38
+#define AVIVO_DC_I2C_START
(1 << 0)
+#define AVIVO_DC_I2C_STOP
(1 << 1)
+#define AVIVO_DC_I2C_RECEIVE
(1 << 2)
+#define AVIVO_DC_I2C_EN
(1 << 8)
+#define AVIVO_DC_I2C_PIN_SELECT(x)
((x) << 16)
+#define AVIVO_SEL_DDC1
0
+#define AVIVO_SEL_DDC2
1
+#define AVIVO_SEL_DDC3
2
+#define AVIVO_DC_I2C_CONTROL2
0x7d3c
+#define AVIVO_DC_I2C_ADDR_COUNT(x)
((x) << 0)
+#define AVIVO_DC_I2C_DATA_COUNT(x)
((x) << 8)
+#define AVIVO_DC_I2C_CONTROL3
0x7d40
+#define AVIVO_DC_I2C_DATA_DRIVE_EN
(1 << 0)
+#define AVIVO_DC_I2C_DATA_DRIVE_SEL
(1 << 1)
+#define AVIVO_DC_I2C_CLK_DRIVE_EN
(1 << 7)
+#define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x)
((x) << 8)
+#define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x)
((x) << 16)
+#define AVIVO_DC_I2C_TIME_LIMIT(x)
((x) << 24)
+#define AVIVO_DC_I2C_DATA
0x7d44
+#define AVIVO_DC_I2C_INTERRUPT_CONTROL
0x7d48
+#define AVIVO_DC_I2C_INTERRUPT_STATUS
(1 << 0)
+#define AVIVO_DC_I2C_INTERRUPT_AK
(1 << 8)
+#define AVIVO_DC_I2C_INTERRUPT_ENABLE
(1 << 16)
+#define AVIVO_DC_I2C_ARBITRATION
0x7d50
+#define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C
(1 << 0)
+#define AVIVO_DC_I2C_SW_CAN_USE_I2C
(1 << 1)
+#define AVIVO_DC_I2C_SW_DONE_USING_I2C
(1 << 8)
+#define AVIVO_DC_I2C_HW_NEEDS_I2C
(1 << 9)
+#define AVIVO_DC_I2C_ABORT_HDCP_I2C
(1 << 16)
+#define AVIVO_DC_I2C_HW_USING_I2C
(1 << 17)
+
+#define AVIVO_DC_GPIO_DDC1_MASK
0x7e40
+#define AVIVO_DC_GPIO_DDC1_A
0x7e44
+#define AVIVO_DC_GPIO_DDC1_EN
0x7e48
+#define AVIVO_DC_GPIO_DDC1_Y
0x7e4c
+
+#define AVIVO_DC_GPIO_DDC2_MASK
0x7e50
+#define AVIVO_DC_GPIO_DDC2_A
0x7e54
+#define AVIVO_DC_GPIO_DDC2_EN
0x7e58
+#define AVIVO_DC_GPIO_DDC2_Y
0x7e5c
+
+#define AVIVO_DC_GPIO_DDC3_MASK
0x7e60
+#define AVIVO_DC_GPIO_DDC3_A
0x7e64
+#define AVIVO_DC_GPIO_DDC3_EN
0x7e68
+#define AVIVO_DC_GPIO_DDC3_Y
0x7e6c
+
+#define AVIVO_DISP_INTERRUPT_STATUS
0x7edc
+#define AVIVO_D1_VBLANK_INTERRUPT
(1 << 4)
+#define AVIVO_D2_VBLANK_INTERRUPT
(1 << 5)
+
+
+#endif /* AVIVO_H */
\ No newline at end of file
diff --git a/headers/private/graphics/radeon_hd/r500_reg.h
b/headers/private/graphics/radeon_hd/r500_reg.h
index 93afeea..e76eb47 100644
--- a/headers/private/graphics/radeon_hd/r500_reg.h
+++ b/headers/private/graphics/radeon_hd/r500_reg.h
@@ -260,14 +260,11 @@
#define R520_MC_AGP_BASE_2 0x07
-#define AVIVO_MC_INDEX 0x0070
#define R520_MC_STATUS 0x00
#define R520_MC_STATUS_IDLE (1<<1)
#define RV515_MC_STATUS 0x08
#define RV515_MC_STATUS_IDLE (1<<4)
#define RV515_MC_INIT_MISC_LAT_TIMER 0x09
-#define AVIVO_MC_DATA 0x0074
-
#define R520_MC_IND_INDEX 0x70
#define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74
@@ -279,511 +276,5 @@
# define R520_MEM_NUM_CHANNELS_SHIFT 24
# define R520_MC_CHANNEL_SIZE (1 << 23)
-#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */
-# define AVIVO_CP_FORCEON (1 << 0)
-#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */
-# define AVIVO_E2_FORCEON (1 << 0)
-#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */
-# define AVIVO_IDCT_FORCEON (1 << 0)
-
-#define AVIVO_HDP_FB_LOCATION 0x134
-
-#define AVIVO_VGA_RENDER_CONTROL 0x0300
-# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)
-#define AVIVO_D1VGA_CONTROL 0x0330
-# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
-# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
-# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
-# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
-# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
-# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
-#define AVIVO_D2VGA_CONTROL 0x0338
-
-#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
-#define AVIVO_EXT1_PPLL_REF_DIV 0x404
-#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
-#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
-
-#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
-#define AVIVO_EXT2_PPLL_REF_DIV 0x414
-#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
-#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
-
-#define AVIVO_EXT1_PPLL_FB_DIV 0x430
-#define AVIVO_EXT2_PPLL_FB_DIV 0x434
-
-#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
-#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
-
-#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
-#define AVIVO_EXT2_PPLL_POST_DIV 0x444
-
-#define AVIVO_EXT1_PPLL_CNTL 0x448
-#define AVIVO_EXT2_PPLL_CNTL 0x44c
-
-#define AVIVO_P1PLL_CNTL 0x450
-#define AVIVO_P2PLL_CNTL 0x454
-#define AVIVO_P1PLL_INT_SS_CNTL 0x458
-#define AVIVO_P2PLL_INT_SS_CNTL 0x45c
-#define AVIVO_P1PLL_TMDSA_CNTL 0x460
-#define AVIVO_P2PLL_LVTMA_CNTL 0x464
-
-#define AVIVO_PCLK_CRTC1_CNTL 0x480
-#define AVIVO_PCLK_CRTC2_CNTL 0x484
-
-#define AVIVO_D1CRTC_H_TOTAL 0x6000
-#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
-#define AVIVO_D1CRTC_H_SYNC_A 0x6008
-#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
-#define AVIVO_D1CRTC_H_SYNC_B 0x6010
-#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
-
-#define AVIVO_D1CRTC_V_TOTAL 0x6020
-#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
-#define AVIVO_D1CRTC_V_SYNC_A 0x6028
-#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
-#define AVIVO_D1CRTC_V_SYNC_B 0x6030
-#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
-
-#define AVIVO_D1CRTC_CONTROL 0x6080
-# define AVIVO_CRTC_EN (1 << 0)
-# define AVIVO_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
-#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
-#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
-#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
-#define AVIVO_D1CRTC_STATUS_POSITION 0x60a0
-#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
-#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
-
-#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
-
-/* master controls */
-#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
-#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
-
-#define AVIVO_D1GRPH_ENABLE 0x6100
-#define AVIVO_D1GRPH_CONTROL 0x6104
-# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0)
-# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0)
-# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0)
-# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0)
-
-# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8)
-
-# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8)
-# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8)
-# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8)
-# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8)
-# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8)
-
-# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8)
-# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8)
-# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8)
-# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8)
-
-
-# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8)
-
-# define AVIVO_D1GRPH_SWAP_RB (1 << 16)
-# define AVIVO_D1GRPH_TILED (1 << 20)
-# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
-
-# define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
-# define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
-# define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)
-# define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20)
-
-/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
- * block and vice versa. This applies to GRPH, CUR, etc.
- */
-#define AVIVO_D1GRPH_LUT_SEL 0x6108
-#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
-#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
-#define AVIVO_D1GRPH_PITCH 0x6120
-#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
-#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
-#define AVIVO_D1GRPH_X_START 0x612c
-#define AVIVO_D1GRPH_Y_START 0x6130
-#define AVIVO_D1GRPH_X_END 0x6134
-#define AVIVO_D1GRPH_Y_END 0x6138
-#define AVIVO_D1GRPH_UPDATE 0x6144
-# define AVIVO_D1GRPH_SURFACE_UPDATE_PENDING (1 << 2)
-# define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16)
-#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
-# define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
-
-#define AVIVO_D1CUR_CONTROL 0x6400
-# define AVIVO_D1CURSOR_EN (1 << 0)
-# define AVIVO_D1CURSOR_MODE_SHIFT 8
-# define AVIVO_D1CURSOR_MODE_MASK (3 << 8)
-# define AVIVO_D1CURSOR_MODE_24BPP 2
-#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
-#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
-#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
-#define AVIVO_D1CUR_SIZE 0x6410
-#define AVIVO_D1CUR_POSITION 0x6414
-#define AVIVO_D1CUR_HOT_SPOT 0x6418
-#define AVIVO_D1CUR_UPDATE 0x6424
-# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
-
-#define AVIVO_DC_LUT_RW_SELECT 0x6480
-#define AVIVO_DC_LUT_RW_MODE 0x6484
-#define AVIVO_DC_LUT_RW_INDEX 0x6488
-#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
-#define AVIVO_DC_LUT_PWL_DATA 0x6490
-#define AVIVO_DC_LUT_30_COLOR 0x6494
-#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
-#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
-#define AVIVO_DC_LUT_AUTOFILL 0x64a0
-
-#define AVIVO_DC_LUTA_CONTROL 0x64c0
-#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
-#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
-#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
-#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
-#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
-#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
-
-#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
-# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
-# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
-# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
-# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
-# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2
-# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
-# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
-# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
-# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
-
-#define AVIVO_D1MODE_DATA_FORMAT 0x6528
-# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
-#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
-#define AVIVO_D1MODE_VBLANK_STATUS 0x6534
-# define AVIVO_VBLANK_ACK (1 << 4)
-#define AVIVO_D1MODE_VLINE_START_END 0x6538
-#define AVIVO_D1MODE_VLINE_STATUS 0x653c
-# define AVIVO_D1MODE_VLINE_STAT (1 << 12)
-#define AVIVO_DxMODE_INT_MASK 0x6540
-# define AVIVO_D1MODE_INT_MASK (1 << 0)
-# define AVIVO_D2MODE_INT_MASK (1 << 8)
-#define AVIVO_D1MODE_VIEWPORT_START 0x6580
-#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
-#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
-#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
-
-#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
-#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
-#define AVIVO_D1SCL_UPDATE 0x65cc
-# define AVIVO_D1SCL_UPDATE_LOCK (1 << 16)
-
-/* second crtc */
-#define AVIVO_D2CRTC_H_TOTAL 0x6800
-#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
-#define AVIVO_D2CRTC_H_SYNC_A 0x6808
-#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
-#define AVIVO_D2CRTC_H_SYNC_B 0x6810
-#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
-
-#define AVIVO_D2CRTC_V_TOTAL 0x6820
-#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
-#define AVIVO_D2CRTC_V_SYNC_A 0x6828
-#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
-#define AVIVO_D2CRTC_V_SYNC_B 0x6830
-#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
-
-#define AVIVO_D2CRTC_CONTROL 0x6880
-#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
-#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
-#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
-#define AVIVO_D2CRTC_STATUS_POSITION 0x68a0
-#define AVIVO_D2CRTC_FRAME_COUNT 0x68a4
-#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
-
-#define AVIVO_D2GRPH_ENABLE 0x6900
-#define AVIVO_D2GRPH_CONTROL 0x6904
-#define AVIVO_D2GRPH_LUT_SEL 0x6908
-#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
-#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
-#define AVIVO_D2GRPH_PITCH 0x6920
-#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
-#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
-#define AVIVO_D2GRPH_X_START 0x692c
-#define AVIVO_D2GRPH_Y_START 0x6930
-#define AVIVO_D2GRPH_X_END 0x6934
-#define AVIVO_D2GRPH_Y_END 0x6938
-#define AVIVO_D2GRPH_UPDATE 0x6944
-#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
-
-#define AVIVO_D2CUR_CONTROL 0x6c00
-#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
-#define AVIVO_D2CUR_SIZE 0x6c10
-#define AVIVO_D2CUR_POSITION 0x6c14
-
-#define AVIVO_D2MODE_VBLANK_STATUS 0x6d34
-#define AVIVO_D2MODE_VLINE_START_END 0x6d38
-#define AVIVO_D2MODE_VLINE_STATUS 0x6d3c
-#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
-#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
-#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
-#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
-
-#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
-#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
-
-#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214
-
-#define AVIVO_DACA_ENABLE 0x7800
-# define AVIVO_DAC_ENABLE (1 << 0)
-#define AVIVO_DACA_SOURCE_SELECT 0x7804
-# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
-# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
-# define AVIVO_DAC_SOURCE_TV (2 << 0)
-
-#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
-#define AVIVO_DACA_POWERDOWN 0x7850
-# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
-# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
-# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
-# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
-
-#define AVIVO_DACB_ENABLE 0x7a00
-#define AVIVO_DACB_SOURCE_SELECT 0x7a04
-#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
-#define AVIVO_DACB_POWERDOWN 0x7a50
-# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
-# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
-# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
-# define AVIVO_DACB_POWERDOWN_RED
-
-#define AVIVO_TMDSA_CNTL 0x7880
-# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
-# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
-# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
-# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
-# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
-# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
-# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
-#define AVIVO_TMDSA_SOURCE_SELECT 0x7884
-/* 78a8 appears to be some kind of (reasonably tolerant) clock?
- * 78d0 definitely hits the transmitter, definitely clock. */
-/* MYSTERY1 This appears to control dithering? */
-#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
-#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
-#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
-# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
-# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
-#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
-#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
-
-#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 <<
31)
-
-#define AVIVO_LVTMA_CNTL 0x7a80
-# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
-# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
-# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
-# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
-# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
-# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
-# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
-#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
-#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
-#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
-
-
-
-#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
-
-#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
-# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
-# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
-#define R500_LVTMA_CLOCK_ENABLE 0x7b00
-#define R600_LVTMA_CLOCK_ENABLE 0x7b04
-
-#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
-#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
-
-#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
-#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
-
-#define R500_LVTMA_PWRSEQ_CNTL 0x7af0
-#define R600_LVTMA_PWRSEQ_CNTL 0x7af4
-# define AVIVO_LVTMA_PWRSEQ_EN (1
<< 0)
-# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1
<< 2)
-# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1
<< 3)
-# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1
<< 4)
-# define AVIVO_LVTMA_SYNCEN (1
<< 8)
-# define AVIVO_LVTMA_SYNCEN_OVRD (1
<< 9)
-# define AVIVO_LVTMA_SYNCEN_POL (1
<< 10)
-# define AVIVO_LVTMA_DIGON (1
<< 16)
-# define AVIVO_LVTMA_DIGON_OVRD (1
<< 17)
-# define AVIVO_LVTMA_DIGON_POL (1
<< 18)
-# define AVIVO_LVTMA_BLON (1
<< 24)
-# define AVIVO_LVTMA_BLON_OVRD (1
<< 25)
-# define AVIVO_LVTMA_BLON_POL (1
<< 26)
-
-#define R500_LVTMA_PWRSEQ_STATE 0x7af4
-#define R600_LVTMA_PWRSEQ_STATE 0x7af8
-# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
-# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
-# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
-# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
-# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
-# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
-
-#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
-# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
-# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
-# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
-
-#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
-
-#define AVIVO_DC_GPIO_HPD_A 0x7e94
-#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
-
-#define AVIVO_DC_I2C_STATUS1 0x7d30
-# define AVIVO_DC_I2C_DONE (1 << 0)
-# define AVIVO_DC_I2C_NACK (1 << 1)
-# define AVIVO_DC_I2C_HALT (1 << 2)
-# define AVIVO_DC_I2C_GO (1 << 3)
-#define AVIVO_DC_I2C_RESET 0x7d34
-# define AVIVO_DC_I2C_SOFT_RESET (1 << 0)
-# define AVIVO_DC_I2C_ABORT (1 << 8)
-#define AVIVO_DC_I2C_CONTROL1 0x7d38
-# define AVIVO_DC_I2C_START (1 << 0)
-# define AVIVO_DC_I2C_STOP (1 << 1)
-# define AVIVO_DC_I2C_RECEIVE (1 << 2)
-# define AVIVO_DC_I2C_EN (1 << 8)
-# define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16)
-# define AVIVO_SEL_DDC1 0
-# define AVIVO_SEL_DDC2 1
-# define AVIVO_SEL_DDC3 2
-#define AVIVO_DC_I2C_CONTROL2 0x7d3c
-# define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0)
-# define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8)
-#define AVIVO_DC_I2C_CONTROL3 0x7d40
-# define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0)
-# define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1)
-# define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7)
-# define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8)
-# define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16)
-# define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24)
-#define AVIVO_DC_I2C_DATA 0x7d44
-#define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48
-# define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0)
-# define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8)
-# define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16)
-#define AVIVO_DC_I2C_ARBITRATION 0x7d50
-# define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0)
-# define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1)
-# define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8)
-# define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9)
-# define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16)
-# define AVIVO_DC_I2C_HW_USING_I2C (1 << 17)
-
-#define AVIVO_DC_GPIO_DDC1_MASK 0x7e40
-#define AVIVO_DC_GPIO_DDC1_A 0x7e44
-#define AVIVO_DC_GPIO_DDC1_EN 0x7e48
-#define AVIVO_DC_GPIO_DDC1_Y 0x7e4c
-
-#define AVIVO_DC_GPIO_DDC2_MASK 0x7e50
-#define AVIVO_DC_GPIO_DDC2_A 0x7e54
-#define AVIVO_DC_GPIO_DDC2_EN 0x7e58
-#define AVIVO_DC_GPIO_DDC2_Y 0x7e5c
-
-#define AVIVO_DC_GPIO_DDC3_MASK 0x7e60
-#define AVIVO_DC_GPIO_DDC3_A 0x7e64
-#define AVIVO_DC_GPIO_DDC3_EN 0x7e68
-#define AVIVO_DC_GPIO_DDC3_Y 0x7e6c
-
-#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc
-# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4)
-# define AVIVO_D2_VBLANK_INTERRUPT (1 << 5)
-#endif
+#endif
\ No newline at end of file
diff --git a/headers/private/graphics/radeon_hd/r600_reg.h
b/headers/private/graphics/radeon_hd/r600_reg.h
index 5c27c01..da662c3 100644
--- a/headers/private/graphics/radeon_hd/r600_reg.h
+++ b/headers/private/graphics/radeon_hd/r600_reg.h
@@ -30,16 +30,16 @@
/* Scratch Registers */
-#define R600_BIOS_0_SCRATCH 0x1724
-#define R600_BIOS_1_SCRATCH 0x1728
-#define R600_BIOS_2_SCRATCH 0x172c
-#define R600_BIOS_3_SCRATCH 0x1730
-#define R600_BIOS_4_SCRATCH 0x1734
-#define R600_BIOS_5_SCRATCH 0x1738
-#define R600_BIOS_6_SCRATCH 0x173c
-#define R600_BIOS_7_SCRATCH 0x1740
-
-
+#define R600_SCRATCH_REG0 0x1724 // aka
R600_BIOS_0_SCRATCH
+#define R600_SCRATCH_REG1 0x1728 // aka
R600_BIOS_1_SCRATCH
+#define R600_SCRATCH_REG2 0x172c // aka
R600_BIOS_2_SCRATCH
+#define R600_SCRATCH_REG3 0x1730 // aka
R600_BIOS_3_SCRATCH
+#define R600_SCRATCH_REG4 0x1734 // aka
R600_BIOS_4_SCRATCH
+#define R600_SCRATCH_REG5 0x1738 // aka
R600_BIOS_5_SCRATCH
+#define R600_SCRATCH_REG6 0x173c // aka
R600_BIOS_6_SCRATCH
+#define R600_SCRATCH_REG7 0x1740 // aka
R600_BIOS_7_SCRATCH
+
+/* CRT controler register offset */
#define R600_CRTC0_REGISTER_OFFSET 0x0
#define R600_CRTC1_REGISTER_OFFSET 0x800
diff --git a/headers/private/graphics/radeon_hd/r700_reg.h
b/headers/private/graphics/radeon_hd/r700_reg.h
index 39ecf49..9032269 100644
--- a/headers/private/graphics/radeon_hd/r700_reg.h
+++ b/headers/private/graphics/radeon_hd/r700_reg.h
@@ -28,6 +28,22 @@
#define R700_H
+/* Scratch Registers */
+#define R700_SCRATCH_REG0 0x8500
+#define R700_SCRATCH_REG1 0x8504
+#define R700_SCRATCH_REG2 0x8508
+#define R700_SCRATCH_REG3 0x850C
+#define R700_SCRATCH_REG4 0x8510
+#define R700_SCRATCH_REG5 0x8514
+#define R700_SCRATCH_REG6 0x8518
+#define R700_SCRATCH_REG7 0x851C
+#define R700_SCRATCH_UMSK 0x8540
+#define R700_SCRATCH_ADDR 0x8544
+
+/* CRT controler register offset */
+#define R700_CRTC0_REGISTER_OFFSET 0x0
+#define R700_CRTC1_REGISTER_OFFSET 0x800
+
#define R700_MAX_SH_GPRS 256
#define R700_MAX_TEMP_GPRS 16
#define R700_MAX_SH_THREADS 256
@@ -197,17 +213,6 @@
#define R700_PA_SC_MULTI_CHIP_CNTL 0x8B20
#define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
-#define R700_SCRATCH_REG0
0x8500
-#define R700_SCRATCH_REG1
0x8504
-#define R700_SCRATCH_REG2
0x8508
-#define R700_SCRATCH_REG3
0x850C
-#define R700_SCRATCH_REG4
0x8510
-#define R700_SCRATCH_REG5
0x8514
-#define R700_SCRATCH_REG6
0x8518
-#define R700_SCRATCH_REG7
0x851C
-#define R700_SCRATCH_UMSK
0x8540
-#define R700_SCRATCH_ADDR
0x8544
-
#if 0
#define SMX_DC_CTL0 0xA020
#define USE_HASH_FUNCTION (1 << 0)
diff --git a/headers/private/graphics/radeon_hd/radeon_hd.h
b/headers/private/graphics/radeon_hd/radeon_hd.h
index c8b6ef1..76534a1 100644
--- a/headers/private/graphics/radeon_hd/radeon_hd.h
+++ b/headers/private/graphics/radeon_hd/radeon_hd.h
@@ -14,8 +14,8 @@
#include "radeon_reg.h"
-#include "avivo.h"
-#include "r500_reg.h"
+//#include "r500_reg.h" // Not used atm
+#include "avivo_reg.h"
#include "r600_reg.h"
#include "r700_reg.h"
#include "evergreen_reg.h"
diff --git a/src/add-ons/accelerants/radeon_hd/bios.cpp
b/src/add-ons/accelerants/radeon_hd/bios.cpp
index a26c63a..5a2b776 100644
--- a/src/add-ons/accelerants/radeon_hd/bios.cpp
+++ b/src/add-ons/accelerants/radeon_hd/bios.cpp
@@ -37,8 +37,8 @@ radeon_bios_init_scratch()
uint32 biosScratch6;
if (info.chipsetID >= RADEON_R600) {
- biosScratch2 = Read32(OUT, R600_BIOS_2_SCRATCH);
- biosScratch6 = Read32(OUT, R600_BIOS_6_SCRATCH);
+ biosScratch2 = Read32(OUT, R600_SCRATCH_REG2);
+ biosScratch6 = Read32(OUT, R600_SCRATCH_REG6);
} else {
biosScratch2 = Read32(OUT, RADEON_BIOS_2_SCRATCH);
biosScratch6 = Read32(OUT, RADEON_BIOS_6_SCRATCH);
@@ -50,8 +50,8 @@ radeon_bios_init_scratch()
// bios shouldn't handle mode switching
if (info.chipsetID >= RADEON_R600) {
- Write32(OUT, R600_BIOS_2_SCRATCH, biosScratch2);
- Write32(OUT, R600_BIOS_6_SCRATCH, biosScratch6);
+ Write32(OUT, R600_SCRATCH_REG2, biosScratch2);
+ Write32(OUT, R600_SCRATCH_REG6, biosScratch6);
} else {
Write32(OUT, RADEON_BIOS_2_SCRATCH, biosScratch2);
Write32(OUT, RADEON_BIOS_6_SCRATCH, biosScratch6);
diff --git a/src/add-ons/accelerants/radeon_hd/display.cpp
b/src/add-ons/accelerants/radeon_hd/display.cpp
index a175adf..8f3c747 100644
--- a/src/add-ons/accelerants/radeon_hd/display.cpp
+++ b/src/add-ons/accelerants/radeon_hd/display.cpp
@@ -113,13 +113,13 @@ init_registers(register_info* regs, uint8 crtcID)
switch (crtcID) {
case 0:
- offset = R600_CRTC0_REGISTER_OFFSET;
+ offset = R700_CRTC0_REGISTER_OFFSET;
regs->vgaControl = AVIVO_D1VGA_CONTROL;
regs->grphPrimarySurfaceAddrHigh
=
R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
break;
case 1:
- offset = R600_CRTC1_REGISTER_OFFSET;
+ offset = R700_CRTC1_REGISTER_OFFSET;
regs->vgaControl = AVIVO_D2VGA_CONTROL;
regs->grphPrimarySurfaceAddrHigh
=
R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
@@ -134,7 +134,7 @@ init_registers(register_info* regs, uint8 crtcID)
regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset;
regs->grphControl = AVIVO_D1GRPH_CONTROL + offset;
- regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset;
+ regs->grphSwapControl = AVIVO_D1GRPH_SWAP_CNTL + offset;
regs->grphPrimarySurfaceAddr
= R700_D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
@@ -177,12 +177,12 @@ init_registers(register_info* regs, uint8 crtcID)
regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset;
regs->grphControl = AVIVO_D1GRPH_CONTROL + offset;
- regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset;
+ regs->grphSwapControl = AVIVO_D1GRPH_SWAP_CNTL + offset;
regs->grphPrimarySurfaceAddr
- = D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
+ = AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
regs->grphSecondarySurfaceAddr
- = D1GRPH_SECONDARY_SURFACE_ADDRESS + offset;
+ = AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + offset;
// Surface Address high only used on r700 and higher
regs->grphPrimarySurfaceAddrHigh = 0xDEAD;
diff --git a/src/add-ons/accelerants/radeon_hd/encoder.cpp
b/src/add-ons/accelerants/radeon_hd/encoder.cpp
index f017295..52a3beb 100644
--- a/src/add-ons/accelerants/radeon_hd/encoder.cpp
+++ b/src/add-ons/accelerants/radeon_hd/encoder.cpp
@@ -1013,7 +1013,7 @@ encoder_dac_load_detect(uint32 connectorIndex)
= B_HOST_TO_LENDIAN_INT16(ATOM_DEVICE_CRT1_SUPPORT);
atom_execute_table(gAtomContext, index, (uint32*)&args);
- uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
+ uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
if ((biosScratch0 & ATOM_S0_CRT1_MASK) != 0)
return true;
@@ -1023,7 +1023,7 @@ encoder_dac_load_detect(uint32 connectorIndex)
= B_HOST_TO_LENDIAN_INT16(ATOM_DEVICE_CRT2_SUPPORT);
atom_execute_table(gAtomContext, index, (uint32*)&args);
- uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
+ uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
if ((biosScratch0 & ATOM_S0_CRT2_MASK) != 0)
return true;
@@ -1035,7 +1035,7 @@ encoder_dac_load_detect(uint32 connectorIndex)
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
atom_execute_table(gAtomContext, index, (uint32*)&args);
- uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
+ uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
if ((biosScratch0 & (ATOM_S0_CV_MASK | ATOM_S0_CV_MASK_A)) != 0)
return true;
@@ -1047,7 +1047,7 @@ encoder_dac_load_detect(uint32 connectorIndex)
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
atom_execute_table(gAtomContext, index, (uint32*)&args);
- uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
+ uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
if ((biosScratch0
& (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) !=
0) {
@@ -1076,7 +1076,7 @@ encoder_dig_load_detect(uint32 connectorIndex)
encoder_external_setup(connectorIndex,
EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
- uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
+ uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
@@ -1465,7 +1465,7 @@ encoder_crtc_scratch(uint8 crtcID)
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
// TODO: r500
- uint32 biosScratch3 = Read32(OUT, R600_BIOS_3_SCRATCH);
+ uint32 biosScratch3 = Read32(OUT, R600_SCRATCH_REG3);
if ((encoderFlags & ATOM_DEVICE_TV1_SUPPORT) != 0) {
biosScratch3 &= ~ATOM_S3_TV1_CRTC_ACTIVE;
@@ -1501,7 +1501,7 @@ encoder_crtc_scratch(uint8 crtcID)
}
// TODO: r500
- Write32(OUT, R600_BIOS_3_SCRATCH, biosScratch3);
+ Write32(OUT, R600_SCRATCH_REG3, biosScratch3);
}
@@ -1514,7 +1514,7 @@ encoder_dpms_scratch(uint8 crtcID, bool power)
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
// TODO: r500
- uint32 biosScratch2 = Read32(OUT, R600_BIOS_2_SCRATCH);
+ uint32 biosScratch2 = Read32(OUT, R600_SCRATCH_REG2);
if ((encoderFlags & ATOM_DEVICE_TV1_SUPPORT) != 0) {
if (power == true)
@@ -1576,7 +1576,7 @@ encoder_dpms_scratch(uint8 crtcID, bool power)
else
biosScratch2 |= ATOM_S2_DFP5_DPMS_STATE;
}
- Write32(OUT, R600_BIOS_2_SCRATCH, biosScratch2);
+ Write32(OUT, R600_SCRATCH_REG2, biosScratch2);
}
@@ -1800,7 +1800,7 @@ void
encoder_output_lock(bool lock)
{
TRACE("%s: %s\n", __func__, lock ? "true" : "false");
- uint32 biosScratch6 = Read32(OUT, R600_BIOS_6_SCRATCH);
+ uint32 biosScratch6 = Read32(OUT, R600_SCRATCH_REG6);
if (lock) {
biosScratch6 |= ATOM_S6_CRITICAL_STATE;
@@ -1810,7 +1810,7 @@ encoder_output_lock(bool lock)
biosScratch6 |= ATOM_S6_ACC_MODE;
}
- Write32(OUT, R600_BIOS_6_SCRATCH, biosScratch6);
+ Write32(OUT, R600_SCRATCH_REG6, biosScratch6);
}
diff --git a/src/add-ons/accelerants/radeon_hd/gpu.cpp
b/src/add-ons/accelerants/radeon_hd/gpu.cpp
index ecd60a1..b835d2e 100644
--- a/src/add-ons/accelerants/radeon_hd/gpu.cpp
+++ b/src/add-ons/accelerants/radeon_hd/gpu.cpp
@@ -166,50 +166,50 @@ void
radeon_gpu_mc_halt(gpu_state* gpuState)
{
// Backup current memory controller state
- gpuState->d1vgaControl = Read32(OUT, D1VGA_CONTROL);
- gpuState->d2vgaControl = Read32(OUT, D2VGA_CONTROL);
- gpuState->vgaRenderControl = Read32(OUT, VGA_RENDER_CONTROL);
- gpuState->vgaHdpControl = Read32(OUT, VGA_HDP_CONTROL);
- gpuState->d1crtcControl = Read32(OUT, D1CRTC_CONTROL);
- gpuState->d2crtcControl = Read32(OUT, D2CRTC_CONTROL);
+ gpuState->d1vgaControl = Read32(OUT, AVIVO_D1VGA_CONTROL);
+ gpuState->d2vgaControl = Read32(OUT, AVIVO_D2VGA_CONTROL);
+ gpuState->vgaRenderControl = Read32(OUT, AVIVO_VGA_RENDER_CONTROL);
+ gpuState->vgaHdpControl = Read32(OUT, AVIVO_VGA_HDP_CONTROL);
+ gpuState->d1crtcControl = Read32(OUT, AVIVO_D1CRTC_CONTROL);
+ gpuState->d2crtcControl = Read32(OUT, AVIVO_D2CRTC_CONTROL);
// halt all memory controller actions
- Write32(OUT, VGA_RENDER_CONTROL, 0);
- Write32(OUT, D1CRTC_UPDATE_LOCK, 1);
- Write32(OUT, D2CRTC_UPDATE_LOCK, 1);
- Write32(OUT, D1CRTC_CONTROL, 0);
- Write32(OUT, D2CRTC_CONTROL, 0);
- Write32(OUT, D1CRTC_UPDATE_LOCK, 0);
- Write32(OUT, D2CRTC_UPDATE_LOCK, 0);
- Write32(OUT, D1VGA_CONTROL, 0);
- Write32(OUT, D2VGA_CONTROL, 0);
+ Write32(OUT, AVIVO_VGA_RENDER_CONTROL, 0);
+ Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1);
+ Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 1);
+ Write32(OUT, AVIVO_D1CRTC_CONTROL, 0);
+ Write32(OUT, AVIVO_D2CRTC_CONTROL, 0);
+ Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 0);
+ Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 0);
+ Write32(OUT, AVIVO_D1VGA_CONTROL, 0);
+ Write32(OUT, AVIVO_D2VGA_CONTROL, 0);
}
void
radeon_gpu_mc_resume(gpu_state* gpuState)
{
- Write32(OUT, D1GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
- Write32(OUT, D1GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
- Write32(OUT, D2GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
- Write32(OUT, D2GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
+ Write32(OUT, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
+ Write32(OUT, AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS,
gInfo->fb.vramStart);
+ Write32(OUT, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
+ Write32(OUT, AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS,
gInfo->fb.vramStart);
// TODO: Evergreen high surface addresses?
- Write32(OUT, VGA_MEMORY_BASE_ADDRESS, gInfo->fb.vramStart);
+ Write32(OUT, AVIVO_VGA_MEMORY_BASE_ADDRESS, gInfo->fb.vramStart);
// Unlock host access
- Write32(OUT, VGA_HDP_CONTROL, gpuState->vgaHdpControl);
+ Write32(OUT, AVIVO_VGA_HDP_CONTROL, gpuState->vgaHdpControl);
snooze(1);
// Restore memory controller state
- Write32(OUT, D1VGA_CONTROL, gpuState->d1vgaControl);
- Write32(OUT, D2VGA_CONTROL, gpuState->d2vgaControl);
- Write32(OUT, D1CRTC_UPDATE_LOCK, 1);
- Write32(OUT, D2CRTC_UPDATE_LOCK, 1);
- Write32(OUT, D1CRTC_CONTROL, gpuState->d1crtcControl);
- Write32(OUT, D2CRTC_CONTROL, gpuState->d2crtcControl);
- Write32(OUT, D1CRTC_UPDATE_LOCK, 0);
- Write32(OUT, D2CRTC_UPDATE_LOCK, 0);
- Write32(OUT, VGA_RENDER_CONTROL, gpuState->vgaRenderControl);
+ Write32(OUT, AVIVO_D1VGA_CONTROL, gpuState->d1vgaControl);
+ Write32(OUT, AVIVO_D2VGA_CONTROL, gpuState->d2vgaControl);
+ Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1);
+ Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 1);
+ Write32(OUT, AVIVO_D1CRTC_CONTROL, gpuState->d1crtcControl);
+ Write32(OUT, AVIVO_D2CRTC_CONTROL, gpuState->d2crtcControl);
+ Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 0);
+ Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 0);
+ Write32(OUT, AVIVO_VGA_RENDER_CONTROL, gpuState->vgaRenderControl);
}
@@ -331,7 +331,7 @@ radeon_gpu_mc_setup_r700()
if (radeon_gpu_mc_idlewait() != B_OK)
ERROR("%s: Modifying non-idle memory controller!\n", __func__);
- Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+ Write32(OUT, AVIVO_VGA_HDP_CONTROL, AVIVO_VGA_MEMORY_DISABLE);
// TODO: Memory Controller AGP
Write32(OUT, R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
@@ -391,7 +391,7 @@ radeon_gpu_mc_setup_evergreen()
if (radeon_gpu_mc_idlewait() != B_OK)
ERROR("%s: Modifying non-idle memory controller!\n", __func__);
- Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+ Write32(OUT, AVIVO_VGA_HDP_CONTROL, AVIVO_VGA_MEMORY_DISABLE);
// TODO: Memory Controller AGP
Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp
b/src/add-ons/accelerants/radeon_hd/mode.cpp
index 8dad3e5..c0b5c3d 100644
--- a/src/add-ons/accelerants/radeon_hd/mode.cpp
+++ b/src/add-ons/accelerants/radeon_hd/mode.cpp
@@ -219,10 +219,14 @@ radeon_set_display_mode(display_mode* mode)
}
// for debugging
- TRACE("D1CRTC_STATUS Value: 0x%X\n", Read32(CRT, D1CRTC_STATUS));
- TRACE("D2CRTC_STATUS Value: 0x%X\n", Read32(CRT, D2CRTC_STATUS));
- TRACE("D1CRTC_CONTROL Value: 0x%X\n", Read32(CRT,
D1CRTC_CONTROL));
- TRACE("D2CRTC_CONTROL Value: 0x%X\n", Read32(CRT,
D2CRTC_CONTROL));
+ TRACE("D1CRTC_STATUS Value: 0x%X\n",
+ Read32(CRT, AVIVO_D1CRTC_STATUS));
+ TRACE("D2CRTC_STATUS Value: 0x%X\n",
+ Read32(CRT, AVIVO_D2CRTC_STATUS));
+ TRACE("D1CRTC_CONTROL Value: 0x%X\n",
+ Read32(CRT, AVIVO_D1CRTC_CONTROL));
+ TRACE("D2CRTC_CONTROL Value: 0x%X\n",
+ Read32(CRT, AVIVO_D2CRTC_CONTROL));
TRACE("D1GRPH_ENABLE Value: 0x%X\n",
Read32(CRT, AVIVO_D1GRPH_ENABLE));
TRACE("D2GRPH_ENABLE Value: 0x%X\n",
diff --git a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
index bfbaf08..1609f9c 100644
--- a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
+++ b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
@@ -260,7 +260,7 @@ radeon_hd_getbios_ni(radeon_info &info)
write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
- write32(info.registers + D2VGA_CONTROL, (d2vga_control
+ write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
@@ -332,7 +332,7 @@ radeon_hd_getbios_r700(radeon_info &info)
write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
- write32(info.registers + D2VGA_CONTROL, (d2vga_control
+ write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
@@ -416,7 +416,7 @@ radeon_hd_getbios_r600(radeon_info &info)
write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
- write32(info.registers + D2VGA_CONTROL, (d2vga_control
+ write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
Other related posts:
- » [haiku-commits] haiku: hrev44441 - headers/private/graphics/radeon_hd src/add-ons/accelerants/radeon_hd - kallisti5
