[haiku-commits] haiku: hrev44138 - headers/private/kernel/arch/arm src/system/kernel/arch/arm
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Thu, 10 May 2012 19:40:34 +0200 (CEST)
hrev44138 adds 1 changeset to branch 'master'
old head: 875b21820256044d2e40d7fff021619d01b4d5ea
new head: f78cbe4710973798077cb8de62686a0c25ad3f13
----------------------------------------------------------------------------
f78cbe4: pl011 uart: Work on uart startup code
* Add missing PL011 register locations
* Move startup code to class init and ensure port is
started up more like Linux PL011 Amba driver.
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev44138
Commit: f78cbe4710973798077cb8de62686a0c25ad3f13
URL: http://cgit.haiku-os.org/haiku/commit/?id=f78cbe4
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Thu May 10 17:38:52 2012 UTC
----------------------------------------------------------------------------
3 files changed, 106 insertions(+), 23 deletions(-)
.../arch/arm/board/raspberry_pi/board_config.h | 5 +-
headers/private/kernel/arch/arm/uart_pl011.h | 75 ++++++++++++++--
src/system/kernel/arch/arm/uart_pl011.cpp | 49 +++++++---
----------------------------------------------------------------------------
diff --git a/headers/private/kernel/arch/arm/board/raspberry_pi/board_config.h
b/headers/private/kernel/arch/arm/board/raspberry_pi/board_config.h
index 5393754..789ca49 100644
--- a/headers/private/kernel/arch/arm/board/raspberry_pi/board_config.h
+++ b/headers/private/kernel/arch/arm/board/raspberry_pi/board_config.h
@@ -19,10 +19,13 @@
#define BOARD_UART_AMBA_PL011 1
#define BOARD_UART1_BASE UART0_BASE
+ // PL011 UART
#define BOARD_UART2_BASE UART1_BASE + 0x40
+ // miniUART
#define BOARD_UART3_BASE 0
+ // N/A
-#define BOARD_UART_DEBUG BOARD_UART2_BASE
+#define BOARD_UART_DEBUG BOARD_UART1_BASE
#define BOARD_UART_CLOCK 3000000
/* 3Mhz */
diff --git a/headers/private/kernel/arch/arm/uart_pl011.h
b/headers/private/kernel/arch/arm/uart_pl011.h
index 4c86118..470f40b 100644
--- a/headers/private/kernel/arch/arm/uart_pl011.h
+++ b/headers/private/kernel/arch/arm/uart_pl011.h
@@ -64,14 +64,14 @@
#define PL011_CR_DTR 0x0400 // DTR
#define PL011_CR_RXE 0x0200 // Receive enable
#define PL011_CR_TXE 0x0100 // Transmit enable
-#define PL011_CR_LBR 0x0080 // Loopback enable
-#define PL011_CR_RTIE 0x0040
-#define PL011_CR_TIE 0x0020
-#define PL011_CR_RIE 0x0010
-#define PL011_CR_MSIE 0x0008
-#define PL011_CR_IIRLP 0x0004 // SIR low power mode
-#define PL011_CR_SIREN 0x0002 // SIR enable
-#define PL011_CR_UARTEN 0x0001 // UART enable
+#define PL011_CR_LBE 0x0080 // Loopback enable
+#define PL010_CR_RTIE 0x0040
+#define PL010_CR_TIE 0x0020
+#define PL010_CR_RIE 0x0010
+#define PL010_CR_MSIE 0x0008
+#define PL01x_CR_IIRLP 0x0004 // SIR low power mode
+#define PL01x_CR_SIREN 0x0002 // SIR enable
+#define PL01x_CR_UARTEN 0x0001 // UART enable
#define PL011_LCRH_SPS 0x80
#define PL01x_LCRH_WLEN_8 0x60
@@ -84,7 +84,64 @@
#define PL01x_LCRH_PEN 0x02
#define PL01x_LCRH_BRK 0x01
-// TODO: Other PL01x registers + values?
+#define PL010_IIR_RTIS 0x08
+#define PL010_IIR_TIS 0x04
+#define PL010_IIR_RIS 0x02
+#define PL010_IIR_MIS 0x01
+
+#define PL011_IFLS_RX1_8 (0 << 3)
+#define PL011_IFLS_RX2_8 (1 << 3)
+#define PL011_IFLS_RX4_8 (2 << 3)
+#define PL011_IFLS_RX6_8 (3 << 3)
+#define PL011_IFLS_RX7_8 (4 << 3)
+#define PL011_IFLS_TX1_8 (0 << 0)
+#define PL011_IFLS_TX2_8 (1 << 0)
+#define PL011_IFLS_TX4_8 (2 << 0)
+#define PL011_IFLS_TX6_8 (3 << 0)
+#define PL011_IFLS_TX7_8 (4 << 0)
+
+#define PL011_IFLS_RX_HALF (5 << 3) // ST vendor only
+#define PL011_IFLS_TX_HALF (5 << 0) // ST vendor only
+
+#define PL011_OEIM (1 << 10) // overrun error interrupt mask
+#define PL011_BEIM (1 << 9) // break error interrupt mask
+#define PL011_PEIM (1 << 8) // parity error interrupt mask
+#define PL011_FEIM (1 << 7) // framing error interrupt mask
+#define PL011_RTIM (1 << 6) // receive timeout interrupt mask
+#define PL011_TXIM (1 << 5) // transmit interrupt mask
+#define PL011_RXIM (1 << 4) // receive interrupt mask
+#define PL011_DSRMIM (1 << 3) // DSR interrupt mask
+#define PL011_DCDMIM (1 << 2) // DCD interrupt mask
+#define PL011_CTSMIM (1 << 1) // CTS interrupt mask
+#define PL011_RIMIM (1 << 0) // RI interrupt mask
+
+#define PL011_OEIS (1 << 10) // overrun error interrupt state
+#define PL011_BEIS (1 << 9) // break error interrupt state
+#define PL011_PEIS (1 << 8) // parity error interrupt state
+#define PL011_FEIS (1 << 7) // framing error interrupt state
+#define PL011_RTIS (1 << 6) // receive timeout interrupt state
+#define PL011_TXIS (1 << 5) // transmit interrupt state
+#define PL011_RXIS (1 << 4) // receive interrupt state
+#define PL011_DSRMIS (1 << 3) // DSR interrupt state
+#define PL011_DCDMIS (1 << 2) // DCD interrupt state
+#define PL011_CTSMIS (1 << 1) // CTS interrupt state
+#define PL011_RIMIS (1 << 0) // RI interrupt state
+
+#define PL011_OEIC (1 << 10) // overrun error interrupt clear
+#define PL011_BEIC (1 << 9) // break error interrupt clear
+#define PL011_PEIC (1 << 8) // parity error interrupt clear
+#define PL011_FEIC (1 << 7) // framing error interrupt clear
+#define PL011_RTIC (1 << 6) // receive timeout interrupt clear
+#define PL011_TXIC (1 << 5) // transmit interrupt clear
+#define PL011_RXIC (1 << 4) // receive interrupt clear
+#define PL011_DSRMIC (1 << 3) // DSR interrupt clear
+#define PL011_DCDMIC (1 << 2) // DCD interrupt clear
+#define PL011_CTSMIC (1 << 1) // CTS interrupt clear
+#define PL011_RIMIC (1 << 0) // RI interrupt clear
+
+#define PL011_DMAONERR (1 << 2) // disable dma on err
+#define PL011_TXDMAE (1 << 1) // enable transmit dma
+#define PL011_RXDMAE (1 << 0) // enable receive dma
class UartPL011 {
diff --git a/src/system/kernel/arch/arm/uart_pl011.cpp
b/src/system/kernel/arch/arm/uart_pl011.cpp
index 6dc1e07..ad67eed 100644
--- a/src/system/kernel/arch/arm/uart_pl011.cpp
+++ b/src/system/kernel/arch/arm/uart_pl011.cpp
@@ -19,6 +19,38 @@ UartPL011::UartPL011(addr_t base)
fUARTEnabled(true),
fUARTBase(base)
{
+ // ** Loopback test
+ uint32 cr = PL01x_CR_UARTEN;
+ // Enable UART
+ cr |= PL011_CR_TXE;
+ // Enable TX
+ cr |= PL011_CR_LBE;
+ // Enable Loopback mode
+ WriteUart(PL011_CR, cr);
+
+ WriteUart(PL011_FBRD, 0);
+ WriteUart(PL011_IBRD, 1);
+ WriteUart(PL011_LCRH, 0); // TODO: ST is different tx, rx lcr
+
+ // Write a 0 to the port and wait for confim..
+ WriteUart(PL01x_DR, 0);
+
+ while (ReadUart(PL01x_FR) & PL01x_FR_BUSY);
+ // Wait for xmit on loopback
+
+ // ** Disable loopback, enable uart
+ cr = PL01x_CR_UARTEN | PL011_CR_RXE | PL011_CR_TXE;
+ WriteUart(PL011_CR, cr);
+
+ // Enable DMA to received request outputs
+ WriteUart(PL011_DMACR, PL011_DMAONERR);
+
+ // ** Clear interrupts
+ WriteUart(PL011_ICR, PL011_OEIS | PL011_BEIS
+ | PL011_PEIS | PL011_FEIS);
+
+ // Set Rx timeout interrupt mask and Rx interrput mask
+ WriteUart(PL011_IMSC, PL011_RTIM | PL011_RXIM);
}
@@ -67,28 +99,19 @@ void
UartPL011::InitEarly()
{
// Perform special hardware UART configuration
- // Raspberry Pi: Early setup handled by gpio_init in platform code
+ // Raspberry Pi: Early gpio handled by gpio_init in platform code
}
void
UartPL011::Enable()
{
- // TODO: Enable clock producer?
-
- unsigned char cr = PL011_CR_UARTEN;
+ uint32 cr = PL01x_CR_UARTEN;
// Enable UART
- cr |= PL011_CR_TXE; // | PL011_CR_RXE;
+ cr |= PL011_CR_TXE | PL011_CR_RXE;
// Enable TX and RX
- WriteUart(PL011_CR, cr);
-
- // TODO: For arm vendor, st different rx vs tx
- // WriteUart(PL011_LCRH, 0);
- WriteUart(PL01x_DR, 0);
-
- while (ReadUart(PL01x_FR) & PL01x_FR_BUSY);
- // Wait for xmit
+ WriteUart(PL011_CR, cr);
fUARTEnabled = true;
}
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