[haiku-commits] haiku: hrev44055 - src/add-ons/accelerants/radeon_hd
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Wed, 18 Apr 2012 22:21:06 +0200 (CEST)
hrev44055 adds 2 changesets to branch 'master'
old head: 163e02d670dd9648692f0280cf542bf1df46776f
new head: af6e0179caa3b796787848cdbf5a44e7d4c4f3b1
----------------------------------------------------------------------------
bb228d7: radeon_hd: Only assign encoder to crtc after dpms call
* This is the order I received via email long ago and
it makes more sense to me then the drm method
af6e017: radeon_hd: DIG encoder work
* Cleanup some AtomBIOS arg versions
* Add tracing to encoder calls
* Program a missing dig lane count
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
2 files changed, 56 insertions(+), 31 deletions(-)
src/add-ons/accelerants/radeon_hd/encoder.cpp | 79 ++++++++++++++-------
src/add-ons/accelerants/radeon_hd/mode.cpp | 8 +-
############################################################################
Commit: bb228d7ca60ae5922385b703df72831ee32b073d
URL: http://cgit.haiku-os.org/haiku/commit/?id=bb228d7
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Wed Apr 18 16:40:51 2012 UTC
radeon_hd: Only assign encoder to crtc after dpms call
* This is the order I received via email long ago and
it makes more sense to me then the drm method
----------------------------------------------------------------------------
diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp
b/src/add-ons/accelerants/radeon_hd/mode.cpp
index 381878d..2eaa2b6 100644
--- a/src/add-ons/accelerants/radeon_hd/mode.cpp
+++ b/src/add-ons/accelerants/radeon_hd/mode.cpp
@@ -173,15 +173,15 @@ radeon_set_display_mode(display_mode* mode)
if (connector_is_dp(connectorIndex))
dpInfo->laneCount = dp_get_lane_count(dpInfo, mode);
- // *** encoder prep
+ // *** crtc and encoder prep
encoder_output_lock(true);
encoder_dpms_set(id, B_DPMS_OFF);
- encoder_assign_crtc(id);
-
- // *** CRT controler prep
display_crtc_lock(id, ATOM_ENABLE);
display_crtc_dpms(id, B_DPMS_OFF);
+ // *** Set up encoder -> crtc routing
+ encoder_assign_crtc(id);
+
// *** CRT controler mode set
// TODO: program SS
pll_set(ATOM_PPLL1, mode->timing.pixel_clock, id);
############################################################################
Revision: hrev44055
Commit: af6e0179caa3b796787848cdbf5a44e7d4c4f3b1
URL: http://cgit.haiku-os.org/haiku/commit/?id=af6e017
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Wed Apr 18 20:16:53 2012 UTC
radeon_hd: DIG encoder work
* Cleanup some AtomBIOS arg versions
* Add tracing to encoder calls
* Program a missing dig lane count
----------------------------------------------------------------------------
diff --git a/src/add-ons/accelerants/radeon_hd/encoder.cpp
b/src/add-ons/accelerants/radeon_hd/encoder.cpp
index 4ac205b..f017295 100644
--- a/src/add-ons/accelerants/radeon_hd/encoder.cpp
+++ b/src/add-ons/accelerants/radeon_hd/encoder.cpp
@@ -37,6 +37,7 @@ extern "C" void _sPrintf(const char* format, ...);
void
encoder_init()
{
+ TRACE("%s: called\n", __func__);
radeon_shared_info &info = *gInfo->shared_info;
for (uint32 id = 0; id < ATOM_MAX_SUPPORTED_DEVICE; id++) {
@@ -79,6 +80,9 @@ encoder_assign_crtc(uint8 crtcID)
!= B_OK)
return;
+ TRACE("%s: table %" B_PRIu8 ".%" B_PRIu8 "\n", __func__,
+ tableMajor, tableMinor);
+
uint16 connectorIndex = gDisplay[crtcID]->connectorIndex;
uint16 encoderID = gConnector[connectorIndex]->encoder.objectID;
uint16 encoderFlags = gConnector[connectorIndex]->encoder.flags;
@@ -577,17 +581,23 @@ encoder_dig_setup(uint32 connectorIndex, uint32
pixelClock, int command)
bool linkB = connector->encoder.linkEnumeration
== GRAPH_OBJECT_ENUM_ID2 ? true : false;
- // determine DP panel mode
- uint32 panelMode;
- if (info.dceMajor >= 4 && isDPBridge) {
- if (connector->encoderExternal.objectID ==
ENCODER_OBJECT_ID_NUTMEG)
- panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
- else {
- // aka ENCODER_OBJECT_ID_TRAVIS or VIDEO_CONNECTOR_EDP
- panelMode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
- }
- } else
- panelMode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+ uint32 panelMode = 0;
+ // determine DP panel mode if doing panel mode setup
+ if (command == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) {
+ if (info.dceMajor >= 4 && isDPBridge) {
+ if (connector->encoderExternal.objectID ==
ENCODER_OBJECT_ID_NUTMEG)
+ panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
+ else if (connector->encoderExternal.objectID
+ == ENCODER_OBJECT_ID_TRAVIS) {
+ TRACE("%s: TODO: Travis: read DP confg data,
DP1 vs DP2 mode\n",
+ __func__);
+ panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
+ } else {
+ panelMode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+ }
+ } else
+ panelMode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+ }
#if 0
uint32 encoderID = gConnector[connectorIndex]->encoder.objectID;
@@ -606,6 +616,13 @@ encoder_dig_setup(uint32 connectorIndex, uint32
pixelClock, int command)
if (dpInfo->valid == true)
dpClock = dpInfo->linkRate;
+ bool dualLink = false;
+ if (connector->type == VIDEO_CONNECTOR_DVID
+ && pixelClock > 165000) {
+ // TODO: Expand on this
+ dualLink = true;
+ }
+
switch (tableMinor) {
case 1:
args.v1.ucAction = command;
@@ -618,6 +635,14 @@ encoder_dig_setup(uint32 connectorIndex, uint32
pixelClock, int command)
=
display_get_encoder_mode(connectorIndex);
}
+ if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP
+ || args.v1.ucEncoderMode ==
ATOM_ENCODER_MODE_DP_MST) {
+ args.v1.ucLaneNum = dpInfo->laneCount;
+ } else if (dualLink)
+ args.v1.ucLaneNum = 8;
+ else
+ args.v1.ucLaneNum = 4;
+
if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP
|| args.v1.ucEncoderMode ==
ATOM_ENCODER_MODE_DP_MST)
&& dpClock == 270000) {
@@ -644,8 +669,8 @@ encoder_dig_setup(uint32 connectorIndex, uint32 pixelClock,
int command)
break;
case 2:
case 3:
- args.v1.ucAction = command;
- args.v1.usPixelClock =
B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
+ args.v3.ucAction = command;
+ args.v3.usPixelClock =
B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
if (command == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
args.v3.ucPanelMode = panelMode;
@@ -654,16 +679,16 @@ encoder_dig_setup(uint32 connectorIndex, uint32
pixelClock, int command)
=
display_get_encoder_mode(connectorIndex);
}
- if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP
- || args.v1.ucEncoderMode ==
ATOM_ENCODER_MODE_DP_MST) {
- args.v1.ucLaneNum = dpInfo->laneCount;
- } else if (pixelClock > 165000)
- args.v1.ucLaneNum = 8;
+ if (args.v3.ucEncoderMode == ATOM_ENCODER_MODE_DP
+ || args.v3.ucEncoderMode ==
ATOM_ENCODER_MODE_DP_MST) {
+ args.v3.ucLaneNum = dpInfo->laneCount;
+ } else if (dualLink)
+ args.v3.ucLaneNum = 8;
else
- args.v1.ucLaneNum = 4;
+ args.v3.ucLaneNum = 4;
- if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP
- || args.v1.ucEncoderMode ==
ATOM_ENCODER_MODE_DP_MST)
+ if ((args.v3.ucEncoderMode == ATOM_ENCODER_MODE_DP
+ || args.v3.ucEncoderMode ==
ATOM_ENCODER_MODE_DP_MST)
&& dpClock == 270000) {
args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
}
@@ -673,23 +698,23 @@ encoder_dig_setup(uint32 connectorIndex, uint32
pixelClock, int command)
// TODO: get BPC
switch (8) {
case 0:
- args.v4.ucBitPerColor =
PANEL_BPC_UNDEFINE;
+ args.v3.ucBitPerColor =
PANEL_BPC_UNDEFINE;
break;
case 6:
- args.v4.ucBitPerColor =
PANEL_6BIT_PER_COLOR;
+ args.v3.ucBitPerColor =
PANEL_6BIT_PER_COLOR;
break;
case 8:
default:
- args.v4.ucBitPerColor =
PANEL_8BIT_PER_COLOR;
+ args.v3.ucBitPerColor =
PANEL_8BIT_PER_COLOR;
break;
case 10:
- args.v4.ucBitPerColor =
PANEL_10BIT_PER_COLOR;
+ args.v3.ucBitPerColor =
PANEL_10BIT_PER_COLOR;
break;
case 12:
- args.v4.ucBitPerColor =
PANEL_12BIT_PER_COLOR;
+ args.v3.ucBitPerColor =
PANEL_12BIT_PER_COLOR;
break;
case 16:
- args.v4.ucBitPerColor =
PANEL_16BIT_PER_COLOR;
+ args.v3.ucBitPerColor =
PANEL_16BIT_PER_COLOR;
break;
}
break;
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