[haiku-commits] haiku: hrev43512 - src/add-ons/accelerants/radeon_hd
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Fri, 16 Dec 2011 00:19:23 +0100 (CET)
hrev43512 adds 1 changeset to branch 'master'
old head: 099d5afd119fdc8e63198bdd96c543fbf669180b
new head: 09aaa658b0fa53eff3ad4cd5a44cf488bdfc1e3c
----------------------------------------------------------------------------
09aaa65: DisplayPort call organization and cleanup
* Add color space to BPP function
* Pass display_mode to DP lane count function
* Get BPP in DP lane count
* Move some DPInfo population out of DP link training
as other things need them sooner.
* Fill out DP code in external encoder setup
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev43512
Commit: 09aaa658b0fa53eff3ad4cd5a44cf488bdfc1e3c
URL: http://cgit.haiku-os.org/haiku/commit/?id=09aaa65
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Thu Dec 15 23:17:46 2011 UTC
----------------------------------------------------------------------------
7 files changed, 51 insertions(+), 28 deletions(-)
src/add-ons/accelerants/radeon_hd/connector.cpp | 6 ----
src/add-ons/accelerants/radeon_hd/display.cpp | 6 ++++
src/add-ons/accelerants/radeon_hd/displayport.cpp | 16 ++++------
src/add-ons/accelerants/radeon_hd/displayport.h | 1 +
src/add-ons/accelerants/radeon_hd/encoder.cpp | 23 ++++++--------
src/add-ons/accelerants/radeon_hd/mode.cpp | 26 +++++++++++++++++
src/add-ons/accelerants/radeon_hd/mode.h | 1 +
----------------------------------------------------------------------------
diff --git a/src/add-ons/accelerants/radeon_hd/connector.cpp
b/src/add-ons/accelerants/radeon_hd/connector.cpp
index 2bb5f3a..a9663d0 100644
--- a/src/add-ons/accelerants/radeon_hd/connector.cpp
+++ b/src/add-ons/accelerants/radeon_hd/connector.cpp
@@ -699,12 +699,6 @@ connector_probe()
break;
}
- if (gConnector[connectorIndex]->encoder.isDPBridge ==
true) {
- TRACE("%s: is bridge, performing bridge DDC
setup\n", __func__);
- encoder_external_setup(connectorIndex, 0,
- EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
- }
-
connectorIndex++;
} // END for each valid connector
} // end for each display path
diff --git a/src/add-ons/accelerants/radeon_hd/display.cpp
b/src/add-ons/accelerants/radeon_hd/display.cpp
index 85f5b0f..48697da 100644
--- a/src/add-ons/accelerants/radeon_hd/display.cpp
+++ b/src/add-ons/accelerants/radeon_hd/display.cpp
@@ -256,6 +256,12 @@ detect_displays()
if (displayIndex >= MAX_DISPLAY)
continue;
+ if (gConnector[id]->encoder.isDPBridge == true) {
+ // if this is a DisplayPort Bridge, setup ddc on bus
+ TRACE("%s: is bridge, performing bridge DDC setup\n",
__func__);
+ encoder_external_setup(id, 0,
EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
+ }
+
if (connector_read_edid(id,
&gDisplay[displayIndex]->edid_info)) {
if (gConnector[id]->encoder.type == VIDEO_ENCODER_TVDAC
diff --git a/src/add-ons/accelerants/radeon_hd/displayport.cpp
b/src/add-ons/accelerants/radeon_hd/displayport.cpp
index 8673d03..2f85c04 100644
--- a/src/add-ons/accelerants/radeon_hd/displayport.cpp
+++ b/src/add-ons/accelerants/radeon_hd/displayport.cpp
@@ -14,6 +14,7 @@
#include "accelerant.h"
#include "accelerant_protos.h"
#include "connector.h"
+#include "mode.h"
#undef TRACE
@@ -360,11 +361,10 @@ dp_get_link_clock_decode(uint32 dpLinkClock)
}
-static uint32
-dp_get_lane_count(uint32 connectorIndex, uint32 pixelClock)
+uint32
+dp_get_lane_count(uint32 connectorIndex, display_mode* mode)
{
- // TODO: bpp hardcoded
- uint32 bitsPerPixel = 32;
+ uint32 bitsPerPixel = get_mode_bpp(mode);
uint32 maxLaneCount = gDPInfo[connectorIndex]->config[DP_MAX_LANE_COUNT]
& DP_MAX_LANE_COUNT_MASK;
@@ -375,7 +375,7 @@ dp_get_lane_count(uint32 connectorIndex, uint32 pixelClock)
uint32 lane;
for (lane = 1; lane < maxLaneCount; lane <<= 1) {
uint32 maxDPPixelClock = (maxLinkRate * lane * 8) /
bitsPerPixel;
- if (pixelClock <= maxDPPixelClock)
+ if (mode->timing.pixel_clock <= maxDPPixelClock)
break;
}
TRACE("%s: connector: %" B_PRIu32 ", lanes: %" B_PRIu32 "\n", __func__,
@@ -413,6 +413,8 @@ dp_setup_connectors()
gDPInfo[index]->valid = true;
memcpy(gDPInfo[index]->config, auxMessage, 8);
}
+
+ gDPInfo[index]->clock = dp_get_link_clock(index);
}
}
@@ -429,10 +431,6 @@ dp_link_train(uint8 crtcID, display_mode* mode)
return B_ERROR;
}
- gDPInfo[connectorIndex]->clock = dp_get_link_clock(connectorIndex);
- gDPInfo[connectorIndex]->laneCount
- = dp_get_lane_count(connectorIndex, mode->timing.pixel_clock);
-
int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
// Table version
uint8 tableMajor;
diff --git a/src/add-ons/accelerants/radeon_hd/displayport.h
b/src/add-ons/accelerants/radeon_hd/displayport.h
index 70c0708..5a705dc 100644
--- a/src/add-ons/accelerants/radeon_hd/displayport.h
+++ b/src/add-ons/accelerants/radeon_hd/displayport.h
@@ -25,6 +25,7 @@ status_t dp_aux_set_i2c_byte(uint32 hwPin, uint16 address,
status_t dp_aux_get_i2c_byte(uint32 hwPin, uint16 address,
uint8* data, bool end);
+uint32 dp_get_lane_count(uint32 connectorIndex, display_mode* mode);
uint32 dp_get_link_clock(uint32 connectorIndex);
uint32 dp_get_link_clock_encode(uint32 dpLinkClock);
uint32 dp_get_link_clock_decode(uint32 dpLinkClock);
diff --git a/src/add-ons/accelerants/radeon_hd/encoder.cpp
b/src/add-ons/accelerants/radeon_hd/encoder.cpp
index 75b2ce7..89b71be 100644
--- a/src/add-ons/accelerants/radeon_hd/encoder.cpp
+++ b/src/add-ons/accelerants/radeon_hd/encoder.cpp
@@ -713,16 +713,15 @@ encoder_external_setup(uint32 connectorIndex, uint32
pixelClock, int command)
=
B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
args.v1.sDigEncoder.ucEncoderMode
=
display_get_encoder_mode(connectorIndex);
- #if 0
- if (0) { //
ENCODER_MODE_IS_DP(v1.sDigEncoder.ucEncoderMode)
- if (dp_clock == 270000) {
+
+ if (connector_is_dp(connectorIndex)) {
+ if
(gDPInfo[connectorIndex]->clock == 270000) {
args.v1.sDigEncoder.ucConfig
|=
ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
}
- args.v1.sDigEncoder.ucLaneNum =
dp_lane_count;
+ args.v1.sDigEncoder.ucLaneNum
+ =
gDPInfo[connectorIndex]->laneCount;
} else if (pixelClock > 165000) {
- #endif
- if (pixelClock > 165000) {
args.v1.sDigEncoder.ucLaneNum =
8;
} else {
args.v1.sDigEncoder.ucLaneNum =
4;
@@ -742,19 +741,17 @@ encoder_external_setup(uint32 connectorIndex, uint32
pixelClock, int command)
args.v3.sExtEncoder.ucEncoderMode
=
display_get_encoder_mode(connectorIndex);
- #if 0
- if
(ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
- if (dp_clock == 270000) {
+ if (connector_is_dp(connectorIndex)) {
+ if
(gDPInfo[connectorIndex]->clock == 270000) {
args.v3.sExtEncoder.ucConfig
|=EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
- } else if (dp_clock == 540000) {
+ } else if
(gDPInfo[connectorIndex]->clock == 540000) {
args.v3.sExtEncoder.ucConfig
|=EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
}
- args.v3.sExtEncoder.ucLaneNum =
dp_lane_count;
+ args.v1.sDigEncoder.ucLaneNum
+ =
gDPInfo[connectorIndex]->laneCount;
} else if (pixelClock > 165000) {
- #endif
- if (pixelClock > 165000) {
args.v3.sExtEncoder.ucLaneNum =
8;
} else {
args.v3.sExtEncoder.ucLaneNum =
4;
diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp
b/src/add-ons/accelerants/radeon_hd/mode.cpp
index ca26929..1a22745 100644
--- a/src/add-ons/accelerants/radeon_hd/mode.cpp
+++ b/src/add-ons/accelerants/radeon_hd/mode.cpp
@@ -37,6 +37,7 @@ extern "C" void _sPrintf(const char* format, ...);
# define TRACE(x...) ;
#endif
+#define ERROR(x...) _sPrintf("radeon_hd: " x)
status_t
create_mode_list(void)
@@ -172,6 +173,11 @@ radeon_set_display_mode(display_mode* mode)
uint16 connectorIndex = gDisplay[id]->connectorIndex;
+ // Determine DP lanes if DP
+ if (connector_is_dp(connectorIndex))
+ gDPInfo[connectorIndex]->laneCount
+ = dp_get_lane_count(connectorIndex, mode);
+
// *** encoder prep
encoder_output_lock(true);
encoder_dpms_set(id,
gConnector[connectorIndex]->encoder.objectID,
@@ -399,3 +405,23 @@ is_mode_sane(display_mode* mode)
}
+uint32
+get_mode_bpp(display_mode* mode)
+{
+ // Get bitsPerPixel for given mode
+
+ switch (mode->space) {
+ case B_CMAP8:
+ return 8;
+ case B_RGB15_LITTLE:
+ return 15;
+ case B_RGB16_LITTLE:
+ return 16;
+ case B_RGB24_LITTLE:
+ case B_RGB32_LITTLE:
+ return 32;
+ }
+ ERROR("%s: Unknown colorspace for mode, guessing 32 bits per pixel\n",
+ __func__);
+ return 32;
+}
diff --git a/src/add-ons/accelerants/radeon_hd/mode.h
b/src/add-ons/accelerants/radeon_hd/mode.h
index a0b3759..59a5ce1 100644
--- a/src/add-ons/accelerants/radeon_hd/mode.h
+++ b/src/add-ons/accelerants/radeon_hd/mode.h
@@ -33,6 +33,7 @@ status_t is_mode_sane(display_mode* mode);
uint32 radeon_dpms_capabilities(void);
uint32 radeon_dpms_mode(void);
void radeon_dpms_set(int mode);
+uint32 get_mode_bpp(display_mode* mode);
#endif /*RADEON_HD_MODE_H*/
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