[haiku-commits] haiku: hrev43497 - src/add-ons/accelerants/radeon_hd headers/private/graphics/radeon_hd
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Wed, 14 Dec 2011 18:02:35 +0100 (CET)
hrev43497 adds 2 changesets to branch 'master'
old head: cda904359e0e36cf048b8cc04891178b33afa464
new head: 18500e1cd61a4573bea20cb33544d8051a236112
----------------------------------------------------------------------------
249495e: Add complete set of DRM DisplayPort defines into radeon_hd
* I'd rather this be common code, but I don't have access
to the DisplayPort specifications. If I added it as common
code I would want to be 100% it was complete and variables
were named properly.
* For now putting in radeon_hd private headers
18500e1: GPIO info struct style cleanup, (hopefully) no functional change
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
6 files changed, 255 insertions(+), 114 deletions(-)
.../private/graphics/radeon_hd/displayport_reg.h | 160 ++++++++++++++++
src/add-ons/accelerants/radeon_hd/accelerant.h | 44 ++--
src/add-ons/accelerants/radeon_hd/connector.cpp | 112 ++++++------
src/add-ons/accelerants/radeon_hd/connector.h | 2 +-
src/add-ons/accelerants/radeon_hd/displayport.cpp | 23 ++-
src/add-ons/accelerants/radeon_hd/displayport.h | 28 +---
############################################################################
Commit: 249495e284126bc59526cbad8e77d1f0f4db3083
URL: http://cgit.haiku-os.org/haiku/commit/?id=249495e
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Wed Dec 14 16:19:00 2011 UTC
Add complete set of DRM DisplayPort defines into radeon_hd
* I'd rather this be common code, but I don't have access
to the DisplayPort specifications. If I added it as common
code I would want to be 100% it was complete and variables
were named properly.
* For now putting in radeon_hd private headers
----------------------------------------------------------------------------
diff --git a/headers/private/graphics/radeon_hd/displayport_reg.h
b/headers/private/graphics/radeon_hd/displayport_reg.h
new file mode 100644
index 0000000..a13ca8c
--- /dev/null
+++ b/headers/private/graphics/radeon_hd/displayport_reg.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2011, Haiku, Inc. All Rights Reserved.
+ * Distributed under the terms of the MIT License.
+ *
+ * Authors:
+ * Alexander von Gluck, kallisti5@xxxxxxxxxxx
+ *
+ * DisplayPort DRM Specifications:
+ * Copyright © 2008 Keith Packard
+ */
+#ifndef __DISPLAYPORT_REG_H__
+#define __DISPLAYPORT_REG_H__
+
+
+/* TODO: get access to DisplayPort specifications and
+ * place this into graphic private common code
+ */
+
+#define AUX_NATIVE_WRITE 0x8
+#define AUX_NATIVE_READ 0x9
+#define AUX_I2C_WRITE 0x0
+#define AUX_I2C_READ 0x1
+#define AUX_I2C_STATUS 0x2
+#define AUX_I2C_MOT 0x4
+
+#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
+#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
+#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
+#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
+
+#define AUX_I2C_REPLY_ACK (0x0 << 6)
+#define AUX_I2C_REPLY_NACK (0x1 << 6)
+#define AUX_I2C_REPLY_DEFER (0x2 << 6)
+#define AUX_I2C_REPLY_MASK (0x3 << 6)
+
+// ** AUX channel addresses
+// * DisplayPort Configuration data
+#define DP_DPCD_REV 0x000
+#define DP_MAX_LINK_RATE 0x001
+#define DP_MAX_LANE_COUNT 0x002
+#define DP_MAX_LANE_COUNT_MASK 0x1f
+#define DP_TPS3_SUPPORTED (1 << 6)
+#define DP_ENHANCED_FRAME_CAP (1 << 7)
+
+#define DP_MAX_DOWNSPREAD 0x003
+#define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
+
+#define DP_NORP
0x004
+
+// Down stream DisplayPort status
+#define DP_DOWNSTREAMPORT_PRESENT 0x005
+# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
+# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
+// Down stream port types:
+// 00 = DisplayPort
+// 01 = Analog
+// 10 = TMDS or HDMI
+// 11 = Other
+
+#define DP_FORMAT_CONVERSION (1 << 3)
+
+#define DP_MAIN_LINK_CHANNEL_CODING 0x006
+#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
+
+// DisplayPort link configuration
+#define DP_LINK_BW_SET 0x100
+#define DP_LINK_BW_1_62 0x06
+#define DP_LINK_BW_2_7 0x0a
+#define DP_LINK_BW_5_4 0x14
+#define DP_LANE_COUNT_SET 0x101
+#define DP_LANE_COUNT_MASK 0x0f
+#define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
+
+// DisplayPort training patern (used for link training)
+#define DP_TRAINING_PATTERN_SET 0x102
+#define DP_TRAINING_PATTERN_DISABLE 0
+#define DP_TRAINING_PATTERN_1 1
+#define DP_TRAINING_PATTERN_2 2
+#define DP_TRAINING_PATTERN_3 3
+#define DP_TRAINING_PATTERN_MASK 0x3
+
+#define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
+#define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
+#define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
+#define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
+#define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
+
+#define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
+#define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
+
+#define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
+#define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
+#define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
+#define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
+
+#define DP_TRAINING_LANE0_SET 0x103
+#define DP_TRAINING_LANE1_SET 0x104
+#define DP_TRAINING_LANE2_SET 0x105
+#define DP_TRAINING_LANE3_SET 0x106
+
+#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
+#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
+#define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
+#define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
+
+#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
+
+#define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
+#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
+
+#define DP_DOWNSPREAD_CTRL 0x107
+#define DP_SPREAD_AMP_0_5 (1 << 4)
+
+#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
+#define DP_SET_ANSI_8B10B (1 << 0)
+
+#define DP_LANE0_1_STATUS 0x202
+#define DP_LANE2_3_STATUS 0x203
+#define DP_LANE_CR_DONE (1 << 0)
+#define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
+#define DP_LANE_SYMBOL_LOCKED (1 << 2)
+
+#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE \
+ | DP_LANE_CHANNEL_EQ_DONE \
+ | DP_LANE_SYMBOL_LOCKED)
+
+#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
+
+#define DP_INTERLANE_ALIGN_DONE (1 << 0)
+#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
+#define DP_LINK_STATUS_UPDATED (1 << 7)
+
+#define DP_SINK_STATUS 0x205
+
+#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
+#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
+
+#define DP_ADJUST_REQUEST_LANE0_1 0x206
+#define DP_ADJUST_REQUEST_LANE2_3 0x207
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
+#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
+#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
+
+#define DP_SET_POWER 0x600
+#define DP_SET_POWER_D0 0x1
+
+
+#endif /*__DISPLAYPORT_REG_H__*/
diff --git a/src/add-ons/accelerants/radeon_hd/displayport.cpp
b/src/add-ons/accelerants/radeon_hd/displayport.cpp
index be9d31e..f4805ef 100644
--- a/src/add-ons/accelerants/radeon_hd/displayport.cpp
+++ b/src/add-ons/accelerants/radeon_hd/displayport.cpp
@@ -13,6 +13,7 @@
#include "accelerant.h"
#include "accelerant_protos.h"
+#include "displayport_reg.h"
#undef TRACE
diff --git a/src/add-ons/accelerants/radeon_hd/displayport.h
b/src/add-ons/accelerants/radeon_hd/displayport.h
index 914c2d0..e1a7b45 100644
--- a/src/add-ons/accelerants/radeon_hd/displayport.h
+++ b/src/add-ons/accelerants/radeon_hd/displayport.h
@@ -13,26 +13,6 @@
#include <SupportDefs.h>
-// From the VESA DisplayPort spec
-// TODO: may want to move these into common code
-#define AUX_NATIVE_WRITE 0x8
-#define AUX_NATIVE_READ 0x9
-#define AUX_I2C_WRITE 0x0
-#define AUX_I2C_READ 0x1
-#define AUX_I2C_STATUS 0x2
-#define AUX_I2C_MOT 0x4
-
-#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
-#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
-#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
-#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
-
-#define AUX_I2C_REPLY_ACK (0x0 << 6)
-#define AUX_I2C_REPLY_NACK (0x1 << 6)
-#define AUX_I2C_REPLY_DEFER (0x2 << 6)
-#define AUX_I2C_REPLY_MASK (0x3 << 6)
-
-
int dp_aux_write(uint32 hwLine, uint16 address, uint8* send,
uint8 sendBytes, uint8 delay);
int dp_aux_read(uint32 hwLine, uint16 address, uint8* recv,
############################################################################
Revision: hrev43497
Commit: 18500e1cd61a4573bea20cb33544d8051a236112
URL: http://cgit.haiku-os.org/haiku/commit/?id=18500e1
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Wed Dec 14 17:09:41 2011 UTC
GPIO info struct style cleanup, (hopefully) no functional change
----------------------------------------------------------------------------
diff --git a/src/add-ons/accelerants/radeon_hd/accelerant.h
b/src/add-ons/accelerants/radeon_hd/accelerant.h
index 1f40ea8..38dcad1 100644
--- a/src/add-ons/accelerants/radeon_hd/accelerant.h
+++ b/src/add-ons/accelerants/radeon_hd/accelerant.h
@@ -102,28 +102,28 @@ struct register_info {
typedef struct {
bool valid;
- bool hw_capable; // can do hw assisted i2c
- uint32 hw_line;
-
- uint32 mask_scl_reg;
- uint32 mask_sda_reg;
- uint32 mask_scl_mask;
- uint32 mask_sda_mask;
-
- uint32 en_scl_reg;
- uint32 en_sda_reg;
- uint32 en_scl_mask;
- uint32 en_sda_mask;
-
- uint32 y_scl_reg;
- uint32 y_sda_reg;
- uint32 y_scl_mask;
- uint32 y_sda_mask;
-
- uint32 a_scl_reg;
- uint32 a_sda_reg;
- uint32 a_scl_mask;
- uint32 a_sda_mask;
+ uint32 hwPin; // GPIO hardware pin on GPU
+ bool hwCapable; // can do hw assisted i2c
+
+ uint32 sclMaskReg;
+ uint32 sdaMaskReg;
+ uint32 sclMask;
+ uint32 sdaMask;
+
+ uint32 sclEnReg;
+ uint32 sdaEnReg;
+ uint32 sclEnMask;
+ uint32 sdaEnMask;
+
+ uint32 sclYReg;
+ uint32 sdaYReg;
+ uint32 sclYMask;
+ uint32 sdaYMask;
+
+ uint32 sclAReg;
+ uint32 sdaAReg;
+ uint32 sclAMask;
+ uint32 sdaAMask;
} gpio_info;
diff --git a/src/add-ons/accelerants/radeon_hd/connector.cpp
b/src/add-ons/accelerants/radeon_hd/connector.cpp
index fa513d0..be18ee1 100644
--- a/src/add-ons/accelerants/radeon_hd/connector.cpp
+++ b/src/add-ons/accelerants/radeon_hd/connector.cpp
@@ -39,46 +39,46 @@ gpio_lock_i2c(void* cookie, bool lock)
uint32 buffer = 0;
if (lock == true) {
- // hw_capable and > DCE3
- if (info->hw_capable == true && gInfo->shared_info->dceMajor >=
3) {
+ // hwCapable and > DCE3
+ if (info->hwCapable == true && gInfo->shared_info->dceMajor >=
3) {
// Switch GPIO pads to ddc mode
- buffer = Read32(OUT, info->mask_scl_reg);
+ buffer = Read32(OUT, info->sclMaskReg);
buffer &= ~(1 << 16);
- Write32(OUT, info->mask_scl_reg, buffer);
+ Write32(OUT, info->sclMaskReg, buffer);
}
// Clear pins
- buffer = Read32(OUT, info->a_scl_reg) & ~info->a_scl_mask;
- Write32(OUT, info->a_scl_reg, buffer);
- buffer = Read32(OUT, info->a_sda_reg) & ~info->a_sda_mask;
- Write32(OUT, info->a_sda_reg, buffer);
+ buffer = Read32(OUT, info->sclAReg) & ~info->sclAMask;
+ Write32(OUT, info->sclAReg, buffer);
+ buffer = Read32(OUT, info->sdaAReg) & ~info->sdaAMask;
+ Write32(OUT, info->sdaAReg, buffer);
}
// Set pins to input
- buffer = Read32(OUT, info->en_scl_reg) & ~info->en_scl_mask;
- Write32(OUT, info->en_scl_reg, buffer);
- buffer = Read32(OUT, info->en_sda_reg) & ~info->en_sda_mask;
- Write32(OUT, info->en_sda_reg, buffer);
+ buffer = Read32(OUT, info->sclEnReg) & ~info->sclEnMask;
+ Write32(OUT, info->sclEnReg, buffer);
+ buffer = Read32(OUT, info->sdaEnReg) & ~info->sdaEnMask;
+ Write32(OUT, info->sdaEnReg, buffer);
// mask clock GPIO pins for software use
- buffer = Read32(OUT, info->mask_scl_reg);
+ buffer = Read32(OUT, info->sclMaskReg);
if (lock == true)
- buffer |= info->mask_scl_mask;
+ buffer |= info->sclMask;
else
- buffer &= ~info->mask_scl_mask;
+ buffer &= ~info->sclMask;
- Write32(OUT, info->mask_scl_reg, buffer);
- Read32(OUT, info->mask_scl_reg);
+ Write32(OUT, info->sclMaskReg, buffer);
+ Read32(OUT, info->sclMaskReg);
// mask data GPIO pins for software use
- buffer = Read32(OUT, info->mask_sda_reg);
+ buffer = Read32(OUT, info->sdaMaskReg);
if (lock == true)
- buffer |= info->mask_sda_mask;
+ buffer |= info->sdaMask;
else
- buffer &= ~info->mask_sda_mask;
+ buffer &= ~info->sdaMask;
- Write32(OUT, info->mask_sda_reg, buffer);
- Read32(OUT, info->mask_sda_reg);
+ Write32(OUT, info->sdaMaskReg, buffer);
+ Read32(OUT, info->sdaMaskReg);
}
@@ -87,8 +87,8 @@ gpio_get_i2c_bit(void* cookie, int* _clock, int* _data)
{
gpio_info* info = (gpio_info*)cookie;
- uint32 scl = Read32(OUT, info->y_scl_reg) & info->y_scl_mask;
- uint32 sda = Read32(OUT, info->y_sda_reg) & info->y_sda_mask;
+ uint32 scl = Read32(OUT, info->sclYReg) & info->sclYMask;
+ uint32 sda = Read32(OUT, info->sdaYReg) & info->sdaYMask;
*_clock = scl != 0;
*_data = sda != 0;
@@ -102,15 +102,15 @@ gpio_set_i2c_bit(void* cookie, int clock, int data)
{
gpio_info* info = (gpio_info*)cookie;
- uint32 scl = Read32(OUT, info->en_scl_reg) & ~info->en_scl_mask;
- scl |= clock ? 0 : info->en_scl_mask;
- Write32(OUT, info->en_scl_reg, scl);
- Read32(OUT, info->en_scl_reg);
+ uint32 scl = Read32(OUT, info->sclEnReg) & ~info->sclEnMask;
+ scl |= clock ? 0 : info->sclEnMask;
+ Write32(OUT, info->sclEnReg, scl);
+ Read32(OUT, info->sclEnReg);
- uint32 sda = Read32(OUT, info->en_sda_reg) & ~info->en_sda_mask;
- sda |= data ? 0 : info->en_sda_mask;
- Write32(OUT, info->en_sda_reg, sda);
- Read32(OUT, info->en_sda_reg);
+ uint32 sda = Read32(OUT, info->sdaEnReg) & ~info->sdaEnMask;
+ sda |= data ? 0 : info->sdaEnMask;
+ Write32(OUT, info->sdaEnReg, sda);
+ Read32(OUT, info->sdaEnReg);
return B_OK;
}
@@ -223,11 +223,11 @@ connector_read_edid_lvds(uint32 connectorIndex,
edid1_info* edid)
status_t
-connector_attach_gpio(uint32 connectorIndex, uint8 hwLine)
+connector_attach_gpio(uint32 connectorIndex, uint8 hwPin)
{
gConnector[connectorIndex]->gpioID = 0;
for (uint32 i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
- if (gGPIOInfo[i]->hw_line != hwLine)
+ if (gGPIOInfo[i]->hwPin != hwPin)
continue;
gConnector[connectorIndex]->gpioID = i;
return B_OK;
@@ -295,50 +295,50 @@ gpio_probe()
}
// populate gpio information
- gGPIOInfo[i]->hw_line = gpio->sucI2cId.ucAccess;
- gGPIOInfo[i]->hw_capable
+ gGPIOInfo[i]->hwPin = gpio->sucI2cId.ucAccess;
+ gGPIOInfo[i]->hwCapable
= (gpio->sucI2cId.sbfAccess.bfHW_Capable) ? true :
false;
// GPIO mask (Allows software to control the GPIO pad)
// 0 = chip access; 1 = only software;
- gGPIOInfo[i]->mask_scl_reg
+ gGPIOInfo[i]->sclMaskReg
= B_LENDIAN_TO_HOST_INT16(gpio->usClkMaskRegisterIndex)
* 4;
- gGPIOInfo[i]->mask_sda_reg
+ gGPIOInfo[i]->sdaMaskReg
=
B_LENDIAN_TO_HOST_INT16(gpio->usDataMaskRegisterIndex) * 4;
- gGPIOInfo[i]->mask_scl_mask = 1 << gpio->ucClkMaskShift;
- gGPIOInfo[i]->mask_sda_mask = 1 << gpio->ucDataMaskShift;
+ gGPIOInfo[i]->sclMask = 1 << gpio->ucClkMaskShift;
+ gGPIOInfo[i]->sdaMask = 1 << gpio->ucDataMaskShift;
// GPIO output / write (A) enable
// 0 = GPIO input (Y); 1 = GPIO output (A);
- gGPIOInfo[i]->en_scl_reg
+ gGPIOInfo[i]->sclEnReg
= B_LENDIAN_TO_HOST_INT16(gpio->usClkEnRegisterIndex) *
4;
- gGPIOInfo[i]->en_sda_reg
+ gGPIOInfo[i]->sdaEnReg
= B_LENDIAN_TO_HOST_INT16(gpio->usDataEnRegisterIndex)
* 4;
- gGPIOInfo[i]->en_scl_mask = 1 << gpio->ucClkEnShift;
- gGPIOInfo[i]->en_sda_mask = 1 << gpio->ucDataEnShift;
+ gGPIOInfo[i]->sclEnMask = 1 << gpio->ucClkEnShift;
+ gGPIOInfo[i]->sdaEnMask = 1 << gpio->ucDataEnShift;
// GPIO output / write (A)
- gGPIOInfo[i]->a_scl_reg
+ gGPIOInfo[i]->sclAReg
= B_LENDIAN_TO_HOST_INT16(gpio->usClkA_RegisterIndex) *
4;
- gGPIOInfo[i]->a_sda_reg
+ gGPIOInfo[i]->sdaAReg
= B_LENDIAN_TO_HOST_INT16(gpio->usDataA_RegisterIndex)
* 4;
- gGPIOInfo[i]->a_scl_mask = 1 << gpio->ucClkA_Shift;
- gGPIOInfo[i]->a_sda_mask = 1 << gpio->ucDataA_Shift;
+ gGPIOInfo[i]->sclAMask = 1 << gpio->ucClkA_Shift;
+ gGPIOInfo[i]->sdaAMask = 1 << gpio->ucDataA_Shift;
// GPIO input / read (Y)
- gGPIOInfo[i]->y_scl_reg
+ gGPIOInfo[i]->sclYReg
= B_LENDIAN_TO_HOST_INT16(gpio->usClkY_RegisterIndex) *
4;
- gGPIOInfo[i]->y_sda_reg
+ gGPIOInfo[i]->sdaYReg
= B_LENDIAN_TO_HOST_INT16(gpio->usDataY_RegisterIndex)
* 4;
- gGPIOInfo[i]->y_scl_mask = 1 << gpio->ucClkY_Shift;
- gGPIOInfo[i]->y_sda_mask = 1 << gpio->ucDataY_Shift;
+ gGPIOInfo[i]->sclYMask = 1 << gpio->ucClkY_Shift;
+ gGPIOInfo[i]->sdaYMask = 1 << gpio->ucDataY_Shift;
// ensure data is valid
- gGPIOInfo[i]->valid = gGPIOInfo[i]->mask_scl_reg ? true : false;
+ gGPIOInfo[i]->valid = gGPIOInfo[i]->sclMaskReg ? true : false;
- TRACE("%s: GPIO @ %" B_PRIu32 ", valid: %s, hw_line: 0x%"
B_PRIX32 "\n",
+ TRACE("%s: GPIO @ %" B_PRIu32 ", valid: %s, hwPin: 0x%"
B_PRIX32 "\n",
__func__, i, gGPIOInfo[i]->valid ? "true" : "false",
- gGPIOInfo[i]->hw_line);
+ gGPIOInfo[i]->hwPin);
}
return B_OK;
@@ -727,7 +727,7 @@ debug_connectors()
ERROR(" + connector: %s\n",
get_connector_name(connectorType));
ERROR(" + gpio table id: %" B_PRIu16 "\n", gpioID);
ERROR(" + gpio hw pin: 0x%" B_PRIX32 "\n",
- gGPIOInfo[gpioID]->hw_line);
+ gGPIOInfo[gpioID]->hwPin);
ERROR(" + gpio valid: %s\n",
gGPIOInfo[gpioID]->valid ? "true" : "false");
ERROR(" + encoder: %s\n",
get_encoder_name(encoderType));
diff --git a/src/add-ons/accelerants/radeon_hd/connector.h
b/src/add-ons/accelerants/radeon_hd/connector.h
index 81b1de9..6522ddb 100644
--- a/src/add-ons/accelerants/radeon_hd/connector.h
+++ b/src/add-ons/accelerants/radeon_hd/connector.h
@@ -61,7 +61,7 @@ const int kConnectorConvert[] = {
status_t gpio_probe();
-status_t connector_attach_gpio(uint32 id, uint8 hw_line);
+status_t connector_attach_gpio(uint32 id, uint8 hwPin);
bool connector_read_edid(uint32 connector, edid1_info* edid);
status_t connector_probe();
status_t connector_probe_legacy();
diff --git a/src/add-ons/accelerants/radeon_hd/displayport.cpp
b/src/add-ons/accelerants/radeon_hd/displayport.cpp
index f4805ef..d15a27c 100644
--- a/src/add-ons/accelerants/radeon_hd/displayport.cpp
+++ b/src/add-ons/accelerants/radeon_hd/displayport.cpp
@@ -29,10 +29,10 @@
static int
-dp_aux_speak(uint32 hwLine, uint8* send, int sendBytes,
+dp_aux_speak(uint32 hwPin, uint8* send, int sendBytes,
uint8* recv, int recvBytes, uint8 delay, uint8* ack)
{
- if (hwLine == 0) {
+ if (hwPin == 0) {
ERROR("%s: cannot speak on invalid GPIO pin!\n", __func__);
return B_IO_ERROR;
}
@@ -50,7 +50,7 @@ dp_aux_speak(uint32 hwLine, uint8* send, int sendBytes,
args.v1.lpAuxRequest = 0;
args.v1.lpDataOut = 16;
args.v1.ucDataOutLen = 0;
- args.v1.ucChannelID = hwLine;
+ args.v1.ucChannelID = hwPin;
args.v1.ucDelay = delay / 10;
//if (ASIC_IS_DCE4(rdev))
@@ -87,7 +87,7 @@ dp_aux_speak(uint32 hwLine, uint8* send, int sendBytes,
int
-dp_aux_write(uint32 hwLine, uint16 address,
+dp_aux_write(uint32 hwPin, uint16 address,
uint8* send, uint8 sendBytes, uint8 delay)
{
uint8 auxMessage[20];
@@ -105,7 +105,7 @@ dp_aux_write(uint32 hwLine, uint16 address,
uint8 retry;
for (retry = 0; retry < 4; retry++) {
uint8 ack;
- int result = dp_aux_speak(hwLine, auxMessage, auxMessageBytes,
+ int result = dp_aux_speak(hwPin, auxMessage, auxMessageBytes,
NULL, 0, delay, &ack);
if (result == B_BUSY)
@@ -126,7 +126,7 @@ dp_aux_write(uint32 hwLine, uint16 address,
int
-dp_aux_read(uint32 hwLine, uint16 address,
+dp_aux_read(uint32 hwPin, uint16 address,
uint8* recv, int recvBytes, uint8 delay)
{
uint8 auxMessage[4];
@@ -140,7 +140,7 @@ dp_aux_read(uint32 hwLine, uint16 address,
uint8 retry;
for (retry = 0; retry < 4; retry++) {
uint8 ack;
- int result = dp_aux_speak(hwLine, auxMessage, auxMessageBytes,
+ int result = dp_aux_speak(hwPin, auxMessage, auxMessageBytes,
recv, recvBytes, delay, &ack);
if (result == B_BUSY)
@@ -161,7 +161,7 @@ dp_aux_read(uint32 hwLine, uint16 address,
status_t
-dp_aux_get_i2c_byte(uint32 hwLine, uint16 address, uint8* data, bool end)
+dp_aux_get_i2c_byte(uint32 hwPin, uint16 address, uint8* data, bool end)
{
uint8 auxMessage[5];
int auxMessageBytes = 4; // 4 for read
@@ -182,7 +182,7 @@ dp_aux_get_i2c_byte(uint32 hwLine, uint16 address, uint8*
data, bool end)
uint8 reply[2];
int replyBytes = 1;
- int result = dp_aux_speak(hwLine, auxMessage, auxMessageBytes,
+ int result = dp_aux_speak(hwPin, auxMessage, auxMessageBytes,
reply, replyBytes, 0, &ack);
if (result == B_BUSY)
continue;
@@ -232,7 +232,7 @@ dp_aux_get_i2c_byte(uint32 hwLine, uint16 address, uint8*
data, bool end)
status_t
-dp_aux_set_i2c_byte(uint32 hwLine, uint16 address, uint8* data, bool end)
+dp_aux_set_i2c_byte(uint32 hwPin, uint16 address, uint8* data, bool end)
{
uint8 auxMessage[5];
int auxMessageBytes = 5; // 5 for write
@@ -254,7 +254,7 @@ dp_aux_set_i2c_byte(uint32 hwLine, uint16 address, uint8*
data, bool end)
uint8 reply[2];
int replyBytes = 1;
- int result = dp_aux_speak(hwLine, auxMessage, auxMessageBytes,
+ int result = dp_aux_speak(hwPin, auxMessage, auxMessageBytes,
reply, replyBytes, 0, &ack);
if (result == B_BUSY)
continue;
diff --git a/src/add-ons/accelerants/radeon_hd/displayport.h
b/src/add-ons/accelerants/radeon_hd/displayport.h
index e1a7b45..b7be707 100644
--- a/src/add-ons/accelerants/radeon_hd/displayport.h
+++ b/src/add-ons/accelerants/radeon_hd/displayport.h
@@ -13,13 +13,13 @@
#include <SupportDefs.h>
-int dp_aux_write(uint32 hwLine, uint16 address, uint8* send,
+int dp_aux_write(uint32 hwPin, uint16 address, uint8* send,
uint8 sendBytes, uint8 delay);
-int dp_aux_read(uint32 hwLine, uint16 address, uint8* recv,
+int dp_aux_read(uint32 hwPin, uint16 address, uint8* recv,
int recvBytes, uint8 delay);
-status_t dp_aux_set_i2c_byte(uint32 hwLine, uint16 address,
+status_t dp_aux_set_i2c_byte(uint32 hwPin, uint16 address,
uint8* data, bool end);
-status_t dp_aux_get_i2c_byte(uint32 hwLine, uint16 address,
+status_t dp_aux_get_i2c_byte(uint32 hwPin, uint16 address,
uint8* data, bool end);
uint32 dp_get_link_clock(uint32 connectorIndex);
Other related posts:
- » [haiku-commits] haiku: hrev43497 - src/add-ons/accelerants/radeon_hd headers/private/graphics/radeon_hd - kallisti5
