hrev43327 adds 1 changeset to branch 'master' old head: f1a3316b9606a67fa38053682691fa971b9baa87 new head: 54fda1c6dfe5f9b76df5c0da2dbffbe591699a67 ---------------------------------------------------------------------------- 2 files changed, 79 insertions(+), 0 deletions(-) src/add-ons/accelerants/radeon_hd/gpu.cpp | 77 +++++++++++++++++++++++++ src/add-ons/accelerants/radeon_hd/gpu.h | 2 + ############################################################################ Revision: hrev43327 Commit: 54fda1c6dfe5f9b76df5c0da2dbffbe591699a67 URL: http://cgit.haiku-os.org/haiku/commit/?id=54fda1c Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> Date: Sat Nov 26 23:35:33 2011 UTC Enhance lvds laptop panel support * if an edid request for LVDS panel is detected, we now return true and the VESA edid info. * add #if 0'ed function to pull prefered timing info from atombios on LVDS panels, still need to generate a fake EDID with this. * not sure which method above is better... maybe a combination of both ---------------------------------------------------------------------------- diff --git a/src/add-ons/accelerants/radeon_hd/gpu.cpp b/src/add-ons/accelerants/radeon_hd/gpu.cpp index c9213fc..9b98a2f 100644 --- a/src/add-ons/accelerants/radeon_hd/gpu.cpp +++ b/src/add-ons/accelerants/radeon_hd/gpu.cpp @@ -623,6 +623,14 @@ radeon_gpu_read_edid(uint32 connector, edid1_info *edid) if (gGPIOInfo[gpioID]->valid == false) return false; + if (gConnector[connector]->type == VIDEO_CONNECTOR_LVDS) { + // we should call radeon_gpu_read_edid_lvds at some point + ERROR("%s: LCD panel detected (LVDS), sending VESA EDID!\n", + __func__); + memcpy(edid, &gInfo->shared_info->edid_info, sizeof(struct edid1_info)); + return true; + } + i2c_bus bus; ddc2_init_timing(&bus); @@ -644,6 +652,75 @@ radeon_gpu_read_edid(uint32 connector, edid1_info *edid) } +#if 0 +bool +radeon_gpu_read_edid_lvds(uint32 connector, edid1_info *edid) +{ + uint8 dceMajor; + uint8 dceMinor; + int index = GetIndexIntoMasterTable(DATA, LVDS_Info); + uint16 offset; + + if (atom_parse_data_header(gAtomContexg, index, NULL, + &dceMajor, &dceMinor, &offset) == B_OK) { + lvdsInfo = (union lvds_info *)(gAtomContext->bios + offset); + + display_timing timing; + // Pixel Clock + timing.pixel_clock + = B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usPixClk) * 10; + // Horizontal + timing.h_display + = B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usHActive); + timing.h_total = timing.h_display + B_LENDIAN_TO_HOST_INT16( + lvdsInfo->info.sLCDTiming.usHBlanking_Time); + timing.h_sync_start = timing.h_display + + B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usHSyncOffset); + timing.h_sync_end = timing.h_sync_start + + B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usHSyncWidth); + // Vertical + timing.v_display + = B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usVActive); + timing.v_total = timing.v_display + B_LENDIAN_TO_HOST_INT16( + lvdsInfo->info.sLCDTiming.usVBlanking_Time); + timing.v_sync_start = timing.v_display + + B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usVSyncOffset); + timing.v_sync_end = timing.v_sync_start + + B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.sLCDTiming.usVSyncWidth); + + #if 0 + // Who cares. + uint32 powerDelay + = B_LENDIAN_TO_HOST_INT16(lvdsInfo->info.usOffDelayInMs); + uint32 lcdMisc = lvdsInfo->info.ucLVDS_Misc; + #endif + + uint16 flags = B_LENDIAN_TO_HOST_INT16( + lvdsInfo->info.sLCDTiming.susModeMiscInfo.usAccess); + + if ((flags & ATOM_VSYNC_POLARITY) == 0) + timing.flags |= B_POSITIVE_VSYNC; + if ((flags & ATOM_HSYNC_POLARITY) == 0) + timing.flags |= B_POSITIVE_HSYNC; + + // Extra flags + if ((flags & ATOM_INTERLACE) != 0) + timing.flags |= B_TIMING_INTERLACED; + + #if 0 + // We don't use these timing flags at the moment + if ((flags & ATOM_COMPOSITESYNC) != 0) + timing.flags |= MODE_FLAG_CSYNC; + if ((flags & ATOM_DOUBLE_CLOCK_MODE) != 0) + timing.flags |= MODE_FLAG_DBLSCAN; + #endif + + // TODO: generate a fake EDID with information above + } +} +#endif + + status_t radeon_gpu_i2c_attach(uint32 id, uint8 hw_line) { diff --git a/src/add-ons/accelerants/radeon_hd/gpu.h b/src/add-ons/accelerants/radeon_hd/gpu.h index 81005ff..ac42211 100644 --- a/src/add-ons/accelerants/radeon_hd/gpu.h +++ b/src/add-ons/accelerants/radeon_hd/gpu.h @@ -11,6 +11,8 @@ #include "accelerant.h" +#include <video_configuration.h> + #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 #define HDP_NONSURFACE_BASE 0x2C04