From Jérôme Duval <jerome.duval@xxxxxxxxx>:
Jérôme Duval has uploaded this change for review. (
https://review.haiku-os.org/c/haiku/+/5335 ;)
Change subject: intel_extreme: switch FDI to i915 register naming
......................................................................
intel_extreme: switch FDI to i915 register naming
---
M headers/private/graphics/intel_extreme/intel_extreme.h
M src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
M src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
3 files changed, 63 insertions(+), 60 deletions(-)
git pull ssh://git.haiku-os.org:22/haiku refs/changes/35/5335/1
diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h
b/headers/private/graphics/intel_extreme/intel_extreme.h
index 8ca923c..933e239 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -1462,12 +1462,18 @@
// PCH for each display pipe.
// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
// transcoder B, so we have the same mapping as with the display pipes.
-#define PCH_FDI_RX_BASE_REGISTER 0xf0000
-#define PCH_FDI_RX_PIPE_OFFSET 0x01000
-#define PCH_FDI_RX_CONTROL 0x00c
-#define PCH_FDI_RX_MISC 0x010
-#define PCH_FDI_RX_IIR 0x014
-#define PCH_FDI_RX_IMR 0x018
+#define _FDI_RXA_CTL 0xf000c
+#define _FDI_RXB_CTL 0xf100c
+#define FDI_RX_CTL(pipe) (_FDI_RXA_CTL +
(_FDI_RXB_CTL - _FDI_RXA_CTL) * (pipe - INTEL_PIPE_A))
+#define _FDI_RXA_MISC 0xf0010
+#define _FDI_RXB_MISC 0xf1010
+#define FDI_RX_MISC(pipe) (_FDI_RXA_MISC +
(_FDI_RXB_MISC - _FDI_RXA_MISC) * (pipe - INTEL_PIPE_A))
+#define _FDI_RXA_IIR 0xf0014
+#define _FDI_RXB_IIR 0xf1014
+#define FDI_RX_IIR(pipe) (_FDI_RXA_IIR +
(_FDI_RXB_IIR - _FDI_RXA_IIR) * (pipe - INTEL_PIPE_A))
+#define _FDI_RXA_IMR 0xf0018
+#define _FDI_RXB_IMR 0xf1018
+#define FDI_RX_IMR(pipe) (_FDI_RXA_IMR +
(_FDI_RXB_IMR - _FDI_RXA_IMR) * (pipe - INTEL_PIPE_A))
#define FDI_RX_ENABLE (1 << 31)
#define FDI_RX_PLL_ENABLED (1 << 13)
@@ -1506,8 +1512,12 @@
#define FDI_FS_ERRC_ENABLE (1 << 27)
#define FDI_FE_ERRC_ENABLE (1 << 26)
-#define PCH_FDI_RX_TRANS_UNIT_SIZE_1 0x30
-#define PCH_FDI_RX_TRANS_UNIT_SIZE_2 0x38
+#define _FDI_RXA_TUSIZE1 0xf0030
+#define _FDI_RXA_TUSIZE2 0xf0038
+#define _FDI_RXB_TUSIZE1 0xf1030
+#define _FDI_RXB_TUSIZE2 0xf1038
+#define FDI_RX_TUSIZE1(pipe) (_FDI_RXA_TUSIZE1 + (_FDI_RXB_TUSIZE1 -
_FDI_RXA_TUSIZE1) * (pipe - INTEL_PIPE_A))
+#define FDI_RX_TUSIZE2(pipe) (_FDI_RXA_TUSIZE2 + (_FDI_RXB_TUSIZE2 -
_FDI_RXA_TUSIZE2) * (pipe - INTEL_PIPE_A))
#define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25)
#define FDI_RX_TRANS_UNIT_MASK 0x7e000000
@@ -1525,9 +1535,9 @@
#define FDI_RX_TP1_TO_TP2_64 (3 << 20)
#define FDI_RX_FDI_DELAY_90 (0x90 << 0)
-#define PCH_FDI_TX_BASE_REGISTER 0x60000
-#define PCH_FDI_TX_PIPE_OFFSET 0x01000
-#define PCH_FDI_TX_CONTROL 0x100
+#define _FDI_TXA_CTL (0x0100 |
REGS_NORTH_PIPE_AND_PORT)
+#define _FDI_TXB_CTL (0x1100 |
REGS_NORTH_PIPE_AND_PORT)
+#define FDI_TX_CTL(pipe) (_FDI_TXA_CTL +
(_FDI_TXB_CTL - _FDI_TXA_CTL) * (pipe - INTEL_PIPE_A))
#define FDI_TX_ENABLE (1 << 31)
#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
diff --git a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
index 90cc71f..a1def60 100644
--- a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
+++ b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
@@ -44,10 +44,8 @@
FDITransmitter::FDITransmitter(pipe_index pipeIndex)
:
- fRegisterBase(PCH_FDI_TX_BASE_REGISTER)
+ fPipeIndex(pipeIndex)
{
- if (pipeIndex == INTEL_PIPE_B)
- fRegisterBase += PCH_FDI_TX_PIPE_OFFSET * 1;
}
@@ -60,7 +58,7 @@
FDITransmitter::Enable()
{
CALLED();
- uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL;
+ uint32 targetRegister = FDI_TX_CTL(fPipeIndex);
uint32 value = read32(targetRegister);
write32(targetRegister, value | FDI_TX_ENABLE);
@@ -73,7 +71,7 @@
FDITransmitter::Disable()
{
CALLED();
- uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL;
+ uint32 targetRegister = FDI_TX_CTL(fPipeIndex);
uint32 value = read32(targetRegister);
write32(targetRegister, value & ~FDI_TX_ENABLE);
@@ -86,8 +84,7 @@
FDITransmitter::IsPLLEnabled()
{
CALLED();
- return (read32(fRegisterBase + PCH_FDI_TX_CONTROL) & FDI_TX_PLL_ENABLED)
- != 0;
+ return (read32(FDI_TX_CTL(fPipeIndex)) & FDI_TX_PLL_ENABLED) != 0;
}
@@ -95,7 +92,7 @@
FDITransmitter::EnablePLL(uint32 lanes)
{
CALLED();
- uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL;
+ uint32 targetRegister = FDI_TX_CTL(fPipeIndex);
uint32 value = read32(targetRegister);
if ((value & FDI_TX_PLL_ENABLED) != 0) {
// already enabled, possibly IronLake where it always is
@@ -121,11 +118,11 @@
{
CALLED();
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_ILK)) {
- // on IronLake the FDI PLL is alaways enabled, so no point in
trying...
+ // on IronLake the FDI PLL is always enabled, so no point in
trying...
return;
}
- uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL;
+ uint32 targetRegister = FDI_TX_CTL(fPipeIndex);
write32(targetRegister, read32(targetRegister) & ~FDI_TX_PLL_ENABLED);
read32(targetRegister);
spin(100);
@@ -137,10 +134,8 @@
FDIReceiver::FDIReceiver(pipe_index pipeIndex)
:
- fRegisterBase(PCH_FDI_RX_BASE_REGISTER)
+ fPipeIndex(pipeIndex)
{
- if (pipeIndex == INTEL_PIPE_B)
- fRegisterBase += PCH_FDI_RX_PIPE_OFFSET * 1;
}
@@ -153,7 +148,7 @@
FDIReceiver::Enable()
{
CALLED();
- uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
+ uint32 targetRegister = FDI_RX_CTL(fPipeIndex);
uint32 value = read32(targetRegister);
write32(targetRegister, value | FDI_RX_ENABLE);
@@ -166,7 +161,7 @@
FDIReceiver::Disable()
{
CALLED();
- uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
+ uint32 targetRegister = FDI_RX_CTL(fPipeIndex);
uint32 value = read32(targetRegister);
write32(targetRegister, value & ~FDI_RX_ENABLE);
@@ -179,8 +174,7 @@
FDIReceiver::IsPLLEnabled()
{
CALLED();
- return (read32(fRegisterBase + PCH_FDI_RX_CONTROL) & FDI_RX_PLL_ENABLED)
- != 0;
+ return (read32(FDI_RX_CTL(fPipeIndex)) & FDI_RX_PLL_ENABLED) != 0;
}
@@ -188,7 +182,7 @@
FDIReceiver::EnablePLL(uint32 lanes)
{
CALLED();
- uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
+ uint32 targetRegister = FDI_RX_CTL(fPipeIndex);
uint32 value = read32(targetRegister);
if ((value & FDI_RX_PLL_ENABLED) != 0) {
// already enabled, possibly IronLake where it always is
@@ -218,7 +212,7 @@
FDIReceiver::DisablePLL()
{
CALLED();
- uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
+ uint32 targetRegister = FDI_RX_CTL(fPipeIndex);
write32(targetRegister, read32(targetRegister) & ~FDI_RX_PLL_ENABLED);
read32(targetRegister);
spin(100);
@@ -229,7 +223,7 @@
FDIReceiver::SwitchClock(bool toPCDClock)
{
CALLED();
- uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
+ uint32 targetRegister = FDI_RX_CTL(fPipeIndex);
write32(targetRegister, (read32(targetRegister) & ~FDI_RX_CLOCK_MASK)
| (toPCDClock ? FDI_RX_CLOCK_PCD : FDI_RX_CLOCK_RAW));
read32(targetRegister);
@@ -254,8 +248,8 @@
{
CALLED();
- uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
- uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
+ uint32 txControl = FDI_TX_CTL(fPipeIndex);
+ uint32 rxControl = FDI_RX_CTL(fPipeIndex);
//Link bit depth: this should be globally known per FDI link (i.e.
laptop panel 3x6, rest 3x8)
*bitsPerPixel = ((read32(rxControl) & FDI_RX_LINK_BPC_MASK) >>
FDI_RX_LINK_COLOR_SHIFT);
@@ -336,12 +330,12 @@
status_t result = B_OK;
- uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
- uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
+ uint32 txControl = FDI_TX_CTL(fPipeIndex);
+ uint32 rxControl = FDI_RX_CTL(fPipeIndex);
//Set receiving end TU size bits to match sending end's setting
- write32(Receiver().Base() + PCH_FDI_RX_TRANS_UNIT_SIZE_1,
FDI_RX_TRANS_UNIT_MASK);
- write32(Receiver().Base() + PCH_FDI_RX_TRANS_UNIT_SIZE_2,
FDI_RX_TRANS_UNIT_MASK);
+ write32(FDI_RX_TUSIZE1(fPipeIndex), FDI_RX_TRANS_UNIT_MASK);
+ write32(FDI_RX_TUSIZE2(fPipeIndex), FDI_RX_TRANS_UNIT_MASK);
#if 0
//when link training is to be done re-enable this code
@@ -376,8 +370,8 @@
FDILink::_NormalTrain(uint32 lanes)
{
CALLED();
- uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
- uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
+ uint32 txControl = FDI_TX_CTL(fPipeIndex);
+ uint32 rxControl = FDI_RX_CTL(fPipeIndex);
// Enable normal link training
uint32 tmp = read32(txControl);
@@ -419,14 +413,14 @@
FDILink::_IlkTrain(uint32 lanes)
{
CALLED();
- uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
- uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
+ uint32 txControl = FDI_TX_CTL(fPipeIndex);
+ uint32 rxControl = FDI_RX_CTL(fPipeIndex);
// Train 1: unmask FDI RX Interrupt symbol_lock and bit_lock
- uint32 tmp = read32(Receiver().Base() + PCH_FDI_RX_IMR);
+ uint32 tmp = read32(FDI_RX_IMR(fPipeIndex));
tmp &= ~FDI_RX_SYMBOL_LOCK;
tmp &= ~FDI_RX_BIT_LOCK;
- write32(Receiver().Base() + PCH_FDI_RX_IMR, tmp);
+ write32(FDI_RX_IMR(fPipeIndex), tmp);
spin(150);
// Enable CPU FDI TX and RX
@@ -455,7 +449,7 @@
| FDI_RX_PHASE_SYNC_POINTER_EN);
}
- uint32 iirControl = Receiver().Base() + PCH_FDI_RX_IIR;
+ uint32 iirControl = FDI_RX_IIR(fPipeIndex);
TRACE("%s: FDI RX IIR Control @ 0x%" B_PRIx32 "\n", __func__,
iirControl);
int tries = 0;
@@ -513,11 +507,11 @@
FDILink::_SnbTrain(uint32 lanes)
{
CALLED();
- uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
- uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
+ uint32 txControl = FDI_TX_CTL(fPipeIndex);
+ uint32 rxControl = FDI_RX_CTL(fPipeIndex);
// Train 1
- uint32 imrControl = Receiver().Base() + PCH_FDI_RX_IMR;
+ uint32 imrControl = FDI_RX_IMR(fPipeIndex);
uint32 tmp = read32(imrControl);
tmp &= ~FDI_RX_SYMBOL_LOCK;
tmp &= ~FDI_RX_BIT_LOCK;
@@ -535,7 +529,7 @@
tmp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
write32(txControl, tmp);
- write32(Receiver().Base() + PCH_FDI_RX_MISC,
+ write32(FDI_RX_MISC(fPipeIndex),
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
tmp = read32(rxControl);
@@ -549,7 +543,7 @@
write32(rxControl, tmp);
Receiver().Enable();
- uint32 iirControl = Receiver().Base() + PCH_FDI_RX_IIR;
+ uint32 iirControl = FDI_RX_IIR(fPipeIndex);
TRACE("%s: FDI RX IIR Control @ 0x%" B_PRIx32 "\n", __func__,
iirControl);
int i = 0;
@@ -656,8 +650,8 @@
FDILink::_AutoTrain(uint32 lanes)
{
CALLED();
- uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
- uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
+ uint32 txControl = FDI_TX_CTL(fPipeIndex);
+ uint32 rxControl = FDI_RX_CTL(fPipeIndex);
uint32 buffer = read32(txControl);
@@ -672,8 +666,7 @@
buffer &= ~FDI_LINK_TRAIN_NONE;
write32(txControl, buffer);
- write32(Receiver().Base() + PCH_FDI_RX_MISC,
- FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
+ write32(FDI_RX_MISC(fPipeIndex), FDI_RX_TP1_TO_TP2_48 |
FDI_RX_FDI_DELAY_90);
bool trained = false;
diff --git a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
index cc3a28f..62cb84b 100644
--- a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
+++ b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
@@ -25,11 +25,11 @@
void
EnablePLL(uint32 lanes);
void DisablePLL();
- uint32 Base()
-
{ return fRegisterBase; };
+ pipe_index PipeIndex()
+
{ return fPipeIndex; };
-private:
- uint32 fRegisterBase;
+protected:
+ pipe_index fPipeIndex;
};
@@ -47,11 +47,11 @@
void
SwitchClock(bool toPCDClock);
- uint32 Base()
-
{ return fRegisterBase; };
+ pipe_index PipeIndex()
+
{ return fPipeIndex; };
protected:
- uint32 fRegisterBase;
+ pipe_index fPipeIndex;
};
--
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Gerrit-Project: haiku
Gerrit-Branch: master
Gerrit-Change-Id: Ib7382240a2bc07dbbd2aed7647b06f14a6c5cb4c
Gerrit-Change-Number: 5335
Gerrit-PatchSet: 1
Gerrit-Owner: Jérôme Duval <jerome.duval@xxxxxxxxx>
Gerrit-MessageType: newchange
