[haiku-commits] BRANCH pdziepak-github.lock_elision [05061a6] headers/private/kernel/arch/x86 src/system/kernel/arch/x86
- From: pdziepak-github.lock_elision <community@xxxxxxxxxxxx>
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Fri, 12 Jul 2013 21:00:33 +0200 (CEST)
added 2 changesets to branch 'refs/remotes/pdziepak-github/lock_elision'
old head: 0000000000000000000000000000000000000000
new head: 05061a62994025df9554762b478958da7ad3ba79
overview: https://github.com/pdziepak/Haiku/compare/05061a6
----------------------------------------------------------------------------
8fba56e: x86: Detect Transactional Synchronization Extensions
Detect two features that are part of Transactional Synchronization
Extensions: Hardware Lock Elision and Restricted Transactional Memory.
05061a6: x86: Remove dead links to the CPUID flags descriptions
[ Pawel Dziepak <pdziepak@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
2 files changed, 14 insertions(+), 4 deletions(-)
headers/private/kernel/arch/x86/arch_cpu.h | 9 +++++----
src/system/kernel/arch/x86/arch_cpu.cpp | 9 +++++++++
############################################################################
Commit: 8fba56e54df634bb9a35d24c28fb7e05a99388f3
Author: Pawel Dziepak <pdziepak@xxxxxxxxxxx>
Date: Fri Jul 12 18:39:08 2013 UTC
x86: Detect Transactional Synchronization Extensions
Detect two features that are part of Transactional Synchronization
Extensions: Hardware Lock Elision and Restricted Transactional Memory.
----------------------------------------------------------------------------
diff --git a/headers/private/kernel/arch/x86/arch_cpu.h
b/headers/private/kernel/arch/x86/arch_cpu.h
index bc9f4c8..22afe17 100644
--- a/headers/private/kernel/arch/x86/arch_cpu.h
+++ b/headers/private/kernel/arch/x86/arch_cpu.h
@@ -157,6 +157,10 @@
#define IA32_FEATURE_APERFMPERF (1 << 0) //IA32_APERF, IA32_MPERF
#define IA32_FEATURE_EPB (1 << 3) //IA32_ENERGY_PERF_BIAS
+// x86 defined features from cpuid eax 7, ebx register
+#define IA32_FEATURE_HLE (1 << 4) // Hardware Lock Elision
+#define IA32_FEATURE_RTM (1 << 11) // Restricted Transactional Memory
+
// cr4 flags
#define IA32_CR4_PAE (1UL << 5)
#define IA32_CR4_GLOBAL_PAGES (1UL << 7)
@@ -241,6 +245,7 @@ enum x86_feature_type {
FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD)
FEATURE_6_EAX, // cpuid eax=6, eax registers
FEATURE_6_ECX, // cpuid eax=6, ecx registers
+ FEATURE_7_EBX, // cpuid eax=7, ebx registers
FEATURE_NUM
};
diff --git a/src/system/kernel/arch/x86/arch_cpu.cpp
b/src/system/kernel/arch/x86/arch_cpu.cpp
index 710307b..157baf3 100644
--- a/src/system/kernel/arch/x86/arch_cpu.cpp
+++ b/src/system/kernel/arch/x86/arch_cpu.cpp
@@ -500,6 +500,10 @@ dump_feature_string(int currentCPU, cpu_ent* cpu)
strlcat(features, "aperfmperf ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_EPB)
strlcat(features, "epb ", sizeof(features));
+ if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_HLE)
+ strlcat(features, "hle ", sizeof(features));
+ if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RTM)
+ strlcat(features, "rtm ", sizeof(features));
dprintf("CPU %d: features: %s\n", currentCPU, features);
}
@@ -621,6 +625,11 @@ detect_cpu(int currentCPU)
cpu->arch.feature[FEATURE_6_ECX] = cpuid.regs.ecx;
}
+ if (maxBasicLeaf >= 7) {
+ get_current_cpuid(&cpuid, 7);
+ cpu->arch.feature[FEATURE_7_EBX] = cpuid.regs.ebx;
+ }
+
#if DUMP_FEATURE_STRING
dump_feature_string(currentCPU, cpu);
#endif
############################################################################
Commit: 05061a62994025df9554762b478958da7ad3ba79
Author: Pawel Dziepak <pdziepak@xxxxxxxxxxx>
Date: Fri Jul 12 18:42:48 2013 UTC
x86: Remove dead links to the CPUID flags descriptions
----------------------------------------------------------------------------
diff --git a/headers/private/kernel/arch/x86/arch_cpu.h
b/headers/private/kernel/arch/x86/arch_cpu.h
index 22afe17..cf35b5e 100644
--- a/headers/private/kernel/arch/x86/arch_cpu.h
+++ b/headers/private/kernel/arch/x86/arch_cpu.h
@@ -56,7 +56,6 @@
#define K8_MSR_IPM 0xc0010055
// x86 features from cpuid eax 1, edx register
-// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table
5-5)
#define IA32_FEATURE_FPU (1 << 0) // x87 fpu
#define IA32_FEATURE_VME (1 << 1) // virtual 8086
#define IA32_FEATURE_DE (1 << 2) // debugging extensions
@@ -91,7 +90,6 @@
#define IA32_FEATURE_PBE (1 << 31) // pending break enable
// x86 features from cpuid eax 1, ecx register
-// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table
5-4)
#define IA32_FEATURE_EXT_SSE3 (1 << 0) // SSE3
#define IA32_FEATURE_EXT_PCLMULQDQ (1 << 1) // PCLMULQDQ Instruction
#define IA32_FEATURE_EXT_DTES64 (1 << 2) // 64-Bit Debug Store
@@ -144,7 +142,6 @@
| IA32_FEATURE_AMD_EXT_LONG)
// x86 defined features from cpuid eax 6, eax register
-// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table
5-11)
#define IA32_FEATURE_DTS (1 << 0) //Digital Thermal Sensor
#define IA32_FEATURE_ITB (1 << 1) //Intel Turbo Boost Technology
#define IA32_FEATURE_ARAT (1 << 2) //Always running APIC Timer
@@ -153,7 +150,6 @@
#define IA32_FEATURE_PTM (1 << 6) //Package Thermal Management
// x86 defined features from cpuid eax 6, ecx register
-// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table
5-11)
#define IA32_FEATURE_APERFMPERF (1 << 0) //IA32_APERF, IA32_MPERF
#define IA32_FEATURE_EPB (1 << 3) //IA32_ENERGY_PERF_BIAS
Other related posts:
- » [haiku-commits] BRANCH pdziepak-github.lock_elision [05061a6] headers/private/kernel/arch/x86 src/system/kernel/arch/x86 - pdziepak-github . lock_elision
