Hi there, I might be in the wrong place here, but what's known on the Haiku MTRR features setup? Do we have something yet? For instance: Dano/Zeta has modules for this in a folder named 'cpu/' somewhere (loaded by the app_server AFAIK). There is a general module, and three submodules for Intel, AMD and another manufacturor. R5 seems to have a app_Server internal solution(?) Some info: memory type range registers (so MTRR), the WC feature (Write_combining) is used for mapping the graphicscards framebuffer. This increases speed by say 140-200% by using burst writes or so. Only if WC is in use, AGP FW will further speedup access: without WC, AGP-FW has no influence on speed. I think Be never published the interface to the MTR module(s) as it's only in Dano officially. So: we need to setup something at some point, and I would go for modules indeed. We could come up with our own interface if no other option exists, as we also write our own app_server. In the end the whole would be compatible to R5, although the modules themselves will not be useable as drop-ins for Dano/Zeta. The immediate reason for me to ask questions at this time, is that I find myself looking into the subject because of missing VIA CPU MTRR support. BTW: I saw a driver on BeBits for some AMD CPU's that setup those MTRR's. This is a hack which requires the user to have a settings file that feeds this driver the location of the framebuffer, so it's mapping can use MTRR. The author obviously also had no access to Be info. Thanks for any hints/pointers/suggestions someone might have.. Rudolf.