Posts for si-list, 12-2011

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  1. » [SI-LIST] Re: surface roughness, Yuriy Shlepnev
  2. » [SI-LIST] Re: what level of overshoot is acceptalbe, ERIK KUNDRO
  3. » [SI-LIST] Re: SDD21 and SDD11, john lin
  4. » [SI-LIST] Interconnect Model for J971 (100MHz) Teradyne, Church, James
  5. » [SI-LIST] Latest Technical Tidbit - heat sink tines and EMC, Doug Smith
  6. » [SI-LIST] crosstalk and pcb placement of buses on high density pcb's, Bernadine Splettstoeszer
  7. » [SI-LIST] Estimating Crosstalk, Mark Filipov
  8. » [SI-LIST] Re: Fwd: How are you..., Ambr Amit
  9. » [SI-LIST] Number of bits to simulate, Roopesh Badala
  10. » [SI-LIST] s parameter causality problems, Megan Pecheny
  11. » [SI-LIST] Re: Number of bits to simulate, Hassan O . Ali
  12. » [SI-LIST] 2012 IEEE Radio Wireless Week in Santa Clara, CA, Eriko Yamato
  13. » [SI-LIST] Re: Estimating Crosstalk, Istvan Novak
  14. » [SI-LIST] True or False ? Breaking up coupling lengths so it is distributed over the length of the net yields less crosstalk than the same coupled length that is lumped/massed in one location., Bernadine Splettstoeszer
  15. » [SI-LIST] Signal Integrity Event, Helene Thibieroz
  16. » [SI-LIST] s-param validity response from company, Megan Pecheny
  17. » [SI-LIST] Looking For SI job in Southern California, ma mu
  18. » [SI-LIST] Stronger Resistor Vs Weaker Resistor, bala
  19. » [SI-LIST] Signal Integrity Jobs at Intel China Shenzhen, Shikun Liu
  20. » [SI-LIST] Employment Opportunity with Oracle (Burlington, MA), Jason Miller
  21. » [SI-LIST] Connect SGND and PGND on Digital DC/DC Converter?, Tomas Carlsson
  22. » [SI-LIST] Large dip in insertion loss curve for coupled microstrip traces, Mark Filipov
  23. » [SI-LIST] IBIS Summit at DesignCon 2012 - First Call for Participation and Presentations, Mirmak, Michael
  24. » [SI-LIST] Backchannel Training in IBIS-AMI Modeling, Ravinder . Ajmani
  25. » [SI-LIST] PCI Express reference clock, is it needed?, Pehr Andersson
  26. » [SI-LIST] ppm(parts per million)-Crystal OSC, bala
  27. » [SI-LIST] test, Mike LaBonte
  28. » [SI-LIST] scrambled clocks, piyush bhatt
  29. » [SI-LIST] DesignCon tutorial on SI - Analog Mixed Signal Track, Helene Thibieroz
  30. » [SI-LIST] CAF issue or not?, Filion, Marc-Andre
  31. » [SI-LIST] The question for HDMI compliance spec & Debuging method, 김창희
  32. » [SI-LIST] Interested in Signal integrity discussions, aruna bathini
  33. » [SI-LIST] SI Job Opportunity with Broadcom's Mobile Platforms Hardware Group, Sam Karikalan
  34. » [SI-LIST] Hysteresis Inputs, bala
  35. » [SI-LIST] Broadcom looking for SI / PI engineer with 10+ years of experience, PhD preferred, Patrick Zilaro
  36. » [SI-LIST] VHDL problem, Wang Chao
  37. » [SI-LIST] Static ? DCpower_Power dissipation, bala
  38. » [SI-LIST] DC Current Carrying Capacity of a PCB Throu-hole Via, Hirshtal Itzhak
  39. » [SI-LIST] DDR2 - 7 LOADS -suitable topology, Balamanikandan K
  40. » [SI-LIST] Power Integrity job opening at Qualcomm, Smith, Larry
  41. » [SI-LIST] Why"Void power and ground planes under discrete magnetic components", Tesla
  42. » [SI-LIST] FR4 limitations in high speed PCBs, Mohamad Haghtalab
  43. » [SI-LIST] About Common-mode insertion loss of differential mode S-parameter, Lucian Zhang
  44. » [SI-LIST] DDR setup time defination(pin or die), Tesla
  45. » [SI-LIST] WMED 2012, Tim Hollis (thollis)