Posts for si-list, 12-2005

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  1. » [SI-LIST] IBIS question, nrpatel
  2. » [SI-LIST] Re: DC resistance of the Power Supply on PCB, Andrew Ingraham
  3. » [SI-LIST] Re: NEXT and FEXT: Question on relative levels, Grasso, Charles
  4. » [SI-LIST] Mobile DDR specifications., Sanchayan Sinha
  5. » [SI-LIST] pcb board capacitors, david stern
  6. » [SI-LIST] stack up design with a field solver, Eric Bogatin
  7. » [SI-LIST] validation help, Mark Burford
  8. » [SI-LIST] Re: pcb board capacitors, Lee Ritchey
  9. » [SI-LIST] CR-5000 Lightning, mamontem
  10. » [SI-LIST] Impedance control, rana sadaf
  11. » [SI-LIST] Trace bandwidth, poornima poornima
  12. » [SI-LIST] Gigabit traces on Backplane, jain.nitin
  13. » [SI-LIST] Re: Gigabit traces on Backplane, steve weir
  14. » [SI-LIST] MLF packages, Vivek Chandra
  15. » [SI-LIST] Signal Integrity, Package design project in Santa Clara, Kevin Pierpoint
  16. » [SI-LIST] Back of the envelope termination resistor calculation, Alex Horvath
  17. » [SI-LIST] Re: Back of the envelope termination resistor calculation, Alex Horvath
  18. » [SI-LIST] Question of taking measurement. Thanks., Peng Ye
  19. » [SI-LIST] Re: MLF packages, Ray Anderson
  20. » [SI-LIST] Via inside SMD discrete, Naren Thesia
  21. » [SI-LIST] Application of copper tape for experimental use, Doug Smith
  22. » [SI-LIST] Re: Via inside SMD discrete, kfrobinson
  23. » [SI-LIST] High Aspect Ratio Problem in HFSS 9.0, kundanchand chand
  24. » [SI-LIST] Use of Yahoo and other non-specific email accounts, Dr. Edward P. Sayre
  25. » [SI-LIST] Re: Use of Yahoo and other non-specific email accounts, Peterson, James F (FL51)
  26. » [SI-LIST] Microstrip/Stripline, Babid A
  27. » [SI-LIST] Hi, jbtera77
  28. » [SI-LIST] USB waveform, Pradeep RSA
  29. » [SI-LIST] Re: USB waveform, Vijay S CHACHRA
  30. » [SI-LIST] Re: Microstrip/Stripline, Hassan O. Ali
  31. » [SI-LIST] Logic Analyzer headers XAUI & PCI-E, raja
  32. » [SI-LIST] Firewire 1394 eye mask, Ed Sayre III
  33. » [SI-LIST] Re: Hi, Lee Ritchey
  34. » [SI-LIST] Re: Firewire 1394 eye mask, Ray Anderson
  35. » [SI-LIST] 4-port node numbering, Ray Anderson
  36. » [SI-LIST] Re: 4-port node numbering, Grossman, Brett
  37. » [SI-LIST] effects of propagation time with respect to rise time, john matt
  38. » [SI-LIST] Q on V_fixture in IBIS model., Grasso, Charles
  39. » [SI-LIST] Re: Q on V_fixture in IBIS model., Muranyi, Arpad
  40. » [SI-LIST] Re: effects of propagation time with respect to rise time, Alex Horvath
  41. » [SI-LIST] development of test method standards to characterize probes, Nick Paulter
  42. » [SI-LIST] Timing analysis, m har
  43. » [SI-LIST] I/O Buffer in HSpice, nrpatel
  44. » [SI-LIST] PC debug port pinout?, Dr. Edward P. Sayre
  45. » [SI-LIST] Re: PC debug port pinout?, Ray Anderson
  46. » [SI-LIST] Impedance matching, Babid A
  47. » [SI-LIST] Re: Impedance matching, Suo, Ying (Ying)
  48. » [SI-LIST] GerbTool ACR question, Jim Antonellis
  49. » [SI-LIST] R: I/O Buffer in HSpice, Guasti Giovanni
  50. » [SI-LIST] Question about Echo cancellation testing, Jean_Pierre . Bouthemy
  51. » [SI-LIST] Pin Type Scope ground, Alex Horvath
  52. » [SI-LIST] Re: Pin Type Scope ground, Lee Ritchey
  53. » [SI-LIST] Re: Timing analysis, Edi Fraiman
  54. » [SI-LIST] Adding a capacitance between 2 transmission lines, Matthias Bergmann
  55. » [SI-LIST] Antwort: Re: Adding a capacitance between 2 transmission lines, Matthias Bergmann
  56. » [SI-LIST] FW: Re: Microstrip/Stripline, Ray Anderson
  57. » [SI-LIST] E1 EMI protection, Alex Horvath
  58. » [SI-LIST] Re: Dielctric loss microstip/stripline, Christopher.Jakubiec
  59. » [SI-LIST] Signal Integrity Job Opening, Brent Rogers
  60. » [SI-LIST] how to evaluate the lead inductance of chip packages, david
  61. » [SI-LIST] Question about termination of transmission line, Joey
  62. » [SI-LIST] Re: how to evaluate the lead inductance of chip packages, Lee Ritchey
  63. » [SI-LIST] Re: IBIS Models for the Devices working at GHz speed, Ken Willis
  64. » [SI-LIST] Re: Embedded Microstrip, Loyer, Jeff
  65. » [SI-LIST] Happy Holidays, Dr. Edward P. Sayre
  66. » [SI-LIST] Re: Happy Holidays, Chris Cheng
  67. » [SI-LIST] Rs in W-element, TerenceHsieh
  68. » [SI-LIST] Re: Rs in W-element, Jinghua Huang
  69. » [SI-LIST] Calling subcircuits in HSpice, nrpatel
  70. » [SI-LIST] Re: Calling subcircuits in HSpice, Frank Dunlap
  71. » [SI-LIST] XAUI, Ravindra Johari
  72. » [SI-LIST] Re: how to evaluate the lead inductance of chippackages, Lee Ritchey
  73. » [SI-LIST] Re: sorting thru the junk mail, Ray Anderson
  74. » [SI-LIST] Re: XAUI, Lee Ritchey
  75. » [SI-LIST] Re: Copper atom density, JaMi Smith
  76. » [SI-LIST] Hspice 2D EM Sim Vs. XFX 2D EM Sim, Guasti Giovanni
  77. » [SI-LIST] Hspice 2D Field Solver Vs. XFX, Guasti Giovanni
  78. » [SI-LIST] Re: Hspice 2D Field Solver Vs. XFX, Vijay Hosamani
  79. » [SI-LIST] Unsubscribe, Rich
  80. » [SI-LIST] Jon Powell, Lee Ritchey
  81. » [SI-LIST] Power Integrity- How to set Z target, Yosi Zanjiri
  82. » [SI-LIST] IBIS models needed, Antselovitch Joseph
  83. » [SI-LIST] PCI-X 1.0a simulation, Naren Thesia
  84. » [SI-LIST] Re: PCI-X 1.0a simulation, steve weir
  85. » [SI-LIST] Re: FW: Re: Microstrip/Stripline, Loyer, Jeff
  86. » [SI-LIST] Taking SI and timing specs at face value, Dr. Edward P. Sayre
  87. » [SI-LIST] Selection of Minimum Coupled Length in Cadence SPECCTRAQuest, Ravinder . Ajmani
  88. » [SI-LIST] Test DDR, Ravindra Johari
  89. » [SI-LIST] Re: Test DDR, Mehta, Darshan
  90. » [SI-LIST] Re: Selection of Minimum Coupled Length in Cadence SPECCTRAQuest, Aubrey_Sparkman
  91. » [SI-LIST] Unsubscribe - 2nd attempt, Rich