Posts for si-list, 11-2009

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  1. » [SI-LIST] Re: what's de-emphasis, prasad
  2. » [SI-LIST] Comments on these articles, please!, Karthik Raj Guruchandran
  3. » [SI-LIST] Re: Transmission line capacitance--> My Stripline and Microstrip PCB Calculator, Download Salkow's Freeware, Abe (Abbas) Riazi
  4. » [SI-LIST] Whai's the influence of AC couple capacitor, Zaiyi Liao
  5. » [SI-LIST] Re: coupling calculations, Han, Guobing
  6. » [SI-LIST] IBIS for PDN, Han, Guobing
  7. » [SI-LIST] Ripple current qn?, joe jose
  8. » [SI-LIST] dielectric constant FR4 ITEQ 180, Costel
  9. » [SI-LIST] DDR3 LA riser card, Heyfitch
  10. » [SI-LIST] set digest, Tom Zych
  11. » [SI-LIST] Re: EMI simulation using speed2K, Han, Guobing
  12. » [SI-LIST] Compensating phase diff caused by bends in LVDS signals, Morten Leikvoll
  13. » [SI-LIST] What's the influence of AC couple capacitor, Eric Bogatin
  14. » [SI-LIST] System Test Message, Ray Anderson
  15. » [SI-LIST] IBIS 5.0 support, Mike DeVita
  16. » [SI-LIST] Serial Link Webinar: Multi-Gigabit Design with Xilinx IBIS-AMI Models, Ronda Katz
  17. » [SI-LIST] USB2.0 HS signal integrity analysis, Rick Adolf
  18. » [SI-LIST] 10G Ethernet routing guideline, Sankar K
  19. » [SI-LIST] Query on Eye-Diagram of RX ADC, chundi srikanth
  20. » [SI-LIST] Re: IBIS 5.0 support, Ken Willis
  21. » [SI-LIST] XAUI Routing guidelines and plane considerations on next layers, Rama Mohan Reddy Boreddy
  22. » [SI-LIST] measuring resonant frequencies of cables, Doug Smith
  23. » [SI-LIST] Senior Signal Integrity Jobs at Cisco, San Jose, CA, Amit Agrawal (amiagra2)
  24. » [SI-LIST] Found new simulation site, Doug Smith
  25. » [SI-LIST] relative permittivity, Fatemeh Tabatabaei
  26. » [SI-LIST] Open Design Positions at Freescale Semiconductor Inc., Aaen Peter-R40889
  27. » [SI-LIST] FPGA Camp is 2 days away - 11/11 - silicon valley (Free) - Dinner provided, Vikram Singh
  28. » [SI-LIST] Signal Integrity positions at Amphenol TCS, John Lehman
  29. » [SI-LIST] Re: Book - "Signal Integrity for PCB Designers" offered at low cost, V S
  30. » [SI-LIST] S-parameter Bisection, Moeller, Merrick
  31. » [SI-LIST] WG: S-parameter Bisection, Havermann, Gert
  32. » [SI-LIST] LAST CHANCE TO REGISTER-Serial Link Webinar: Multi-Gigabit Design with Xilinx IBIS-AMI Models, Ronda Katz
  33. » [SI-LIST] jitter tolerance, Sankar K
  34. » [SI-LIST] Re: S-parameter Bisection, Hassan O . Ali
  35. » [SI-LIST] Power Plane inductance, narasimha rao
  36. » [SI-LIST] SDRAM connection topolgy on PCB, Sumathi Kuppuswamy
  37. » [SI-LIST] Free Webinar on Simulation and Timing for Signal Integrity, Timothy Coyle
  38. » [SI-LIST] SI Engineer needed at Intel Server Design, Garrison, Gene
  39. » [SI-LIST] SI Engineer needed at Intel Server Design - CORRECTED LINK, Garrison, Gene
  40. » [SI-LIST] LVDS TL Impedance doubt, Mohamad Haghtalab
  41. » [SI-LIST] RGMII length match guide lines, shivaraj k
  42. » [SI-LIST] PCI/PMC Signal Routing Question, Ross, Craig (EHCOE)
  43. » [SI-LIST] DRC ERROR [ NET 0016 ], jagaveera kumar
  44. » [SI-LIST] Maximum length of 2.5G SerDes trace, Mashook Ahamed Usman
  45. » [SI-LIST] Re: Maximum length of 2.5G SerDes trace, Lee Ritchey
  46. » [SI-LIST] Fast rise time buffer, Kihong Joshua Kim
  47. » [SI-LIST] AC Blocking capacitor relative positions and reference plane voids, jean-francois hasson
  48. » [SI-LIST] FW: AC Blocking capacitor relative positions and reference plane voids, Haller, Robert
  49. » [SI-LIST] Re: AC Blocking capacitor relative positions and reference plane voids, Lee Ritchey
  50. » [SI-LIST] Re: FW: AC Blocking capacitor relative positions andreference plane voids, Lee Ritchey
  51. » [SI-LIST] How does S-parameter influence eyepattern, Zaiyi Liao
  52. » [SI-LIST] mixed-signal RF tuner + digital demodulator layout specification, jweta
  53. » [SI-LIST] Re: FW: AC Blocking capacitor relative positions andreferenceplane voids, Lee Ritchey
  54. » [SI-LIST] REF Clock "total phase jitter" requirement for SATA, Eddy
  55. » [SI-LIST] Via model, Zaiyi Liao
  56. » [SI-LIST] Re: FW: AC Blocking capacitor relative positions andreferenceplanevoids, Lee Ritchey
  57. » [SI-LIST] Signal processing, Jennifer Maharani
  58. » [SI-LIST] Re: Signal processing, Jennifer Maharani
  59. » [SI-LIST] Re: FW: AC Blocking capacitor relative positionsandreferenceplanevoids, Lee Ritchey
  60. » [SI-LIST] DDR2 vs. DDR3, Jennifer Maharani
  61. » [SI-LIST] Multi-Giga-Hertz Rigid-Flex Feasibility, Hirshtal Itzhak
  62. » [SI-LIST] Upcoming SI workshops., wcmartin1
  63. » [SI-LIST] ODT in DDR3, prasad
  64. » [SI-LIST] Which tool is good for long SAS cable model?, Neo
  65. » [SI-LIST] SAS Cable Geometric Spec, Neo
  66. » [SI-LIST] Signal Integrity in 150 B.C., colin_warwick
  67. » [SI-LIST] Microstrip to stripline transition related question, jean-francois hasson
  68. » [SI-LIST] Re: Microstrip to stripline transition related question, Hany Fahmy
  69. » [SI-LIST] Re: AW: Multi-Giga-Hertz Rigid-Flex Feasibility, Lee Ritchey