Posts for si-list, 11-2006

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  1. » [SI-LIST] Electrical Design of Advanced Packaging and Systems (EDAPS), Madhavan Swaminathan
  2. » [SI-LIST] flip chip model for DDR3, Nidhir Kumar
  3. » [SI-LIST] Leading Insight Northwest - Ansoft Application Workship - Nov. 14 in Beaverton, OR, Andrew Byers
  4. » [SI-LIST] DDR Interface Topology, Bingipur, Arjun
  5. » [SI-LIST] one problem about ESD simulation, chenglubeijing
  6. » [SI-LIST] How to simulate ESD test of one chip CMOS chip, ChrisCheng
  7. » [SI-LIST] Signal Integrity Position - Andover MA, Haller, Robert
  8. » [SI-LIST] A question for the instrument guys on TDR and TDT, Chris Cheng
  9. » [SI-LIST] AMD Hiring SI Engineer, jworth
  10. » [SI-LIST] Re: A question for the instrument guys on TDR and TDT, Chris Cheng
  11. » [SI-LIST] Hi, janani
  12. » [SI-LIST] hai test mail, Abin.CV
  13. » [SI-LIST] SSO corner cases, Canes Venatici
  14. » [SI-LIST] TEST MAIL, Girish gopi
  15. » [SI-LIST] Re: Heatsink electrical isolation, Hill, John
  16. » [SI-LIST] Re: How to simulate ESD test of one chip CMOS chip, Grasso, Charles
  17. » [SI-LIST] Signal and Power Integrity Applications Engineer Vacancy, marcekowalski
  18. » [SI-LIST] User2User 2007 Call4Papers ..., Hargin, Bill
  19. » [SI-LIST] Board/DVT project in San Jose, CA, Kevin Pierpoint
  20. » [SI-LIST] How to evaluate IBIS model, Zhangkun
  21. » [SI-LIST] Re: How to evaluate IBIS model, Muranyi, Arpad
  22. » [SI-LIST] RF shapes behaviour at high speeds, chand basha
  23. » [SI-LIST] Conductor loss or Dielectric loss, hkkim
  24. » [SI-LIST] Trace length problem, lijingdea
  25. » [SI-LIST] Hi Test, Partha Simon
  26. » [SI-LIST] Re: Trace length problem, Muranyi, Arpad
  27. » [SI-LIST] Job opening: Signal Integrity Engineer, Tanmoy Roy
  28. » [SI-LIST] Copper pours on a 2-layer PCB, Carlos Toro
  29. » [SI-LIST] Novel chip-to-chip interconnect hits 10 Gbit/s, rbmerrit
  30. » [SI-LIST] Package SI, Madhusudhan Kulkarni
  31. » [SI-LIST] Re: Fwd: Re: Copper pours on a 2-layer PCB, Carlos Toro
  32. » [SI-LIST] EMI/EMC Seminar, Surendra
  33. » [SI-LIST] EMC engineer position open in Shanghai, China, Howard Ji \(howardji\)
  34. » [SI-LIST] Recall: EMC engineer position open in Shanghai, China, Howard Ji \(howardji\)
  35. » [SI-LIST] COMMANDS, Richard Kroposki
  36. » [SI-LIST] UNSUBSCRIBE, Richard Kroposki
  37. » [SI-LIST] Series resistor b/w grounds, nagaraj
  38. » [SI-LIST] How to generate IBIS model, Gang Sun
  39. » [SI-LIST] Fiber transceiver assemblies, fully assembled?, Steven Kan
  40. » [SI-LIST] ddr2 2 sodimm design - clk to add&control signals metcing, Moshe Frid
  41. » [SI-LIST] Re: How to generate IBIS model, Abdulrahman Rafiq -X \(arafiq - Digital-X, Inc. at Cisco\)
  42. » [SI-LIST] immediate opening for Board Design Lead, Josh Nickel
  43. » [SI-LIST] Buffer delay, yan hang
  44. » [SI-LIST] Re: Buffer delay, Mirmak, Michael
  45. » [SI-LIST] noise/emi getting into signal measurements, Doug Smith
  46. » [SI-LIST] About S2ibis2, james cui
  47. » [SI-LIST] Thick vs. thin diff. pairs, Mark Burford
  48. » [SI-LIST] Re: Thick vs. thin diff. pairs, Christopher McGrath
  49. » [SI-LIST] Trace impedance, shekhar sharma
  50. » [SI-LIST] 回复:Statistical Timing Budgets Analysis, zhangkun 29902
  51. » [SI-LIST] Statistical Timing Budgets Analysis, wad
  52. » [SI-LIST] SI job posting, Celestica, Ottawa ON, Kai Keskinen
  53. » [SI-LIST] Why no timing model available unitl now?, Peter Zhu (Zhu Yonghui)
  54. » [SI-LIST] Re: Trace impedance, Grasso, Charles
  55. » [SI-LIST] A New Open Source SI Analysis Tool, Charles Eidsness
  56. » [SI-LIST] Differential IBIS model (with pre-emphasis) generation, david horan
  57. » [SI-LIST] Trace width for 20 amps, RameshK Cozerv IN HO
  58. » [SI-LIST] PICMG3.1 : is length matching really necessary?, Daniel . Peron
  59. » [SI-LIST] Slew Rate Calculation, Bingipur, Arjun
  60. » [SI-LIST] Test Mail Please Ignore, ChandraKanth Gajawada
  61. » [SI-LIST] ESD simulations, Canes Venatici
  62. » [SI-LIST] hspi new release, Ke Wang
  63. » [SI-LIST] Re: hspi new release, Ke Wang
  64. » [SI-LIST] si-list web site address change, Ray Anderson
  65. » [SI-LIST] Re: ESD simulations, Yafei Bi
  66. » [SI-LIST] Re: About S2ibis2, james cui
  67. » [SI-LIST] Patents on backplane, via design, misc..., Bill Dempsey
  68. » [SI-LIST] Re: PICMG3.1 : is length matching really necessary?, Daniel . Peron
  69. » [SI-LIST] digital core model, Saoer Sinaga
  70. » [SI-LIST] Re: R: Re: R: digital core model, Yafei Bi
  71. » [SI-LIST] Re: Slew Rate Calculation, Bingipur, Arjun
  72. » [SI-LIST] trace length matching, p_pornchai
  73. » [SI-LIST] use of PVT corner models for various speed-grades, Zabinski, Patrick
  74. » [SI-LIST] Re: trace length matching, syedmhusain
  75. » [SI-LIST] Electrical Engineering Manger, bruce harvie
  76. » [SI-LIST] Package signal integrity position at NXP, Chris Wyland
  77. » [SI-LIST] DDR2 IMPEDANCE, Kenny Frohlich