Posts for si-list, 10-2002

  1. Home
  2. si-list
  3. Archive
  4. 10-2002

Browse: Last Month: 09-2002    Main Archive Page    Next Month: 11-2002

By Date / By Date Reverse / By Threads

  1. » [SI-LIST] Re: 2.5Gbit connectors and cables, Gil Gafni
  2. » [SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM, Jineshwari B - CTD, Chennai.
  3. » [SI-LIST] BC Fabricator in Hong Kong, Peter Baxter
  4. » [SI-LIST] Re: Planar DDR and LVTTL I/O, jim freeman
  5. » [SI-LIST] Re: SI job opportunity: Technical Marketing Engineer, Dima Smolyansky
  6. » [SI-LIST] SI job opportunity: Technical Marketing Engineer, Dima Smolyansky
  7. » [SI-LIST] Jitter Characterization on a Tester?, Jay Shenoy
  8. » [SI-LIST] Differential microstrip with coplanar ground traces ... unexpected results, Bob Welte
  9. » [SI-LIST] Re: Jitter Characterization on a Tester?, Ingraham, Andrew
  10. » [SI-LIST] Re: Differential microstrip with coplanar ground traces ... une..., MikonCons
  11. » [SI-LIST] Re: Differential microstrip with coplanar ground traces, MikonCons
  12. » [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpected results, Loyer, Jeff
  13. » [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpec..., MikonCons
  14. » [SI-LIST] RMCEMC October Meeting, Charles Grasso
  15. » [SI-LIST] Hyper Transport Probe, Raja
  16. » [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpectedresults, Bob Welte
  17. » [SI-LIST] Re: Hyper Transport Probe, evillaf
  18. » [SI-LIST] Receiver/transmitter offset-sensitivity, Gupta, Naveen
  19. » [SI-LIST] FW: Innoveda User's Groups, Chuck Reynolds
  20. » [SI-LIST] Resume for Design/Applications Engineer, Uzma Khan
  21. » [SI-LIST] How to measure package impedance or characteristic for a chip?, =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
  22. » [SI-LIST] PWB coupling to system enclosures, Douglas C. Smith
  23. » [SI-LIST] test -- please ignore this mail, flin
  24. » [SI-LIST] Eye pattern with HSPICE, Gil Gafni
  25. » [SI-LIST] Re: Eye pattern with HSPICE, Clewell, Craig
  26. » [SI-LIST] Hyper Transport Probe Details, Raja
  27. » [SI-LIST] Unconnected pins in a connector carrying differential signals, Jineshwari Baratharajan
  28. » [SI-LIST] Creating IBIS models for a fee?, Mike Cantwell
  29. » [SI-LIST] Re: Unconnected pins in a connector carrying differential signals, Ingraham, Andrew
  30. » [SI-LIST] How to???, Kevin Buchanan
  31. » [SI-LIST] Re: Differential microstrip with coplanar ground traces... unexpected results, Scott McMorrow
  32. » [SI-LIST] Class on Gigabit design at PCB East, Scott McMorrow
  33. » [SI-LIST] Re: Differential pair impedance, Pat Diao
  34. » [SI-LIST] Why 220ohms at driver end in PECL Terminations, Jineshwari B - CTD, Chennai.
  35. » [SI-LIST] Recall: Why 220ohms at driver end in PECL Terminations, Jineshwari B - CTD, Chennai.
  36. » [SI-LIST] Re: Why 220ohms at driver end in PECL Terminations, Stuart Brorson
  37. » [SI-LIST] RE How to, Kevin Buchanan
  38. » [SI-LIST] Interface of Microphone with Codec, Adeel Malik
  39. » [SI-LIST] AC Waveform question, Doug Brooks
  40. » [SI-LIST] Re: AC Waveform question, Zabinski, Patrick J.
  41. » [SI-LIST] AC Waveform question, clarification, Doug Brooks
  42. » [SI-LIST] Re: How to measure package impedance or characteristic for a chip?, Quyen Vu
  43. » [SI-LIST] test, Adeel Malik
  44. » [SI-LIST] Some Querries regarding Xtalk in traces, Anshuli Goel
  45. » [SI-LIST] complex numbers, Alicia Corrales Chanca
  46. » [SI-LIST] Hi all, Sathish
  47. » [SI-LIST] analog / mixed signal simulation, Roger_Wu
  48. » [SI-LIST] Re: Serpentine Traces, Jack W.C. Lin
  49. » [SI-LIST] how to reduce hspice run-time?, Yoni Tzafrir
  50. » [SI-LIST] Package Parasitics of 168-PIN DIMM Socket, Adeel Malik
  51. » [SI-LIST] 2D transmission line theory, Zhangkun
  52. » [SI-LIST] Antw: Package Parasitics of 168-PIN DIMM Socket, Robert Nowak
  53. » [SI-LIST] Re: how to reduce hspice run-time?, Clewell, Craig
  54. » [SI-LIST] Re: 2D transmission line theory, Jeff Jones
  55. » [SI-LIST] Re: Antw: Package Parasitics of 168-PIN DIMM Socket, Clewell, Craig
  56. » [SI-LIST] 20H Rule theoretically investigated with simulation., Doug McKean
  57. » [SI-LIST] "Line Errors" in Gigabit Ethernet, Gupta, Naveen
  58. » [SI-LIST] Re: 20H Rule theoretically investigated with simulation., Doug McKean
  59. » [SI-LIST] Re: Package Parasitics of 168-PIN DIMM Socket, Gregory R Edlund
  60. » [SI-LIST] Re: SPICE on the cheap?, Stuart Brorson
  61. » [SI-LIST] Other mailing lists for system-level SI issues?, Steven Kan
  62. » [SI-LIST] Re: Other mailing lists for system-level SI issues?, Ray Anderson
  63. » [SI-LIST] Recommendation for edge launched SMA connector for 0.093" board., Vipul Badoni
  64. » [SI-LIST] Why SSTL_2 does not need 1_25V Pull Up in AGP card?, Jack W.C. Lin
  65. » [SI-LIST] Re: Why SSTL_2 does not need 1_25V Pull Up in AGP card?, chris . mcgrath
  66. » [SI-LIST] Opportunity query, SDSIGUY
  67. » [SI-LIST] AC Coupling Capacitors for LVPECL Signals, Jineshwari B - CTD, Chennai.
  68. » [SI-LIST] The model of Cat 5 UTP cable, Nekrylova, Julia
  69. » [SI-LIST] Re: The model of Cat 5 UTP cable, Jerry Martinson
  70. » [SI-LIST] Re: SPICE on the cheap, Jay Shenoy
  71. » [SI-LIST] Re: AC Coupling Capacitors for LVPECL Signals, Steven Kan
  72. » [SI-LIST] Impedance calculation of asymmetric coupled lines?, D G
  73. » [SI-LIST] New Senior Signal Integrity Positions available in AustinTX...., Michael_Greim
  74. » [SI-LIST] Re: Impedance calculation of asymmetric coupled lines?, D G
  75. » [SI-LIST] HSpice Models in SPECCTRAQuest, Andreas Grübl
  76. » [SI-LIST] Re: HSpice Models in SPECCTRAQuest, Ray Anderson
  77. » [SI-LIST] CosmoScope, Khalid Ansari
  78. » [SI-LIST] Reenviar: RESUME, mmirfan
  79. » [SI-LIST] RESUME, mmirfan
  80. » [SI-LIST] What must be considered for simulation of 5Gbit differential signals on FR-4 PCB?, =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
  81. » [SI-LIST] Re: New Senior Signal Integrity Positions available in AustinTX. ...and more!!, Michael_Greim
  82. » [SI-LIST] running scripts with CosmoScope & Hspice, Yoni Tzafrir
  83. » [SI-LIST] JOB OPPORTUNITIES THAT DO NOT EXIST (VAPOR JOBS), simsoc radt
  84. » [SI-LIST] Sigrity Extends Offer for Free Training of SI Tools, Teo Yatman
  85. » (no subject), mmirfan
  86. » [SI-LIST] Question Regarding Some IBIS Parameters, Timothy Coyle
  87. » [SI-LIST] Search for a part, Adeel Malik
  88. » [SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR, Jack W.C. Lin
  89. » [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR, Jack W.C. Lin
  90. » [SI-LIST] AW: Question Regarding Some IBIS Parameters, Lenski Eckhard
  91. » [SI-LIST] Re: AW: Question Regarding Some IBIS Parameters, Timothy Coyle
  92. » [SI-LIST] Pick & Place Machines operation, Adeel Malik
  93. » [SI-LIST] How to Verify C_comp, Timothy Coyle
  94. » [SI-LIST] Re: Pick & Place Machines operation, Matthew Humphreys
  95. » [SI-LIST] Beyond Rail Operation in IBIS, Abhijit Mahajan
  96. » [SI-LIST] Re: Beyond Rail Operation in IBIS, Volk, Andrew M
  97. » [SI-LIST] Senior SI Positions with TI in Austin, Brian Young
  98. » [SI-LIST] Re: Impedance calculation of asymmetric coupled lin es?, houfei chen
  99. » [SI-LIST] Re: How to Verify C_comp, Gregory R Edlund
  100. » [SI-LIST] Low inductance chip capacitor(LICC), Perry Qu
  101. » [SI-LIST] Re: Low inductance chip capacitor(LICC), Larry Smith
  102. » [SI-LIST] Differential trace route question, Doug Brooks
  103. » [SI-LIST] Re: Low inductance chip capacitor(LICC), IDC, Istvan Novak - Board Design Technology
  104. » [SI-LIST] Re: Differential trace route question, Lewandowski, Bob
  105. » [SI-LIST] Interfacing Single ended PECL signal to differential PECL pair, Nagammai Periya Karuppan. - CTD, Chennai.
  106. » [SI-LIST] Re: Differential trace route question, christopher . heard
  107. » [SI-LIST] Re: Interfacing Single ended PECL signal to differential PECL pair, Bill Dempsey
  108. » [SI-LIST] AC Coupling and Differential Pair's Termination, ggafni
  109. » [SI-LIST] SMA replacement, Kikito Vertiginopulos
  110. » [SI-LIST] Re: SMA replacement, Ray Anderson
  111. » [SI-LIST] Re: AC Coupling and Differential Pair's Termination, James_R_Jones
  112. » [SI-LIST] W-element, ttsp
  113. » [SI-LIST] Re: W-element, Beal, Weston
  114. » [SI-LIST] Help:Who has these models?, Zhangmin Zhong
  115. » [SI-LIST] Re: Help:Who has these models?, eric . rushbrook
  116. » [SI-LIST] [SI-LIST]Same Pin Number connected to more than one net., Alicia Corrales Chanca
  117. » [SI-LIST] Occurrence-specific properties on SCHEMATIC1/V1, ignoring, Alicia Corrales Chanca
  118. » [SI-LIST] Re: Occurrence-specific properties on SCHEMATIC1/V1, ignoring, Bill Dempsey
  119. » [SI-LIST] Re: Need a tool to calculate trace inductance., ttsp
  120. » [SI-LIST] MODEL SELECT -- In IBIS and XTK, Siva kumar
  121. » [SI-LIST] Re: input capacitance representation in IBIS, PRIEUR, Olivier
  122. » [SI-LIST] EM simulator software?, Rafael Martinez
  123. » [SI-LIST] Re: EM simulator software?, D G
  124. » [SI-LIST] pwr-gnd loop inductance measurment, Jean Audet
  125. » [SI-LIST] Re: pwr-gnd loop inductance measurment, Clewell, Craig
  126. » [SI-LIST] Pads layout to HSPICE postroute, Siva kumar
  127. » [SI-LIST] Re: Interfacing Single ended PECL signal to differenti, Steven Kan
  128. » [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ?, Paliakara, Vinod
  129. » [SI-LIST] Multi-Plane Equivalent Capacitance in BGA Package, porshs
  130. » [SI-LIST] Reaching 2 Gbps out of a single-ended interface, Stephane Tremblay
  131. » [SI-LIST] IBIS Seminar, Lynne Green
  132. » [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface, Jean Audet
  133. » [SI-LIST] pwr-gnd loop inductance measurement, Eric Bogatin
  134. » [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface, Jean Audet
  135. » [SI-LIST] Re: [IBIS] IBIS Seminar, Lynne Green
  136. » [SI-LIST] Re: pwr-gnd loop inductance measurement, Chris Cheng
  137. » [SI-LIST] Re: Actual experience with LVDS to optical serializers with LVPECL inputs, Muhammad Sagarwala
  138. » [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface, Bill . Cohen
  139. » [SI-LIST] About via model!, Jack W.C. Lin
  140. » [SI-LIST] SPARTAN IIE Voltage regulator selection, Ismail B - CTD, Chennai.
  141. » [SI-LIST] Antw: SPARTAN IIE Voltage regulator selection, Robert Nowak
  142. » [SI-LIST] how to derive eye diagram, Moby Abraham
  143. » [SI-LIST] Re: SPARTAN IIE Voltage regulator selection, Tegan Campbell
  144. » [SI-LIST] Determining load line for LVDS IBIS Device, Timothy Coyle
  145. » [SI-LIST] Re: Determining load line for LVDS IBIS Device, Beal, Weston
  146. » [SI-LIST] Re: Multi Board Simulation with DIMM Board from Micron Tech, tcrondeau
  147. » [SI-LIST] Re: High-Speed Communications Alliance, jeff_latourrette
  148. » [SI-LIST] ODD Power Splitter, Julio
  149. » [SI-LIST] Max curent allowed in solder ball, Moses Chan
  150. » [SI-LIST] Re: ODD Power Splitter, ray_waugh
  151. » [SI-LIST] The maximum length of a bus?, C.Y. Cheng
  152. » [SI-LIST] spice model of tantalum capacitor, Zhangkun
  153. » [SI-LIST] Re: The maximum length of a bus?, C.Y. Cheng
  154. » [SI-LIST] LVPECL to 1.8V HSTL Conversion, Jineshwari B - CTD, Chennai.
  155. » [SI-LIST] Recall: LVPECL to 1.8V HSTL Conversion, Jineshwari B - CTD, Chennai.
  156. » [SI-LIST] Re: spice model of tantalum capacitor, michael . g . mcdermott
  157. » [SI-LIST] Re: LVPECL to 1.8V HSTL Conversion, Ingraham, Andrew
  158. » [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter?, Ray Anderson
  159. » [SI-LIST] New Buried Capacitance Material, Zenklusen, Fred
  160. » [SI-LIST] Re: New Buried Capacitance Material, Zenklusen, Fred
  161. » [SI-LIST] help! hold time calculation of source synchronous timing, =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
  162. » [SI-LIST] Re: help! hold time calculation of source synchronous timing, =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
  163. » [SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter?, Gupta, Deepali
  164. » [SI-LIST] Re: Why we need to use "Series resistor" atTransmitter?, Bill Reams
  165. » [SI-LIST] Re: How to connect to GND planes, Stephane Tremblay
  166. » [SI-LIST] Agilent HPFC5200D or Tachyon XLII, Ritchey Lee
  167. » [SI-LIST] IBIS model generation from Datasheet? How?, Inmyung Song
  168. » [SI-LIST] ESD shielding of the board, Roger_Wu
  169. » [SI-LIST] spatial resolution and effective rise time of VNA with TDR time-domainoption, Jan Vercammen
  170. » [SI-LIST] spice math question, John Ellis
  171. » [SI-LIST] Re: spice math question, Ingraham, Andrew
  172. » [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option, Istvan Novak - Board Design Technology
  173. » [SI-LIST] Re: Routing a 125MHz bus with 1 Bidir, 2 Rcvrs and an input vector, Douglas Burns
  174. » [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option, D G
  175. » [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option, D G
  176. » [SI-LIST] FET Probe, James_R_Jones
  177. » [SI-LIST] Xilinx Virtex2 driver spice models, Fasig, Jonathan L.
  178. » [SI-LIST] Re: FET Probe, Ingraham, Andrew