Posts for si-list, 09-2014

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  1. » [SI-LIST] Re: understanding acceptable amount of jitter for given receiver/system, Jory McKinley
  2. » [SI-LIST] Has anyone Compiled a Loss-Budget List?, Bill Hargin (Nan Ya, USA)
  3. » [SI-LIST] options for reducing EMI, Chen, Sherman
  4. » [SI-LIST] My new YouTube video and GoToMeeting discussion, Doug Smith
  5. » [SI-LIST] Need s-parameter model, bala
  6. » [SI-LIST] Free Signal Integrity Analysis Workshops in September from ANSYS, Margaret Schmitt
  7. » [SI-LIST] Default tap settings for SerDes, Mario Antolos
  8. » [SI-LIST] Caution to those who live outside of California and got there on business!!! (Don't), Doug Smith
  9. » [SI-LIST] Re: SerDes Speed Limitation, icer world
  10. » [SI-LIST] timing in s-parameters, eric silist
  11. » [SI-LIST] Senior SI engineer and internship position available in HP Storage Division, Cheng, Chris
  12. » [SI-LIST] IEEE EDAPS 2014 (Bangalore) Deadline Extended to 12th Sep, Dipanjan Gope
  13. » [SI-LIST] Re: IEEE EDAPS 2014 (Bangalore) Deadline Extended to 12th Sep, Dipanjan Gope
  14. » [SI-LIST] composite NTSC PAL encoder SI simulation model suggestion, Aramareddy Sreekanth reddy
  15. » [SI-LIST] Any SI seminars in the Bay Area, Hithesh
  16. » [SI-LIST] One stitching via or more vias is better for 25Gbps application???, Leeyuyun
  17. » [SI-LIST] Re: One stitching via or more vias is better for 25Gbps application???, steve weir
  18. » [SI-LIST] Re: One stitching via or more vias is better for 25Gbps, David Banas
  19. » [SI-LIST] One stitching via or more vias is better for 25Gbps, Eric Bogatin
  20. » [SI-LIST] free Teledyne LeCroy jitter webinar with Bogatin and Blankman Sept 9, Eric Bogatin
  21. » [SI-LIST] Board design adjustments by manufacturers, Yuriy Shlepnev
  22. » [SI-LIST] Archives for SI LIST, Anto Davis
  23. » [SI-LIST] Improving SNR in Audio signals-PCB, Saravanan Chml
  24. » [SI-LIST] Re: Any SI seminars in the Bay Area, heidi_barnes
  25. » [SI-LIST] free Keysight Technologies (formerly Agilent) Signal Integrity EDA Seminar in Santa Clara on 9/16 and 9/18, heidi_barnes
  26. » [SI-LIST] EM simulation for Waterloo, Ontario RF and SI engineers, David Vye
  27. » [SI-LIST] Ferrite Beads on Differential Signal Lines?, Craig Francis
  28. » [SI-LIST] Re: Ferrite Beads on Differential Signal Lines?, billg12@xxxxxxxxxxxxx
  29. » [SI-LIST] Fwd: Re: Re: Ferrite Beads on Differential Signal Lines?, steve weir
  30. » [SI-LIST] How to add excitation for helix coil, 王文松
  31. » [SI-LIST] Need a equation of inductance calculation for microstrip over the ground plane, 王文松
  32. » [SI-LIST] Noise coupling from TI's MSP430FR5728 MCU to TI's DS100BR210 repeater, Jinhua Chen
  33. » [SI-LIST] Minimizing EMI through Effective Signal and Power Integrity -- Upcoming Seminar from ANSYS & Zuken, Margaret Schmitt
  34. » [SI-LIST] Career opportunity for a new SI Applications Developer position at Keysight EEsof EDA (formerly Agilent EEsof EDA), colin_warwick
  35. » [SI-LIST] Re: Big things are happening at Teraspeed Consulting, Scott McMorrow
  36. » [SI-LIST] Question about common mode termination of Ethernet transformers, Joel Brown
  37. » [SI-LIST] Asian IBIS Summit (Shanghai) - First Announcement, Bob Ross
  38. » [SI-LIST] Re: si-list Digest V14 #214, Eric Tollefson
  39. » [SI-LIST] Webcast: How to Optimize Your SerDes Design During the Pre-layout Phase, colin_warwick
  40. » [SI-LIST] impedance determination of a perticular interface....., Mallikarjun K
  41. » [SI-LIST] Multi Billion Dollar Company That Uses Only Multiplexers As Basic Components, Lucky M
  42. » [SI-LIST] 2015 IEEE USA Symposium on Electromagnetic Compatibility and Signal Integrity Call for Hardware Experiments and Software Demonstrations., Giuseppe Selli (giselli)
  43. » [SI-LIST] rules of thumb in SI Bogatin EDN column, Eric Bogatin
  44. » [SI-LIST] Re: Multi Billion Dollar Company That Uses Only Multiplexers, Hal Murray
  45. » [SI-LIST] Asian IBIS Summit (Taipei) - First Announcement, Bob Ross
  46. » [SI-LIST] DGCON 2014 November 24-25, Israel, Dudi Tash
  47. » [SI-LIST] Where SSTL_15 (DDR3 1.5V SSTL standard) is available ..?, Mallikarjun K
  48. » [SI-LIST] Signal Integrity senior year project examples, Lucky M
  49. » [SI-LIST] plotting large amount of s-parameters, Arnav Shah -X (arnshah - BBI TECHNOLOGIES INC at Cisco)
  50. » [SI-LIST] ESD failure - need advise, Ramesh N
  51. » [SI-LIST] Asian IBIS Summit (Yokohama) - First Announcement, Bob Ross
  52. » [SI-LIST] Senior SI/PI Engineer Openings, Gordon Xiang
  53. » [SI-LIST] Re: Senior SI/PI Engineer Openings, Gordon Xiang
  54. » [SI-LIST] bit inversion in DDR3, Sanjay G
  55. » [SI-LIST] interactive design and debbuging session, Douglas Smith