Posts for si-list, 09-2002

  1. Home
  2. si-list
  3. Archive
  4. 09-2002

Browse: Last Month: 08-2002    Main Archive Page    Next Month: 10-2002

By Date / By Date Reverse / By Threads

  1. » [SI-LIST] Re: General Trace Impedance, Kedar P. Apte
  2. » [SI-LIST] Questions about Power Distribution, Stefano Riccardi
  3. » [SI-LIST] Re: We ought to address mutual SI-EMI issues in this forum, istvan novak
  4. » [SI-LIST] 3.125Gbps trace routing, hwp
  5. » [SI-LIST] IBIS modeling services providers, Craciun, Liviu-Dumitru
  6. » [SI-LIST] Antw: IBIS modeling services providers, Robert Nowak
  7. » [SI-LIST] Rj-45 connectors isolation properties, Jan Vercammen
  8. » [SI-LIST] Re: IBIS modeling services providers, Clewell, Craig
  9. » [SI-LIST] edge slope in eye diagram, Nosovitski, Alexander
  10. » [SI-LIST] AW: Rj-45 connectors isolation properties, Thomas Beneken
  11. » [SI-LIST] Startup time of SAW Resonators, Himanshu Arora
  12. » [SI-LIST] Re: coaxial cable?, Ray Anderson
  13. » [SI-LIST] using 4195A network/spectrum analyzer...., Tegan Campbell
  14. » [SI-LIST] about 'flat region', qzheng
  15. » [SI-LIST] Need picture or drawing of uneven coating, Doug Brooks
  16. » [SI-LIST] Complex number, Pietro Maffei
  17. » [SI-LIST] Re: about 'flat region', ruston, matt
  18. » [SI-LIST] Recommendation on a good intermediate to advanced SI class/course?, Bret Stott
  19. » [SI-LIST] Re: Complex number, Ray Anderson
  20. » [SI-LIST] Re: Need picture or drawing of uneven coating, Doug Brooks
  21. » [SI-LIST] Where can I get AGP8X ibis and ebd file?, Jack W.C. Lin
  22. » [SI-LIST] HELP£¡, Zeng Zheyu
  23. » [SI-LIST] Ground Fill Question, Vishram Pandit
  24. » [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz, Dr. Edward P. Sayre
  25. » [SI-LIST] Kirchoff and Faraday voltage measurements and simulations, Douglas C. Smith
  26. » [SI-LIST] PSPICE, Pietro Maffei
  27. » [SI-LIST] Re: PSPICE, Ray Anderson
  28. » [SI-LIST] Choose the correct ground symbol, obarkan
  29. » [SI-LIST] ARCHIVED: SI Measurement Seminar, Gary Otonari
  30. » [SI-LIST] pspice pwm ic model, Binosh Balachandra
  31. » [SI-LIST] Hspice class, Yongxue Yu
  32. » [SI-LIST] Re: Hspice class, Michael_Greim
  33. » [SI-LIST] Re: Serpentine Traces, Gupta, Deepali
  34. » [SI-LIST] Re: SONET Sync card, Ying Qian
  35. » [SI-LIST] Re: SFF to SFP adapter board, Ying Qian
  36. » [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination, Hora Abu
  37. » [SI-LIST] Sigrity Offers Free Training of SI Tools, Teo Yatman
  38. » [SI-LIST] Re: Rj-45 connectors isolation properties, jeff_latourrette
  39. » [SI-LIST] High Temp Mil Standard Oscillators, Gupta, Deepali
  40. » [SI-LIST] Re: High Temp Mil Standard Oscillators, Clewell, Craig
  41. » [SI-LIST] Termination resistance value for GTL+ bus, Samuel Dadel
  42. » [SI-LIST] ECL terminations, k EPD
  43. » [SI-LIST] Signal Integrity Books, Shiraz Bashir
  44. » [SI-LIST] Re: ECL terminations, SMITH, Andy (STV)
  45. » [SI-LIST] 10ma Current Loop differntial impedance, Billy Hendrie
  46. » [SI-LIST] Calculating power plane capacitance, Hanley, David C
  47. » [SI-LIST] Clocks and translators, Gupta, Deepali
  48. » [SI-LIST] SI Job description of our ideal candidate, Suder, Ed
  49. » [SI-LIST] Re: Clocks and translators, Steven Kan
  50. » [SI-LIST] Re: Termination resistance value for GTL+ bus, Samuel Dadel
  51. » [SI-LIST] Re: FW: We ought to address mutual SI-EMI issues in this forum, Chris Padilla
  52. » [SI-LIST] Ethernet switch problems: detailed questions, Jan Vercammen
  53. » [SI-LIST] Re: Ethernet switch problems: detailed questions, Lewandowski, Bob
  54. » [SI-LIST] Parasitic capacitance of vias, chris . mcgrath
  55. » [SI-LIST] Re: Parasitic capacitance of vias, David Kaiser
  56. » [SI-LIST] A simple problem about setup time, Rtm He
  57. » [SI-LIST] Re: A simple problem about setup time, Ingraham, Andrew
  58. » [SI-LIST] si-list digest TOC strangeness, Ray Anderson
  59. » [SI-LIST] Re: We ought to address mutual SI-EMI issues inthi s forum, Michael_Greim
  60. » [SI-LIST] Re: We ought to address mutual SI-EMI issues in thi s forum, Loyer, Jeff
  61. » [SI-LIST] Re: Question: Obtaining I/V and Switiching Info via lab measurments, Abdulrahman Rafiq
  62. » [SI-LIST] Re: Slide Rules. (Was Re: We ought to address mutual SI-EMI issues in this forum), Sanchez, Louis
  63. » [SI-LIST] Re: Slide Rules., Todd Westerhoff
  64. » [SI-LIST] Re: Slide Rules. (Was Re: We ought to address mutua l SI-EMI issues in this forum), Dunbar, Tony
  65. » [SI-LIST] Simple tool for FIR filters, Chris Cheng
  66. » [SI-LIST] Trace resistance inductance, Hora Abu
  67. » [SI-LIST] AC/DC impedance spec for floppy and 40Pin-IDE cables., =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
  68. » [SI-LIST] Reminder: Sep Meeting of RMCEMC, Charles Grasso
  69. » [SI-LIST] Package ball inductance, Mayank Sharma
  70. » [SI-LIST] Re: Trace resistance inductance, Keskinen, Kai
  71. » [SI-LIST] Re: AC/DC impedance spec for floppy and 40Pin-IDEcable s., James_R_Jones
  72. » [SI-LIST] EMC2003 in Turkey, Dr. Howard Johnson
  73. » [SI-LIST] Re: Simple tool for FIR filters, Stuart Brorson
  74. » [SI-LIST] Ansoft HFSS - inductive xtalk setup, ttsp
  75. » [SI-LIST] SI Tools, chris . mcgrath
  76. » [SI-LIST] Ansoft HFSS - inductive xtalk setup 2, ttsp
  77. » (no subject), javi del
  78. » [SI-LIST] Post- route analysis error, Jayanthi Natarajan
  79. » [SI-LIST] Spectrum analyzer problem, noise, Jochen Feldhaar
  80. » [SI-LIST] Re: Signal Integrity Engineer Opportunity in theHeart of the Ozarks, Michael_Greim
  81. » [SI-LIST] max current value on a PCB trace, Ricchiuti Vittorio
  82. » [SI-LIST] Re: max current value on a PCB trace, Michael_Greim
  83. » [SI-LIST] high speed circuit diagram?, Juan Manuel
  84. » [SI-LIST] Re: high speed circuit diagram?, Gupta, Deepali
  85. » [SI-LIST] LAN EMI/SI question, KRISMARK01
  86. » [SI-LIST] Buried capacitance materials, Sunil Kumar
  87. » [SI-LIST] current probe calibration, =?big5?b?u6+kaLPHXChTLiBDLiBDaGFvXCk=?=
  88. » [SI-LIST] Re: Buried capacitance materials, Greg . LINK
  89. » [SI-LIST] Simulation problems with SSTL2 IBIS model, Linnenbruegger Dirk
  90. » [SI-LIST] Ethernet tools, Jan Vercammen
  91. » [SI-LIST] Re: Simulation problems with SSTL2 IBIS model, Ravinder Ajmani
  92. » [SI-LIST] Re: GTL buffers Vref, Gupta, Naveen
  93. » [SI-LIST] IBIS model problems, John Ellis
  94. » [SI-LIST] Re: SI Tools, PRIEUR, Olivier
  95. » [SI-LIST] AW: Simulation problems with SSTL2 IBIS model (TI CDCV850), Linnenbruegger Dirk
  96. » [SI-LIST] Re: IBIS model problems, Timothy Coyle
  97. » [SI-LIST] Capacitance calculator, ttsp
  98. » [SI-LIST] Re: Capacitance calculator, John Barnes
  99. » [SI-LIST] Looking for SI position, Fabrizio
  100. » [SI-LIST] Presentation slides available for download, Charles Grasso
  101. » [SI-LIST] Re: Simulation problems with SSTL2 IBIS model (TI CDCV8 50), Angulo, John
  102. » [SI-LIST] Simulate a microprocessor in PSpice through a C program or with Matlab?, Alicia Corrales Chanca
  103. » [SI-LIST] fwd: SI Tools, Abdulrahman A. Rafiq
  104. » [SI-LIST] slew rate and driver impedance, Lin Wee
  105. » [SI-LIST] FW: intel-situg: Driver Model for TEK TDR heads?, Loyer, Jeff
  106. » [SI-LIST] Re: slew rate and driver impedance, James_R_Jones
  107. » [SI-LIST] Differential pair impedance, Bill Mueller
  108. » [SI-LIST] Re: Differential pair impedance, Adam . Tambone
  109. » [SI-LIST] USB 1.1 Cable Model, omer orberk
  110. » [SI-LIST] Can I get this from an IBIS model?, Doug Brooks
  111. » [SI-LIST] Re: Can I get this from an IBIS model?, Dunbar, Tony
  112. » [SI-LIST] A SPICE TO IBIS CONVERSION PROBLEM, Jineshwari Baratharajan
  113. » [SI-LIST] W-elements, ttsp
  114. » [SI-LIST] GTLP VOH documentation, Gupta, Naveen
  115. » [SI-LIST] IBIS ramp problem in Hspice, ruston, matt
  116. » [SI-LIST] Multiple drivers and receivers on one net., Inmyung Song
  117. » [SI-LIST] 2.5Gbit connectors and cables, Jeff Reeve