Posts for si-list, 08-2009

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  1. » [SI-LIST] test post 1, John Madden
  2. » [SI-LIST] Re: Free webcast from Agilent EEsof EDA: Signal Integrity Design Using Fast Channel Simulation and Eye Diagram Statistics, colin_warwick
  3. » [SI-LIST] Evaluation Boards, Mohamad Haghtalab
  4. » [SI-LIST] Informal poll: Which of these conferences are you likely to attend?, colin_warwick
  5. » [SI-LIST] Lowest cost way to implement 16 5Gbps SERDES channels, Chris Johnson
  6. » [SI-LIST] Two page scan PDF of fringing field conformal mapping -- Re: Re: Fringing fields of a circular disc capacitor, Kevin G. Rhoads
  7. » [SI-LIST] si-list back "on the air", Ray Anderson
  8. » [SI-LIST] Asian IBIS Summit (China) First Announcement, Bob Ross
  9. » [SI-LIST] LossBudgetForPCIe, lakshmi.narayanan
  10. » [SI-LIST] Free Webinar on IBIS Model Quality, Timothy Coyle
  11. » [SI-LIST] effect of common choke on high speed differential signals, Joel Brown
  12. » [SI-LIST] Test Message, Ray Anderson
  13. » [SI-LIST] Power Integrity Measurments, rula . bakleh
  14. » [SI-LIST] Re: Power Integrity Measurments, olaney
  15. » [SI-LIST] Power Integrity Measurements, Eric Bogatin
  16. » [SI-LIST] Re: effect of common choke on high speed differential signals, Joel Brown
  17. » [SI-LIST] An unusual use for comb generator, Doug Smith
  18. » [SI-LIST] Ibis model Request!, Mohamad Haghtalab
  19. » [SI-LIST] Re: Ibis model Request!, Mohamad Haghtalab
  20. » [SI-LIST] Need SAS 24AWG Cable model, Neo
  21. » [SI-LIST] SAS/PCIE Cable Material, Neo
  22. » [SI-LIST] Re: High speed serial links over copper cables, Neo
  23. » [SI-LIST] SPT Cable?, Neo
  24. » [SI-LIST] Gaussian Pulse, Behzad
  25. » [SI-LIST] About Skin Effect, LY
  26. » [SI-LIST] HSPICE Simulation with S-Parameter (S2P), See Hour
  27. » [SI-LIST] PVC material and dielectric loss, Neo
  28. » [SI-LIST] Old paper, Jennifer Maharani
  29. » [SI-LIST] FEXT reduction by very small spacings, Eric Bogatin
  30. » [SI-LIST] Asian IBIS Summit (China) Second Announcement, Bob Ross
  31. » [SI-LIST] DDRII write problem!!, TinaWu
  32. » [SI-LIST] To S-parameterize or not to S-parameterize?, colin_warwick
  33. » [SI-LIST] Re: FEXT reduction by very small spacings, Herman Ruckerbauer
  34. » [SI-LIST] PCB Design tools, padma gundala
  35. » [SI-LIST] SONNETLITE AS A PCB DESIGN TOOL?, padma gundala
  36. » [SI-LIST] PDN question, Joel Brown
  37. » [SI-LIST] Re: PDN question, Lynne D. Green
  38. » [SI-LIST] Routing 1G diff ethernet traces, Lakshmi N. Sundararajan - PTU
  39. » [SI-LIST] Digital Interconnect, Mohamad Haghtalab
  40. » [SI-LIST] SI opening, Goutham Sabavat (gsabavat)
  41. » [SI-LIST] PWR/GND Bus (SSN simulation), Mohamad Haghtalab
  42. » [SI-LIST] SiBeam, Jennifer Maharani
  43. » [SI-LIST] Meaning of clock forwarding, Ria R
  44. » [SI-LIST] Need a better SERDES, N. Paul Taddonio
  45. » [SI-LIST] Announcing the 2009 IEEE SCV Chapter EMC Mini-Symposium: October 15-16, Oscar Fallah
  46. » [SI-LIST] DDR PHY, Jennifer Maharani
  47. » [SI-LIST] Regarding S-Parameter and SSN, karthik_package
  48. » [SI-LIST] new pop quiz on bethesignal.com, Eric Bogatin
  49. » [SI-LIST] Re: TDR impedance measurement and rise time, Mick zhou
  50. » [SI-LIST] Shall we build a wiki site for EEE, tubecn tubecn
  51. » [SI-LIST] symmetric coupled striplines..., Ishwar Hosagrahar
  52. » [SI-LIST] Control Impedance testing, BO-LIAO
  53. » [SI-LIST] Re: symmetric coupled striplines..., Ishwar Hosagrahar
  54. » [SI-LIST] CTI >600, costel_t