**Browse: **Last Month: 07-2007 Main Archive Page Next Month: 09-2007

By Date **/** By Date Reverse **/** By Threads

- » [SI-LIST] Building a SI department, mappiani
- » [SI-LIST] Re: Building a SI department, steve weir
- » [SI-LIST] Re: Building a SI department, Lars Juul
- » [SI-LIST] R: Building a SI department, gianguida

- » [SI-LIST] IBISCHK4 version 4.2.2 executables on-line!, Mirmak, Michael
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Vinu Arumugham
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, steve weir
- <Possible follow-ups>
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Vinu Arumugham
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Muranyi, Arpad
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, David Banas
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, ronald miller
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, steve weir

- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Muranyi, Arpad

- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Muranyi, Arpad
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, steven.d.corey
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, olaney
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Townsend, Fred
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Julian Ferry

- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Townsend, Fred
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, olaney
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, olaney
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Ihsan Erdin
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, David Banas

- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, olaney
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Ihsan Erdin

- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, Dmitriev-Zdorov, Vladimir
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, olaney
- » [SI-LIST] Re: Circle bus topology; Circular Firing Squad?, olaney

- » [SI-LIST] GM/Buss. Dev. Mgr High Speed Interconnects, bruce harvie
- » [SI-LIST] mobile phone emi into nearby circuits, Doug Smith
- » [SI-LIST] CPU-Memory Simulation, Mohammad Haeri Kermani
- » [SI-LIST] Re: CPU-Memory Simulation, steve weir
- » [SI-LIST] Re: CPU-Memory Simulation, Joseph Kao

- » [SI-LIST] GOOGLE - HW Leadership, Mountain View, CA, Nancy Malone
- » [SI-LIST] Separating IBIS or Spice models into single model files for ICAP/4 import (Intusoft), Peter Sørensen
- » [SI-LIST] SSN Analysis with IBIS 4.2/AMS (was Drivers ?), g_l_pratt
- » [SI-LIST] Asian IBIS Summit (China) Fifth Announcement, Bob Ross
- » [SI-LIST] IBIS seminar in Fremont CA on Oct 4-5, Lynne D. Green
- » [SI-LIST] DDR3 Fly by topology, raja
- » [SI-LIST] Boston Area EMI Workshop 8/22, Chris Herrick
- » [SI-LIST] PCIe Oscilloscope, Edi Fraiman
- » [SI-LIST] Re: PCIe Oscilloscope, Tom Dagostino
- » [SI-LIST] Re: PCIe Oscilloscope, Kotson, Michael
- » [SI-LIST] Re: PCIe Oscilloscope, ronald miller

- » [SI-LIST] PCB layout free student version, olaney
- » [SI-LIST] Re: PCIe Oscilloscope, Jory McKinley
- <Possible follow-ups>
- » [SI-LIST] Re: PCIe Oscilloscope, Steven Kan
- » [SI-LIST] Re: PCIe Oscilloscope, steve weir
- » [SI-LIST] Re: PCIe Oscilloscope, Doug Smith

- » [SI-LIST] Re: PCIe Oscilloscope, steve weir

- » [SI-LIST] query, Aditya Chandra
- » [SI-LIST] Re: query, steve weir
- » [SI-LIST] Re: query, ronald miller
- <Possible follow-ups>
- » [SI-LIST] Query, Aditya Chandra
- » [SI-LIST] Re: Query, Han Li

- » [SI-LIST] Asian IBIS Summit (Japan) Fourth Announcement, Mirmak, Michael
- » [SI-LIST] Join the thousands of people who got slim, Addie Mullen
- » [SI-LIST] Customer support positions at Mentor Graphics, Fox, Andrea
- » [SI-LIST] Re: Customer support positions at Mentor Graphics, Lai, Ricky (Eng Hou)

- » [SI-LIST] need help with micro probes, axel stein
- » [SI-LIST] Re: need help with micro probes, Gustavo Blando

- » [SI-LIST] PCB with Embedded ESD Protection, Dr. B. Prasad
- » [SI-LIST] Re: PCB with Embedded ESD Protection, Srivats Partha
- » [SI-LIST] Reverse Pulse Technique method?, Pras venki
- » [SI-LIST] Re: Reverse Pulse Technique method?, Vadim Heyfitch
- » [SI-LIST] Re: Reverse Pulse Technique method?, istvan novak

- » [SI-LIST] Re: Reverse Pulse Technique method?, olaney
- » [SI-LIST] Re: Reverse Pulse Technique method?, Pras venki
- <Possible follow-ups>
- » [SI-LIST] Re: Reverse Pulse Technique method?, Techentin, Robert
- » [SI-LIST] Re: Reverse Pulse Technique method?, Dmitriev-Zdorov, Vladimir

- » [SI-LIST] reflection coeficient, sub mani
- » [SI-LIST] Re: reflection coeficient, Tom Dagostino
- » [SI-LIST] Re: reflection coeficient, Andrew Ingraham
- » [SI-LIST] Re: reflection coeficient, Eric Bogatin
- » [SI-LIST] Re: reflection coeficient, Kevin G. Rhoads
- » [SI-LIST] Re: reflection coeficient, Lynne D. Green

- » [SI-LIST] Re: reflection coeficient, olaney
- <Possible follow-ups>
- » [SI-LIST] Re: reflection coeficient, olaney

- » [SI-LIST] SV: Separating IBIS or Spice models into single model files for ICAP/4 import (Intusoft), Peter Sørensen
- » [SI-LIST] Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, Peter Sørensen
- » [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, istvan novak
- » [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, Lars Juul
- » [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, steve weir
- » [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, Julian Ferry
- » [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, Lars Juul
- » [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, Julian Ferry

- » [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, Lars Juul

- » [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance, istvan novak
- » [SI-LIST] RF and SI Engineer wanted at Amkor, Pommerenke, David
- » [SI-LIST] Asian IBIS Summit (China) Sixth Announcement, Bob Ross
- » [SI-LIST] Ansoft Worldwide Application Workshop in Bangalore (11 September 2007), Alex Teo
- » [SI-LIST] diff pairs and spacing, lthemanz
- » [SI-LIST] Re: diff pairs and spacing, Beal, Weston
- » [SI-LIST] Re: diff pairs and spacing, Eric Bogatin

- » [SI-LIST] how tables (waveform/pullup/down etc..) in a IBIS files are used/interpeted by IBIS simulators, Sudhanshu SINGH
- » [SI-LIST] Re: how tables (waveform/pullup/down etc..) in a IBIS files are used/interpeted by IBIS simulators, Muranyi, Arpad
- Message not available
- » [SI-LIST] Re: how tables (waveform/pullup/down etc..) in a IBIS files are used/interpeted by IBIS simulators, Muranyi, Arpad

- » [SI-LIST] Pull up and pull down curves in PCI local bus specifications, rahul kumar
- » [SI-LIST] Re: Pull up and pull down curves in PCI local bus specifications, Townsend, Fred
- » [SI-LIST] Re: Pull up and pull down curves in PCI local bus specifications, Andrew Ingraham

- » [SI-LIST] how to model the power supply current ?, jun feng
- » [SI-LIST] Power integrity post follow up, Julian Ferry
- » [SI-LIST] Re: Job Opening at 3PARData Inc, Chris Cheng
- » [SI-LIST] Undershoot issues, vani.chandrasekharan
- » [SI-LIST] Re: Undershoot issues, PRAJIT S NAIR
- » [SI-LIST] Re: Undershoot issues, Andrew Ingraham
- » [SI-LIST] Re: Undershoot issues, vani.chandrasekharan

- » [SI-LIST] Undershoot issues, vani.chandrasekharan
- » [SI-LIST] Re: Undershoot issues, Jory McKinley
- » [SI-LIST] Re: Undershoot issues, art_porter
- » [SI-LIST] Re: Undershoot issues, vani.chandrasekharan

- <Possible follow-ups>
- » [SI-LIST] Re: Undershoot issues, Jory McKinley
- » [SI-LIST] Re: Undershoot issues, Alfred P. Neves
- » [SI-LIST] Re: Undershoot issues, art_porter
- » [SI-LIST] Re: Undershoot issues, vani.chandrasekharan
- » [SI-LIST] Re: Undershoot issues, PRAJIT S NAIR
- » [SI-LIST] Re: Undershoot issues, vani.chandrasekharan
- » [SI-LIST] Re: Undershoot issues, PRAJIT S NAIR

- » [SI-LIST] Re: Undershoot issues, art_porter
- » [SI-LIST] WE# asserted but data does not toggle, Kenny Frohlich
- » [SI-LIST] Memory CAS Latency (CL2 vs CL3), Kenny Frohlich
- » [SI-LIST] Re: Memory CAS Latency (CL2 vs CL3), Ihsan Erdin
- » [SI-LIST] Re: Memory CAS Latency (CL2 vs CL3), Michael Greim

- » [SI-LIST] Re: Memory CAS Latency (CL2 vs CL3), Ihsan Erdin
- » [SI-LIST] SATA board to board connector question, Sihan Goi
- » [SI-LIST] Dynamic noise analysis of inverter, navaram kumar
- » [SI-LIST] regarding the stack up, Govinda samy
- » [SI-LIST] Re: regarding the stack up, Ralph A Wilson III
- » [SI-LIST] Re: regarding the stack up, Benny Yan

- » [SI-LIST] Re: regarding the stack up, Ralph A Wilson III
- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, Vittal.Balasubramanian
- » [SI-LIST] Re: SATA board to board connector question, Sihan Goi
- <Possible follow-ups>
- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, Sihan Goi
- » [SI-LIST] Re: SATA board to board connector question, Dhamija Naresh-B07930

- » [SI-LIST] Re: SATA board to board connector question, Sihan Goi
- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, Loyer, Jeff

- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, Lee Ritchey
- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, Loyer, Jeff

- » [SI-LIST] Re: SATA board to board connector question, Lee Ritchey
- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, steve weir
- » [SI-LIST] Stripline more lossy than Microstrip?, Loyer, Jeff
- » [SI-LIST] Re: Stripline more lossy than Microstrip?, Eric Bogatin

- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, Lee Ritchey
- » [SI-LIST] Re: SATA board to board connector question, olaney
- » [SI-LIST] Re: SATA board to board connector question, Lee Ritchey
- » [SI-LIST] Re: SATA board to board connector question, Jory McKinley

- » [SI-LIST] FW: Re: SATA board to board connector question, Corey Kimble
- » [SI-LIST] signal integrity events coming up, Eric Bogatin
- » [SI-LIST] Power Decoupling, again...., Julian Ferry
- » [SI-LIST] Free SI training in Beijing China by IO Methodology on Sept. 10, Zhang Xinjun
- » [SI-LIST] software needed, jagaveer25
- » [SI-LIST] Re: software needed, Lars Juul
- » [SI-LIST] Re: software needed, Chris Cheng
- » [SI-LIST] Re: software needed, steve weir
- » [SI-LIST] Re: software needed, Tom Dagostino
- » [SI-LIST] Re: software needed, Vadim Heyfitch
- » [SI-LIST] Re: software needed, Tom Dagostino
- » [SI-LIST] Re: software needed, Vadim Heyfitch
- » [SI-LIST] Re: software needed, Tom Dagostino

- » [SI-LIST] Re: software needed, Tom Dagostino

- » [SI-LIST] Re: software needed, Lee Ritchey
- » [SI-LIST] Asian IBIS Summit (Japan) Fifth Announcement, Mirmak, Michael
- » [SI-LIST] hi, jagaveer25
- » [SI-LIST] Re: hi, steve weir
- » [SI-LIST] Re: hi, Chris Cheng
- » [SI-LIST] Re: hi, Curt McNamara
- » [SI-LIST] Re: hi, sunil bharadwaz

- » [SI-LIST] Re: hi, Srivats Partha
- » [SI-LIST] Re: hi, steve weir
- » [SI-LIST] Re: hi, Charles Harrington
- » [SI-LIST] Re: hi, steve weir
- » [SI-LIST] Re: hi, Chris Cheng
- » [SI-LIST] Re: hi, Ray Anderson
- » [SI-LIST] Re: hi, zakariahbarkhiah
- » [SI-LIST] Re: hi, Kevin Ko
- » [SI-LIST] Re: hi, James Freeman
- » [SI-LIST] unsubscribe, Tabatchnick, Justin

- » [SI-LIST] Re: hi, Charles Harrington
- <Possible follow-ups>
- » [SI-LIST] Re: hi, Srivats Partha
- » [SI-LIST] Re: hi, steve weir
- » [SI-LIST] Re: hi, Chris Cheng

- » [SI-LIST] Re: hi, Srivats Partha
- » [SI-LIST] Re: hi, steve weir

- » [SI-LIST] Re: hi, Srivats Partha
- » [SI-LIST] Re: hi, Chris Cheng

- » [SI-LIST] Re: hi, Damon Bowser
- » [SI-LIST] Re: hi, James Freeman
- » [SI-LIST] Re: hi, Vadim Heyfitch
- » [SI-LIST] Re: hi, vadim heyfitch

- » [SI-LIST] Re: hi, steve weir
- » [SI-LIST] How to measure the resistance, inductance and capacitance parasitic of a packaged chip?, James H
- » [SI-LIST] Intern Position in Andover MA., Jim (James) Antonellis
- » [SI-LIST] Re: How to measure the resistance, inductance and capac itance parasitic of a packaged chip?, Clewell, Craig
- » [SI-LIST] AE Position for Spice Characterization Open in San Jose and Austin., Adrianna
- » [SI-LIST] Re: Stripline more lossy than Microstrip?, olaney
- » [SI-LIST] FW: Re: hi, Ray Anderson
- » [SI-LIST] Resonant Modes, xuzhengrong
- » [SI-LIST] Effect of PCB trace cross-section on SI, Paniraj G.
- » [SI-LIST] Re: Effect of PCB trace cross-section on SI, steve weir
- » [SI-LIST] Re: Effect of PCB trace cross-section on SI, Zeeshan Siddiqi
- » [SI-LIST] Re: Effect of PCB trace cross-section on SI, Istvan Novak - Board Design Technology
- » [SI-LIST] Re: Effect of PCB trace cross-section on SI, Tom Dagostino

- » [SI-LIST] Re: Effect of PCB trace cross-section on SI, Zeeshan Siddiqi

- » [SI-LIST] Re: Effect of PCB trace cross-section on SI, steve weir
- » [SI-LIST] 答复: Resonant Modes, xuzhengrong
- » [SI-LIST] Re: Resonant Modes, xuzhengrong
- » [SI-LIST] Re: Resonant Modes, steve weir
- » [SI-LIST] Re: Resonant Modes, xuzhengrong
- » [SI-LIST] Re: Resonant Modes, steve weir
- » [SI-LIST] Re: Resonant Modes, xuzhengrong
- » [SI-LIST] Re: Resonant Modes, steve weir

- » [SI-LIST] Re: Resonant Modes, xuzhengrong

- » [SI-LIST] Re: Resonant Modes, steve weir
- » [SI-LIST] DDR3 On-Board, J.Jebakumar Samuel
- » [SI-LIST] Re: DDR3 On-Board, srikanth

- » [SI-LIST] Conductor loss reduction at High Frequency, M Sridhar
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Ken Cantrell
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Abe (Abbas) Riazi
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Loyer, Jeff
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Scott McMorrow
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Eric Bogatin
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Loyer, Jeff
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Loyer, Jeff
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Aubrey_Sparkman
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Loyer, Jeff
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, steve weir
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, agathon
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Eric Bogatin
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Tom Biggs
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, steve weir
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Tom Biggs
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, steve weir

- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Scott McMorrow
- <Possible follow-ups>
- » [SI-LIST] Conductor loss reduction at High Frequency, M Sridhar
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Dave Peters
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Eric Bogatin

- » [SI-LIST] Re: Conductor loss reduction at High Frequency, ronald miller
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Muranyi, Arpad

- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Dave Peters

- » [SI-LIST] Re: DDR3 On-Board, Alexandre . AMEDEO
- » [SI-LIST] Request for example transmission line models and their 2d solver results, Kirby Goulet
- » [SI-LIST] Request example transmission line structures for 2d field solver, Kirby Goulet
- » [SI-LIST] 2 copies of postings?, Loyer, Jeff

- » [SI-LIST] Re: Conductor loss reduction at High Frequency, olaney
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Kevin G. Rhoads
- <Possible follow-ups>
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, olaney
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, Kevin G. Rhoads

- » [SI-LIST] Re: Conductor loss reduction at High Frequency, olaney
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, olaney
- » [SI-LIST] Re: Conductor loss reduction at High Frequency, olaney

- » [SI-LIST] Asian IBIS Summit (China) - Agenda, Bob Ross
- » [SI-LIST] fiber-weave effect alive and well?, agathon
- » [SI-LIST] Re: fiber-weave effect alive and well?, steve weir
- <Possible follow-ups>
- » [SI-LIST] fiber-weave effect alive and well?, Gregory R Edlund
- » [SI-LIST] Re: fiber-weave effect alive and well?, Loyer, Jeff

- » [SI-LIST] Re: fiber-weave effect alive and well?, sengottuvel m.p.
- » [SI-LIST] Re: fiber-weave effect alive and well?, Aditya Chandra
- <Possible follow-ups>
- » [SI-LIST] Re: fiber-weave effect alive and well?, Lee Ritchey
- » [SI-LIST] Re: fiber-weave effect alive and well?, Lee Ritchey

- » [SI-LIST] Re: return path, sengottuvel m.p.
- » [SI-LIST] Re: return path, steve weir
- » [SI-LIST] Re: return path, Benny Yan
- Message not available
- » [SI-LIST] Re: return path, Benny Yan

- Message not available

- » [SI-LIST] split plane crossing, Mak gudur
- » [SI-LIST] Re: split plane crossing, Shatabda
- » [SI-LIST] Re: split plane crossing, steve weir
- » [SI-LIST] Re: split plane crossing, Mak gudur
- » [SI-LIST] Re: split plane crossing, steve weir
- » [SI-LIST] Re: split plane crossing, Mak gudur

- » [SI-LIST] Re: split plane crossing, Mak gudur

- » [SI-LIST] the difference of current profile between power supply path, signal path and return path in a circuit loop, xuzhengrong
- » [SI-LIST] Re: the difference of current profile between power supply path, signal path and return path in a circuit loop, Jory McKinley
- » [SI-LIST] TDR S-parameter and correlation, ZHENGGANG CHENG
- » [SI-LIST] Re: TDR S-parameter and correlation, Aubrey_Sparkman
- » [SI-LIST] Re: TDR S-parameter and correlation, dmitry.a.smolyansky
- » [SI-LIST] Re: TDR S-parameter and correlation, Aubrey_Sparkman
- » [SI-LIST] Re: TDR S-parameter and correlation, dmitry.a.smolyansky

- » [SI-LIST] Re: TDR S-parameter and correlation, dmitry.a.smolyansky
- » [SI-LIST] Re: TDR S-parameter and correlation, Tom Dagostino
- » [SI-LIST] Re: TDR S-parameter and correlation, ronald miller
- » [SI-LIST] Re: TDR S-parameter and correlation, Chris Cheng
- » [SI-LIST] Re: TDR S-parameter and correlation, David Instone

- » [SI-LIST] Re: TDR S-parameter and correlation, Chris Cheng
- <Possible follow-ups>
- » [SI-LIST] TDR S-parameter and correlation, Dmitriev-Zdorov, Vladimir

- » [SI-LIST] Re: TDR S-parameter and correlation, Aubrey_Sparkman
- » [SI-LIST] Design Guide or Analysis?, Gregory R Edlund
- » [SI-LIST] Re: FW: TDR S-parameter and correlation, ZHENGGANG CHENG
- » [SI-LIST] Re: FW: TDR S-parameter and correlation, steve weir
- » [SI-LIST] Re: FW: TDR S-parameter and correlation, Dmitriev-Zdorov, Vladimir

- » [SI-LIST] Re: FW: TDR S-parameter and correlation, Loyer, Jeff
- » [SI-LIST] Re: FW: TDR S-parameter and correlation, Chris Cheng
- » [SI-LIST] A Hyperlynx7.7 Boardsim tutor in Santa Clara?, Nick Langston

- » [SI-LIST] Re: FW: TDR S-parameter and correlation, Chris Cheng

- » [SI-LIST] Re: FW: TDR S-parameter and correlation, steve weir
- » [SI-LIST] Conduction cooled board, ganeshkumar.m
- » [SI-LIST] Cisco Systems Opportunities-San Bruno, California, Catherine Paradiso -X \(caparadi - Spherion at Cisco\)
- » [SI-LIST] Re: Cisco Systems Opportunities-San Bruno, California, Ray Anderson

- » [SI-LIST] How to properly simulate signal integrity across PCBs interconnected by Flex?, jeanpierrepoulin
- » [SI-LIST] hapice simulation of Z_tdr, ZHENGGANG CHENG