Posts for si-list, 07-2012

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  1. » [SI-LIST] Looking for IBIS model, mydiginet
  2. » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals, Vinu Arumugham
  3. » [SI-LIST] Reg: Editing in IBIS model, SI
  4. » [SI-LIST] NEED IBIS MODEL for BU61865, Vinothkumar D
  5. » [SI-LIST] Series termination and damping resistors, Jason Young
  6. » [SI-LIST] AC Coupling Cap Voids Questions, Dan
  7. » [SI-LIST] Number of bits required for BER simulation?, mark
  8. » [SI-LIST] PCB material selection and stackup optimization, Bill Hargin \(ICD\)
  9. » [SI-LIST] DDR3 Multi rank -ODT, Balamanikandan K
  10. » [SI-LIST] spice RLC extraction of nets based on GDS2 file, jan . vercammen1
  11. » [SI-LIST] R: spice RLC extraction of nets based on GDS2 file, gianguida@xxxxxxxx
  12. » [SI-LIST] SI Engineer, Neely, Mark
  13. » [SI-LIST] Intel List of Recommeded Reading - Signal Integrity, Lora Abbe
  14. » [SI-LIST] Re: Alan Turing Centenary tomorrow, June 23rd, agathon
  15. » [SI-LIST] the relationship between odd mode impedance,even mode impedance, differential impedance and common impedance, Tang, Linda (Xin Cai)
  16. » [SI-LIST] how can impedance effect insertion loss, liufeng1(刘丰)
  17. » [SI-LIST] Re: how can impedance effect insertion loss, Havermann, Gert
  18. » [SI-LIST] Re: Intel List of Recommeded Reading - Signal Integrity, peggi Valentia
  19. » [SI-LIST] How to send data over DC power, Joel Brown
  20. » [SI-LIST] Peaks and Nulls in spectral density, Aaditya Kandibanda
  21. » [SI-LIST] EPEPS-2012 Final Paper Submission Deadline Extension to 27th July 2012, EPEPS Admin
  22. » [SI-LIST] Global EMC and SI University at 2012 IEEE EMC Conf, Eric Bogatin
  23. » [SI-LIST] Auto-response, kundanchand chand
  24. » [SI-LIST] Job Posting for SI Engineer, Randon Richards (rkrichards)
  25. » [SI-LIST] vias and current pathes, Herbert
  26. » [SI-LIST] Just a simple question, Herbert
  27. » [SI-LIST] XGMII is electrically limited to distances of approximately 7 cm, Balamanikandan K
  28. » [SI-LIST] an unusual use for and ESD simulator, Doug Smith
  29. » [SI-LIST] PCB material selection Webinar (Tues.), and "Reflections and Impedance Matching" (Weds.), Bill Hargin \(ICD\)
  30. » [SI-LIST] Sr. SI Engineer (Backplane Architect) needed at Huawei in Santa Clara, CA;, Mark Apton
  31. » [SI-LIST] MOV rating, bala
  32. » [SI-LIST] DDR3 Clock differential signal termination, Tesla
  33. » [SI-LIST] Do you need to do DDR VT test? and how?, jackle zheng
  34. » [SI-LIST] Signal Integrity Opportunity @ Apple, Sandy Perlman
  35. » [SI-LIST] DDR3 CMD/ADD/CTL signal line termination, Tesla
  36. » [SI-LIST] Switcher Efficiency Optimization, Tayyab Rahimkhan Pathan
  37. » [SI-LIST] TML excitation_A very simple question, Tesla
  38. » [SI-LIST] Request for suggestions on developing SI/PI skills, Riley, Jonathan
  39. » [SI-LIST] Length Matching for Interlaken and CFP Trace, Dan
  40. » [SI-LIST] SI Special Session in IEEE EMC 2012 International Symposium, Ye, Chunfei
  41. » [SI-LIST] Thermal Profile WITHIN a trace, dbrooks9