Posts for si-list, 07-2008

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  1. » [SI-LIST] Re: max transient current in target impedance calculation, Hirshtal Itzhak
  2. » [SI-LIST] power integrity test plan, Mustafa Özgür TUTUM
  3. » [SI-LIST] Re: Power/ground BGA assignment in package, Jai Shanker
  4. » [SI-LIST] Looking for good source of information regarding Via tuning, Denomme, Paul S.
  5. » [SI-LIST] Re: Looking for good source of information regarding Via tuning, Chris Herrick
  6. » [SI-LIST] Reg reference plane :speed2000, Pras
  7. » [SI-LIST] RF switch information, Market News Brioconcept
  8. » [SI-LIST] Re: RF switch information, Harry Lin
  9. » [SI-LIST] Parasitic Coupling Between Unshielded Wire Loops, Doug Smith
  10. » [SI-LIST] Virtex -5 PCI ibis file and simulation, crr1231
  11. » [SI-LIST] How to decide the cut off frequency in SIwave, King Da
  12. » [SI-LIST] Signal Integrity programs at upcoming IEEE International Symposium on EMC (August 18 - 22, Detroit, USA), Ye, Xiaoning
  13. » [SI-LIST] Has the performance of the PDN in the receiver little effect on the SSN?, xuzhengrong
  14. » [SI-LIST] Re: Has the performance of the PDN in the receiver little effect on the SSN?, xuzhengrong
  15. » [SI-LIST] What will happen when short the SERDES IO to GND?, liuluping 41830
  16. » [SI-LIST] PCB Laminate - Nelco & S1000-2, Raja_GDA
  17. » [SI-LIST] DDR2 VTT terminations, Edi Fraiman
  18. » [SI-LIST] Re: PCB Laminate - Nelco & S1000-2, olaney
  19. » [SI-LIST] Re: What will happen when short the SERDES IO to GND?, liuluping 41830
  20. » [SI-LIST] Signal intergrity, viswanathan
  21. » [SI-LIST] short video on building a square magentic loop, Doug Smith
  22. » [SI-LIST] MD-Spice, viswanathan
  23. » [SI-LIST] Fw: Re: MD-Spice, viswanathan
  24. » [SI-LIST] DDR2 Simulation, Mustafa Özgür TUTUM
  25. » [SI-LIST] weekly video podcasts, Doug Smith
  26. » [SI-LIST] Recruitment, shine_wu
  27. » [SI-LIST] Fwd: [Help] How to implement filter function in Ansoft Nexxim, King Da
  28. » [SI-LIST] Re: Signal integrity, Lee Ritchey
  29. » [SI-LIST] Need help, bhuvana
  30. » [SI-LIST] Job Opening, Altera High-Speed Characterization, Daniel Chow
  31. » [SI-LIST] Information regarding Stackup Design., Johnni Friis
  32. » [SI-LIST] trivial newbie question, Jack Olson
  33. » [SI-LIST] A powerful troubleshooting technique, Doug Smith
  34. » [SI-LIST] SI books & software for sale, Robert Sefton
  35. » [SI-LIST] LVCMOS to HSTL, Santangelo, Steven
  36. » [SI-LIST] Eric Bogatin's new SI blog, Eric Bogatin
  37. » [SI-LIST] EPEP 2008 Call For Papers, Paul D. Franzon
  38. » [SI-LIST] 10 Layer stack up, sunil bharadwaz
  39. » [SI-LIST] ESS TC failure @ - 20C or -40C, Lum Wee Mei
  40. » [SI-LIST] I am looking for a "good" macromodel dml for MGH simulation, Alexandre . AMEDEO
  41. » [SI-LIST] SATA Receive signal criteria, Joel Brown
  42. » [SI-LIST] Draft IBIS 5.0 specification now available for review, Mirmak, Michael
  43. » [SI-LIST] DDR2 Trace Length Margin, Gregory R Edlund
  44. » [SI-LIST] An S-Parameter matrix to look differential mode crosstalk?, tom_cip_11551
  45. » [SI-LIST] video on PCB troubleshooting, Doug Smith
  46. » [SI-LIST] A warning in ADS simulation, Zhangkun
  47. » [SI-LIST] Multiple series caps in signal lines, Bowden, Ivor
  48. » [SI-LIST] Senior Applications Engineer - Inphi Corporation - Sunnyvale, CA or Westlake Village, CA, Ho, Francis
  49. » [SI-LIST] Hspice Simulation problem!, purushotham br
  50. » [SI-LIST] My new SI blog, colin_warwick
  51. » [SI-LIST] new video podcast "A Scope Probe can Fool You", Doug Smith
  52. » [SI-LIST] Re: DDR2 Trace Length Margin, Lee Ritchey
  53. » [SI-LIST] Re: Free, hands-on PCIe Workshop: Signal Integrity Design, Analysis, and Verification, colin_warwick
  54. » [SI-LIST] Re: Free, hands-on PCIe Workshop: Signal Integrity Design, Analysis, and Verification [test, ignore], colin_warwick
  55. » [SI-LIST] dendrites / edge relief, k EPD
  56. » [SI-LIST] Re: new video podcast "A Scope Probe can Fool You", colin_warwick
  57. » [SI-LIST] power consuming of IC in different temperature, Zhangkun
  58. » [SI-LIST] Signal Integrity Position in DuPont, Washington, Loyer, Jeff
  59. » [SI-LIST] Would you follow the overshoot specs of the datasheet?, liuluping 41830
  60. » [SI-LIST] IBIS Ver 4.2&5, Mohamad Haghtalab
  61. » [SI-LIST] current distribution, Mohamad Haghtalab
  62. » [SI-LIST] Re: current distribution, olaney@xxxxxxxx
  63. » [SI-LIST] mail test, please ignore., Aubrey Sparkman
  64. » [SI-LIST] Email test <D, please ignore., Aubrey_Sparkman
  65. » [SI-LIST] 12 Layer stack, sunil bharadwaz
  66. » [SI-LIST] Enterprise Network Switching DDR & SerDes Interface Design Manager, Jim (James) Antonellis
  67. » [SI-LIST] DDR2 Setup/Hold Derating, Tony Dunbar
  68. » [SI-LIST] How to short two nodes in SPICE, millionwood
  69. » [SI-LIST] the effect of box on EMI, zhangkun 29902
  70. » [SI-LIST] Re: How to short two nodes in SPICE, Kim Helliwell
  71. » [SI-LIST] Indcutance role in EMI, Umamaheswar U-TLS,Chennai
  72. » [SI-LIST] Re: signal quality on unbuffered DIMM, Jory McKinley
  73. » [SI-LIST] Jingling change, ESD, and scope probes video, Doug Smith