Posts for si-list, 07-2002

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  1. » [SI-LIST] Re: IBIS VT & VI curve verification, Dagostino, Tom
  2. » [SI-LIST] Inexpensive, but useful measurement and debugging tools, Douglas C. Smith
  3. » [SI-LIST] Need large bandwidth oscilloscope ?, Steve Rogers
  4. » [SI-LIST] Rectangular patterns on Toplayer., Ismail B - CTD, Chennai.
  5. » [SI-LIST] Re: Rectangular patterns on Toplayer., Keskinen, Kai
  6. » [SI-LIST] a "via" doubt, Juan Manuel
  7. » [SI-LIST] Re: a "via" doubt, Michael Khusid
  8. » [SI-LIST] Current carrying cap - microvia, cadpro2k
  9. » [SI-LIST] IBIS ECL Clock issue., ramroopsingh, marlon
  10. » [SI-LIST] Re: IBIS ECL Clock issue., lgiacott@xxxxxxxxx
  11. » [SI-LIST] Re: reference plane, Charles Grasso
  12. » [SI-LIST] HSPICE W elemnt and 2.5D field solver, Scuba Snail
  13. » [SI-LIST] Re: HSPICE model to XTK model, McKinley, Jory D
  14. » [SI-LIST] Re: Current carrying cap - microvia, Clewell, Craig
  15. » [SI-LIST] Speed Limit for dual stripline diff pairs?, Patrick O'Shea
  16. » [SI-LIST] Re: Speed Limit for dual stripline diff pairs?, Hassan O. Ali
  17. » [SI-LIST] Re: Peak Current Due to Overshoot, Whitaker, Steven
  18. » [SI-LIST] varying the overlap length between two parallel conductors, Jayanta Choudhury
  19. » [SI-LIST] Off Topic : JTAG memory read, Deepak Mohan
  20. » [SI-LIST] How to select the connector under the 3.125Gbps, 胡鹏
  21. » [SI-LIST] TO define the "Preemphasis", 胡鹏
  22. » [SI-LIST] Re: TO define the "Preemphasis", Ismail B - CTD, Chennai.
  23. » [SI-LIST] via capacitance, Juan Manuel
  24. » [SI-LIST] Re: Question on radiation limits, Chris Padilla
  25. » [SI-LIST] SIGRITY Extends Free Service Offer to SI-LIST Community, Teo Yatman
  26. » [SI-LIST] Current Carrying Capacity, AK Mishra
  27. » [SI-LIST] Re: Current Carrying Capacity, Jackson, T L
  28. » [SI-LIST] Re: testing please ignore, leung99
  29. » [SI-LIST] Receiver End Signal, Kedar P. Apte
  30. » [SI-LIST] Re: Receiver End Signal, Ismail B - CTD, Chennai.
  31. » [SI-LIST] Fw: TO define the "Preemphasis", 胡鹏
  32. » [SI-LIST] Availability of IBIS model of 168 pin SDRAM DIMM socket, Raghu.Tilak
  33. » [SI-LIST] Vih for PCI, marko.pulli
  34. » [SI-LIST] Re: Vih for PCI, Ingraham, Andrew
  35. » [SI-LIST] Re: Availability of IBIS model of 168 pin SDRAM DIMM socket, tcrondeau
  36. » [SI-LIST] length of 10Gig traces on FR4, mittalr@xxxxxxxxxx
  37. » [SI-LIST] Hspice simulation, Mohammad Ali
  38. » [SI-LIST] Re: Hspice simulation, Gutzmann, Michael
  39. » [SI-LIST] Data bus skew, nitin bhandari
  40. » [SI-LIST] Re: Data bus skew, James_R_Jones
  41. » [SI-LIST] 550 Mbps LVDS Cable and Connector Help, Rod Barman
  42. » [SI-LIST] AC coupling Capacitors, Alex Jose
  43. » [SI-LIST] AW: Re: Data bus skew, hermann . ruckerbauer
  44. » [SI-LIST] AW: Availability of IBIS model of 168 pin SDRAM DIMM socket, Schaefer, Andreas (Abg)
  45. » [SI-LIST] AW: Availability of IBIS model of 168 pin SDRAM DIMM so cket, Linnenbruegger Dirk
  46. » [SI-LIST] Specctraquest Multiboard, Lucas Bossetti
  47. » [SI-LIST] Re: Specctraquest Multiboard, Carlos Moll
  48. » [SI-LIST] Re: 550 Mbps LVDS Cable and Connector Help, Ravinder Ajmani
  49. » [SI-LIST] Re: Availability of IBIS model of 168 pin SDRAMDIM M so cket, Michael_Greim
  50. » [SI-LIST] Recall: Re: Availability of IBIS model of 168 pinSDRAM DIMM so cket, Michael_Greim
  51. » [SI-LIST] DesignCon call for papers is now on line, Mike Li
  52. » [SI-LIST] ISI Simulation., fname lname
  53. » [SI-LIST] about Hspice w element segment ??, qzheng
  54. » [SI-LIST] Re: ISI Simulation., Michael_Greim
  55. » [SI-LIST] Re: length of 10Gig traces on FR4 - compiled responses, mittalr@xxxxxxxxxx
  56. » [SI-LIST] Looking for IBIS model for Pericom 74FCT2253CTW Mux, Hassan O. Ali
  57. » [SI-LIST] attention Midwest SI engineers, Gregory R Edlund
  58. » [SI-LIST] Re: varying the overlap length between two parallel conductors, Mohamed Shaheen
  59. » [SI-LIST] is it posible to remove reflection in a PCB, Kedar P. Apte
  60. » [SI-LIST] IEC standard on IC pin currents, Thomas Beneken
  61. » [SI-LIST] Re: is it posible to remove reflection in a PCB, Ismail B - CTD, Chennai.
  62. » [SI-LIST] Re: SIGRITY Extends Free Service Offer to SI-LIST Community, Zhou, Xingling (Mick)
  63. » [SI-LIST] ESL component of a SMT resistor, Silva, Benjamin P
  64. » [SI-LIST] test, Scott McMorrow
  65. » [SI-LIST] Board layout issue, Ravinder Ajmani
  66. » [SI-LIST] What's the meaning of "first incident wave"?, yun
  67. » [SI-LIST] still a Hspice segment question, qzheng
  68. » [SI-LIST] add some thing, qzheng
  69. » [SI-LIST] Re: Your password!, jtalavera
  70. » [SI-LIST] Modeling board contribution to Jitter for 2.5Gb/s Channel, Bob Welte
  71. » [SI-LIST] 2003$B%7%9%F%`(BLSI$B5;=QBgA4(B, Yutaka Honda
  72. » [SI-LIST] Apology, Yutaka Honda
  73. » [SI-LIST] Re: Modeling board contribution to Jitter for 2.5Gb/s Channel, Muhammad Sagarwala
  74. » [SI-LIST] Re: varying the overlap length between two parallel con ductors, Mohamed Shaheen
  75. » [SI-LIST] Signal Integ. / IC Characterization Job Posting, E L
  76. » [SI-LIST] Was : IBIS Model of 168 Pin SDRAM DIMM Socket, Raghu.Tilak
  77. » [SI-LIST] Re: via capacitance, Dr. Howard Johnson
  78. » [SI-LIST] Bibliographies, John Barnes
  79. » [SI-LIST] contests or prize for undergraduate students in signal integrity or EMC, Jan Vercammen
  80. » [SI-LIST] Fw: SSN, Juan Manuel
  81. » [SI-LIST] Multidrop bus with 6 Bidir loads topology and termination, Jean Pierre Bouthemy
  82. » [SI-LIST] Re: Board layout issue, cadpro2k
  83. » [SI-LIST] Re: Multidrop bus with 6 Bidir loads topology and termination, Hassan O. Ali
  84. » [SI-LIST], Igor_Slobodnik
  85. » [SI-LIST] Re: Bibliographies - Write a book?, John Barnes
  86. » [SI-LIST] rise and fall times for SCSI-160 and 320, Tegan Campbell
  87. » [SI-LIST] Translating a Differential IBIS buffer to XTK format, Timothy Coyle
  88. » [SI-LIST] DDR333 memory module's IBIS model and board file, sogo_hsu
  89. » [SI-LIST] Re: DDR333 memory module's IBIS model and board file, Michael_Greim
  90. » [SI-LIST] Re: Translating a Differential IBIS buffer to XTK format, Umesh Painaik
  91. » [SI-LIST] SMA for launching 5-10Gbs signals, zanella, fabrizio
  92. » [SI-LIST] Re: SMA for launching 5-10Gbs signals, Clewell, Craig
  93. » [SI-LIST] FW: Re: via capacitance, Tabatchnick, Justin
  94. » [SI-LIST] ZBC-2000 dielectric model, Virendra
  95. » [SI-LIST] Signal Integrity Engineering Manager Wanted!, Lisa Shone
  96. » [SI-LIST] Re: PCB Manufacturer Recommendations, Ibrahim Khan
  97. » [SI-LIST] Re: FW: Re: via capacitance, Istvan Novak - Board Design Technology
  98. » [SI-LIST] abt.Tco and Bufferdelay, zanglinyuan
  99. » [SI-LIST] Re: abt.Tco and Bufferdelay, Shankar Raj
  100. » [SI-LIST] XAUI reference material, Billy Hendrie
  101. » [SI-LIST] Call for Abstracts, Ronda Faries
  102. » [SI-LIST] Re: XAUI reference material, Rotem Gazit
  103. » [SI-LIST] S-paramter to capacitive/inductive crosstalk, ttsp
  104. » [SI-LIST] Intepretation of SPICE Models, Jineshwari B - CTD, Chennai.
  105. » [SI-LIST] AW: Intepretation of SPICE Models, Linnenbruegger Dirk
  106. » [SI-LIST] Re: Intepretation of SPICE Models, Ingraham, Andrew
  107. » [SI-LIST] Power over Ethernet/LAN/DTE design, CHUANG,KENGHUA (Non-HP-Roseville,ex1)
  108. » [SI-LIST] Re: Pre-emphasis and IBIS, Dagostino, Tom
  109. » [SI-LIST] return loop current distribution, Chandrabhushan
  110. » [SI-LIST] how to evaluate the maximum overhsoot/undershoot, zanglinyuan
  111. » [SI-LIST] Re: how to evaluate the maximum overhsoot/undershoot, Martin.J Thompson
  112. » [SI-LIST] package model, Chiwon Kim
  113. » [SI-LIST] ** www.hardware-guru.com **, Eitan k
  114. » [SI-LIST] ** www.hardware-guru.com **, Eitan k
  115. » [SI-LIST] Re: ** www.hardware-guru.com **, Michael_Greim
  116. » [SI-LIST] Re: Archived broadcast, rtm_he
  117. » [SI-LIST] HSTL Terminations, Jineshwari B - CTD, Chennai.
  118. » [SI-LIST] doubt about crosstalk., yun
  119. » [SI-LIST] Re: doubt about crosstalk., Ibrahim Khan
  120. » [SI-LIST] Crosstalk, Mohamed Shaheen
  121. » [SI-LIST] Recall:, Jineshwari B - CTD, Chennai.
  122. » [SI-LIST] How should we terminate unused HSTL Outputs., Jineshwari B - CTD, Chennai.
  123. » [SI-LIST] dont understand, qzheng
  124. » [SI-LIST] Re: doubt about crosstalk, Gregory R Edlund
  125. » [SI-LIST] LVDS RECEIVER IBIS MODEL, Peter LaFlamme
  126. » [SI-LIST] Re: LVDS RECEIVER IBIS MODEL, Kevin (PSD) Chung
  127. » [SI-LIST] Re: Message submitted to 'si-list', Ray Anderson
  128. » [SI-LIST] Re: HSPICE error, Michael Khusid
  129. » [SI-LIST] Job Openings at Sigrity, Teo Yatman
  130. » [SI-LIST] remove, Mohamed Mahmoud
  131. » [SI-LIST] who have this paper, qzheng
  132. » [SI-LIST] i love this place !!!, qzheng
  133. » [SI-LIST] hello, Nasir Abdul Quadir
  134. » [SI-LIST] Package in IBIS Bench Files, Timothy Coyle
  135. » [SI-LIST] Re: Package in IBIS Bench Files, Ingraham, Andrew
  136. » [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not?, Jian X. Zheng
  137. » [SI-LIST] A question for the group, MikonCons
  138. » [SI-LIST] Re: A question for the group, Ibrahim Khan
  139. » [SI-LIST] ibis limitations, kal ansari
  140. » [SI-LIST] HSPICE W-element transmission line model accuracy?, Zhiping Yang
  141. » [SI-LIST] Re: ibis limitations, Chris Cheng
  142. » [SI-LIST] Re: Slot Antenna, EVANS,JEFF (HP-Cupertino,ex3)
  143. » [SI-LIST] Determining timing budgets using IBIS, Alex Horvath
  144. » [SI-LIST] Reflection Simulation, Kedar P. Apte
  145. » [SI-LIST] Re: i love this place !!!, Ibrahim Khan
  146. » [SI-LIST] Re: Determining timing budgets using IBIS, Peters, Stephen
  147. » [SI-LIST] PCI daughter card signal trace length, zanglinyuan
  148. » [SI-LIST] voltage mode and current mode logic, sunil-chandra . kasanyal
  149. » [SI-LIST] Re: PCI daughter card signal trace length, Ingraham, Andrew
  150. » [SI-LIST] job opening at GigaTest Labs, Eric Bogatin
  151. » [SI-LIST] IBIS Version 4.0 is released, Peters, Stephen
  152. » [SI-LIST] Best board design for edge launch SMA to differential, Bob Welte
  153. » [SI-LIST] measuring i/o power without disrupting signal quality, Kim Flint
  154. » [SI-LIST] Routing over a plane split, Christopher . Crowley
  155. » [SI-LIST] Modeling Simultaneous Switching Noise, Khalid Ansari
  156. » [SI-LIST] help ?why my eye is like this ??, qzheng
  157. » [SI-LIST] Re: Routing over a plane split, Christopher . Crowley
  158. » [SI-LIST] Re: help ?why my eye is like this ??, Michael_Greim
  159. » [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or..., MikonCons
  160. » [SI-LIST] Output Capacitor of a switching Regulator, Anand . Kuriakose
  161. » [SI-LIST] Course on Signal Integrity at San Jose State Univ., Raj Raghuram
  162. » [SI-LIST] Re: measuring i/o power without disrupting signalquality, Kim Flint
  163. » [SI-LIST] Roger O Wittman/GDIS/GDYN is out of the office., Roger.Wittman
  164. » [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not?, Scott McMorrow
  165. » [SI-LIST] Issues with Midpoint Crossing of Differential IBIS Buffer, Timothy Coyle
  166. » [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not?, Istvan Novak - Board Design Technology
  167. » [SI-LIST] Re: Issues with Midpoint Crossing of Differential IBIS Buffer, Adam . Tambone
  168. » [SI-LIST] Re: Remove Ground underneath Differential signal is deservedor not?, Ravinder Ajmani
  169. » [SI-LIST] Re: Issues with Midpoint Crossing of DifferentialIBIS Buffer, Timothy Coyle
  170. » [SI-LIST] Re: Output Capacitor of a switching Regulator, Larry Smith
  171. » [SI-LIST] GPPO Edge Launch -- Experiences > 10 GHz / Proper Mount?, Christian Schuster
  172. » [SI-LIST] Layout service recommendations, Martin Euredjian
  173. » [SI-LIST] Re: Layout service recommendations, Ray Anderson