Posts for si-list, 06-2001

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  1. » [si-list] this is a test message, Ray Anderson
  2. » [si-list] test #2, Ray Anderson
  3. » [SI-LIST] test 3, Ray Anderson
  4. » [SI-LIST] test message, Ray Anderson
  5. » [SI-LIST] Re: test message, Ray Anderson
  6. » [SI-LIST] si-list @ new home, Ray Anderson
  7. » [SI-LIST] Re: : Asymmetric Differential Stripline, Doug Brooks
  8. » [SI-LIST] List Management Instructions, Ray Anderson
  9. » [SI-LIST] Re: : pecl termination, Mike Saunders
  10. » [SI-LIST] 1GHz clock needed, please share your info with me., Yu Wang
  11. » [SI-LIST] HSPICE W element field solver model, Alex March
  12. » [SI-LIST] SSTL_3 output buffer design, rajat . chauhan
  13. » [SI-LIST] ANT-10Gig Electrical Interface, Javin Olson
  14. » [SI-LIST] Re: HSPICE W element field solver model, Larry Miller
  15. » [SI-LIST] more data on FR4 loss at high freq, FYI, Greim, Michael
  16. » [SI-LIST] Hello from the staff, John Madden
  17. » [SI-LIST] The types of drivers?, Inmyung Song
  18. » [SI-LIST] FW: HSPICE W element field solver model, Eric Bogatin
  19. » [SI-LIST] Information on CML I/O's, Peter LaFlamme
  20. » [SI-LIST] Re: The types of drivers?, Michael Allen
  21. » [SI-LIST] Re: : Frequency based on rise time for drivers, rajat . chauhan
  22. » [SI-LIST] Attachments to si-list being disabled, raymonda
  23. » [SI-LIST] Mentor IS?, Inmyung Song
  24. » [SI-LIST] Surface roughness of PCB tracks at track/substrate interface ?, Steve Rogers
  25. » [SI-LIST] Serpentine shapes, Senthil . Selvam
  26. » [SI-LIST] Serpentine switchback lengths, Senthil . Selvam
  27. » [SI-LIST] K/a Adam on basic design question, Senthil . Selvam
  28. » [SI-LIST] Re: Surface roughness of PCB tracks at track/substrate interface ?, Zabinski, Patrick J.
  29. » [SI-LIST] Re: Attachments to si-list being disabled, Greim, Michael
  30. » [SI-LIST] EPEP'2001 reminder for July 10, 2001 deadline, Alina Deutsch
  31. » [SI-LIST] Re: Mentor IS?, Cusanelli, Tony
  32. » [SI-LIST] Re: Inductance of Via, Tsuk, Michael
  33. » [SI-LIST] Measuring high speed signals, Alex Horvath
  34. » [SI-LIST] Re: Ideal driver characteristics, Bill . Cohen
  35. » [SI-LIST] Re: Measuring high speed signals, Ingraham, Andrew
  36. » [SI-LIST] Differential signals - even and odd modes, Chris Mesibov
  37. » [SI-LIST] Looking for VHDM cable assembly solutions........, Greim, Michael
  38. » [SI-LIST] Even/Odd mode impedance, Alexis LESTRA
  39. » [SI-LIST] Odd/Even mode impedance, Alexis LESTRA
  40. » [SI-LIST] Re: Even/Odd mode impedance, Robert_Washburn
  41. » [SI-LIST] Seeking a coupled transmission line model, Kim Helliwell
  42. » [SI-LIST] who si-list, Jones, Matthew S
  43. » [SI-LIST] "who [SI-List}", Rich Peyton
  44. » [SI-LIST] set hidden, Armstrong, Bob
  45. » [SI-LIST] admin commands sent to si-list, Ray Anderson
  46. » [SI-LIST] Re: admin commands sent to si-list, Rich Peyton
  47. » [SI-LIST] The PCB is a component, cadpro2k
  48. » [SI-LIST] Re: The PCB is a component, Ingraham, Andrew
  49. » [SI-LIST] Voltage rating of a Ceramic capacitor, Ravinder Ajmani
  50. » [SI-LIST] Re: Voltage rating of a Ceramic capacitor, Ken Patterson
  51. » [SI-LIST] measuring Hi-Z and Lo-Z state, IVOR TING
  52. » [SI-LIST] Re: measuring Hi-Z and Lo-Z state, Ingraham, Andrew
  53. » [SI-LIST] commands, William Shiozaki
  54. » [SI-LIST] matching differential impedance for edge-coupled lines, Perry Qu
  55. » [SI-LIST] LVTTL I/O spec for 3.3V, Sivaraman Chokkalingam
  56. » [SI-LIST] SI Position Open, esther williams
  57. » [SI-LIST] Re: SI Position Open READ THIS!!!!, Alfredo Moncayo
  58. » [SI-LIST] Re: SI Position Open, Joe Cahill
  59. » [SI-LIST] Re: 1GHz clock needed, please share your info with me., Michael Nudelman
  60. » [SI-LIST] Re: Improve the heat on a PCB, Zabinski, Patrick J.
  61. » [SI-LIST] Hspice core dump, Michael Baxter
  62. » [SI-LIST] Re: Hspice core dump, chen, jinhua
  63. » [SI-LIST] FYI: Solder ..., Doug McKean
  64. » [SI-LIST] Validation of XTK results for clock skews, Suchitha . V
  65. » [SI-LIST] New App. Note Available, Gary Otonari
  66. » [SI-LIST] Re: Validation of XTK results for clock skews, Marc Humphreys
  67. » [SI-LIST] Re: (no subject), Muranyi, Arpad
  68. » [SI-LIST] set si-list digest2, Adam Klein
  69. » [SI-LIST] Re: set si-list digest2, Rich Peyton
  70. » [SI-LIST] Crosstalk between different layers, Roberto Carretta
  71. » [SI-LIST] IBIS2XTK v. SPI2MOD, Adam . Tambone
  72. » [SI-LIST] Re: IBIS2XTK v. SPI2MOD, ABOUJEYAB
  73. » [SI-LIST] copper thickness of a ref plane, Peterson, James F (FL51)
  74. » [SI-LIST] Re: copper thickness of a ref plane, Greim, Michael
  75. » [SI-LIST] nRESET, SEOW,ERWIN-SP (HP-Singapore,ex1)
  76. » [SI-LIST] nRESET 2, SEOW,ERWIN-SP (HP-Singapore,ex1)
  77. » [SI-LIST] Where to advertise DSP Job ?, Steve Rogers
  78. » [SI-LIST] Chassis ground, Alex Horvath
  79. » [SI-LIST] Book, Alex Horvath
  80. » [SI-LIST] Re: Book, Ken Beach
  81. » [SI-LIST] Re: Chassis ground, Rich Peyton
  82. » [SI-LIST] Re: si-list Digest V1 #30, Chris Renneman
  83. » [SI-LIST] 3D field solver, Samuel Tilakraj
  84. » [SI-LIST] Re: Book - (Chassis - signal ground), Larry Miller
  85. » [SI-LIST] Re: 3D field solver, Larry Miller
  86. » [SI-LIST] high included message content percentage........, Ray Anderson