Posts for si-list, 04-2003

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  1. » [SI-LIST] regarding standards Fcc etc.,, mbestha
  2. » [SI-LIST] XTK model for I2C bus, SI Eng
  3. » [SI-LIST] Re: XTK model for I2C bus, Guasti Giovanni
  4. » [SI-LIST] Re: Skew and Jitter, Loyer, Jeff
  5. » [SI-LIST] Signal Integrity Analysis Software, Mike Reynell
  6. » [SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda, Hargin, Bill
  7. » [SI-LIST] Routing of 12 GHz diff pairs, buck
  8. » [SI-LIST] Re: Routing of 12 GHz diff pairs, Guasti Giovanni
  9. » [SI-LIST] crosstalk-FastCap, manthos labropoulos
  10. » [SI-LIST] IEEE CPMT Society Phoenix Chapter - April 15 meeting announcement, Sam Karikalan
  11. » [SI-LIST] Lookig for Signal Integrity Position, SRCoe
  12. » [SI-LIST] Re: IBIS, si simulators, modeling and other sources of correlation error, Beal, Weston
  13. » [SI-LIST] Re: IBIS, si simulators, modeling and other sourcesof correlation error, Scott McMorrow
  14. » [SI-LIST] Analyzing noise in chip packages, Doug Smith
  15. » [SI-LIST] What is Latium Error??, Binosh Balachandra
  16. » [SI-LIST] Re: Coupled connector model, Corey Kimble
  17. » [SI-LIST] Re: What is Latium Error??, Muranyi, Arpad
  18. » [SI-LIST] loss tangent calculation, atifshamim khan
  19. » [SI-LIST] Re: What Latium is, Ingraham, Andrew
  20. » [SI-LIST] Re: Loss tangent calculation, Tabatchnick, Justin
  21. » [SI-LIST] test,I am a new member, maxiu
  22. » [SI-LIST] Language conventions, Doug Brooks
  23. » [SI-LIST] Re: Language conventions, Loyer, Jeff
  24. » [SI-LIST] R-T-F-M Re: Language conventions, Feldman, Richard
  25. » [SI-LIST] Re: R-T-F-M Re: Language conventions, Muranyi, Arpad
  26. » [SI-LIST] worst-case / best-case, Yoni Tzafrir
  27. » [SI-LIST] digital vector, Yoni Tzafrir
  28. » [SI-LIST] digital vector, Yoni Tzafrir
  29. » [SI-LIST] Re: digital vector, Ingraham, Andrew
  30. » [SI-LIST] Maxwell matrixes in Hspice, manthos labropoulos
  31. » [SI-LIST] PRBS generation for hspice, timoceous
  32. » [SI-LIST] Re: [SI-LIST]Language conventions, Henrik G. Madsen
  33. » [SI-LIST] measuring active-to-float time for PCI o/p buffer, adeel . ahmad
  34. » [SI-LIST] Material on SI in ASIC, Shripadaraj Annigeri
  35. » [SI-LIST] Re: stitched via shielding, Jim G Roberts
  36. » [SI-LIST] IBIS Modeling Tools, Paradis, Daniel
  37. » [SI-LIST] Signal Integrity Manager Position at AMD -- Austin, TX, Jonathan Dowling
  38. » [SI-LIST] Cat 5 cable properties..., Cesar Coba
  39. » [SI-LIST] question concerning socket for SDRAM module - mechanical problem?, Jan Vercammen
  40. » [SI-LIST] different Vmeas for Rising/Falling, SI Eng
  41. » [SI-LIST] Re: different Vmeas for Rising/Falling, Mirmak, Michael
  42. » [SI-LIST] Re: question concerning socket for SDRAM module - mechanical problem?, Matthew Humphreys
  43. » [SI-LIST] Standards, Rich Peyton
  44. » [SI-LIST] Question Concerning End Launch SMA connector., Gustavo Blando
  45. » [SI-LIST] Re: Question Concerning End Launch SMA connector., Tabatchnick, Justin
  46. » [SI-LIST] Fw: Question Concerning End Launch SMA connector., e.sweetman
  47. » [SI-LIST] Buffer Delay, Gil Gafni
  48. » [SI-LIST] serial loop-back causing clock error, Hong Shi
  49. » [SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX, Priyawrat Dewasthalee
  50. » [SI-LIST] Difference in simulations results between Hspice and Pspice-ORCAD., Parthasarathy Sampath
  51. » [SI-LIST] Re: Difference in simulations results between Hspice and Pspice-ORCAD., Raymond . Leung
  52. » [SI-LIST] Re: serial loop-back causing clock error, Raymond . Leung
  53. » [SI-LIST] PECL vs LVDS, hariharan
  54. » [SI-LIST] Test, Marowsky, Rich
  55. » [SI-LIST] TRST signal of JTAG I/F, Nico Fleurinck
  56. » [SI-LIST] Converting S-parameter to Inductance and Capacitance, H H Goh
  57. » [SI-LIST] Re: TRST signal of JTAG I/F, CJ Clark
  58. » [SI-LIST] Radiating Ceramic Bulk Capacitors, Paradis, Daniel
  59. » [SI-LIST] Re: Converting S-parameter to Inductance and Capacitance, Hassan O. Ali
  60. » [SI-LIST] Re: PECL vs LVDS, Ingraham, Andrew
  61. » [SI-LIST] help, Marowsky, Rich
  62. » [SI-LIST] unset [listname] vacation, Marowsky, Rich
  63. » [SI-LIST] Re: Radiating Ceramic Bulk Capacitors, Istvan Novak - Board Design Technology
  64. » [SI-LIST] a clocking scheme question, Peterson, James F (FL51)
  65. » [SI-LIST] Creating Cable Models in SPECCTRAquest, Geistlinger, Marlow K
  66. » [SI-LIST] Re: a clocking scheme question, MikonCons
  67. » [SI-LIST] Re: Buffer Delay, Raymond . Leung
  68. » [SI-LIST] Converting S-para to L,C --Si list, Eoin Mc Gibney
  69. » [SI-LIST] Twist ratio in a Cat 5 cable, Cesar Coba
  70. » [SI-LIST] IS DEPT TESTING EMAIL Filtering, Marowsky, Rich
  71. » [SI-LIST] SPICE model, Hong Shi
  72. » [SI-LIST] Backplane 'overaly' question, Bill Dempsey
  73. » [SI-LIST] LVDS Termination, Siders, Kenneth W
  74. » [SI-LIST] Re: SPICE model, Abhay Apte
  75. » [SI-LIST] Re: LVDS Termination, Tabatchnick, Justin
  76. » [SI-LIST] Series Termination Resistance, SUDARSHAN
  77. » [SI-LIST] FW: TRST signal of JTAG I/F, Nico Fleurinck
  78. » [SI-LIST] Re: Series Termination Resistance, David Schaefer
  79. » [SI-LIST] The return of nickel!, Boris Yost
  80. » [SI-LIST] Re: The return of nickel!, jeff_latourrette
  81. » [SI-LIST] Question: Circuit representation of partially filled soleniod withinductors., Abdulrahman Rafiq
  82. » [SI-LIST] Re: Immersion gold, Lee Ritchey
  83. » [SI-LIST] SMII interface imped design, qzheng
  84. » [SI-LIST] SPI03 ADVANCE REGISTRATION DEADLINE AND PROGRAM, Carla Giachino
  85. » [SI-LIST] search for clock oscillator, Nico Fleurinck
  86. » [SI-LIST] Re: search for clock oscillator, Clewell, Craig
  87. » [SI-LIST] Power distribution, Tom
  88. » [SI-LIST] Spiral Inductor, Vijay Varadarajan
  89. » [SI-LIST] TV tuner chips, Sankar karuppannan
  90. » [SI-LIST] Buffering 125MHz GMII signals, Samir Gundawar
  91. » [SI-LIST] Re: Buffering 125MHz GMII signals, Sankar karuppannan
  92. » [SI-LIST] DIMM power consumption, Lucas Bossetti
  93. » [SI-LIST] Re: Spiral Inductor, D G
  94. » [SI-LIST] pin type definition for Mentor Expedition, Kupper, Ingo
  95. » [SI-LIST] high speed digital design decoupling question, Nico Fleurinck
  96. » [SI-LIST] Test Message, Ahmad Fallah
  97. » [SI-LIST] coax to PCB transition - return loss, Perry Qu
  98. » [SI-LIST] Re: coax to PCB transition - return loss, Guasti Giovanni
  99. » [SI-LIST] Re: Does ferrite rod affect inductance ?, Vadim Heyfitch
  100. » [SI-LIST] New Software, Juan Manuel
  101. » [SI-LIST] New Software Question, webhugo-gcn
  102. » [SI-LIST] Measuring Crosstalk, Aaron Helleman
  103. » [SI-LIST] Help: how to create IBIS model for a chip which contains two dies, Lu
  104. » [SI-LIST] Seeking SI opportunities, win bery
  105. » [SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies, Crain, Dan S
  106. » [SI-LIST] Transceiver, Lim, Chia Nian
  107. » [SI-LIST] IBIS Model VT Curve Length, Moran, Brian P
  108. » [SI-LIST] What's difference between 3.5mm and SMA?, Moore Mo (Mo Daochun)
  109. » [SI-LIST] AD bus, Nimish Aggarwal
  110. » [SI-LIST] diff-pair, Nimish Aggarwal
  111. » [SI-LIST] via resistance, Paolo Peruzzi
  112. » [SI-LIST] Re: What's difference between 3.5mm and SMA?, Fasig, Jonathan L.
  113. » [SI-LIST] SPI4.2 over cable, Siva kumar
  114. » [SI-LIST] EPEP Books, Sainath Nimmagadda
  115. » [SI-LIST] Re: Help: how to create IBIS model for a chip which containstwo dies, Lu
  116. » [SI-LIST] Signal Integrity Engineer Seeking Position, e.sweetman
  117. » [SI-LIST] Re: Measuring Crosstalk, Crain, Dan S
  118. » [SI-LIST] Re: IBIS Model VT Curve Length, Donnelly, Mike
  119. » [SI-LIST] RS232 transmit and receive frequency, Youssef Khalife
  120. » [SI-LIST] [Q] Usual trace length for 64bit-wide bus using 250Mbps HSTL, cts
  121. » [SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice., penlmml
  122. » [SI-LIST] HSPICE 2003.03 W-element concern, Ed Sayre III
  123. » [SI-LIST] Electrical Modeling Consultants (Bay Area), Bob McCreight
  124. » [SI-LIST] Re: [Fwd: coax to PCB transition - return loss], Loyer, Jeff
  125. » [SI-LIST] test - please ignore, Dimiter Popoff
  126. » [SI-LIST] Re: Electrical Modeling Consultants (Bay Area), Bob McCreight
  127. » [SI-LIST] Common Mode Return Loss Measurements, Ray Anderson
  128. » [SI-LIST] EMI--bare board vs. case, Boris Yost
  129. » [SI-LIST] Re: Common Mode Return Loss Measurements, Loyer, Jeff
  130. » [SI-LIST] Center of Mass of Transistors., Parthasarathy Sampath
  131. » [SI-LIST] Re: EMI--bare board vs. case, Vishram Pandit
  132. » [SI-LIST] Validation of spiral inductors, Gurumurthy, Radhika
  133. » [SI-LIST] How to terminate the bi-directional buses?, C.Y. Cheng
  134. » [SI-LIST] Re: HSPICE 2003.03 W-element concern, Michael_Greim
  135. » [SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office., Steve . Wood
  136. » [SI-LIST] Re: Center of Mass of Transistors., Tom Biggs
  137. » [SI-LIST] N-port model limitations in simulators, Ray Anderson
  138. » [SI-LIST] Re: N-port model limitations in simulators, Muranyi, Arpad
  139. » [SI-LIST] spacing between via, hariharan
  140. » [SI-LIST] VNA Calibration for COAX Testing, Moeller, Merrick
  141. » [SI-LIST] series term + fanout = noise?, Boris Yost
  142. » [SI-LIST] Re: series term + fanout = noise?, Bill Dempsey
  143. » [SI-LIST] Re: VNA Calibration for COAX Testing, Moeller, Merrick
  144. » [SI-LIST] Help on Jtag Emulator connection for Debugging TI DSP, SUDARSHAN
  145. » [SI-LIST] Simulation error, Alicia Corrales Chanca
  146. » [SI-LIST] Re: Simulation error, jeff_latourrette
  147. » [SI-LIST] Looking for Spectrum Analyzer info, Gary Thompson
  148. » [SI-LIST] RS232 and RS422, Moustapha Abdi Hassan
  149. » [SI-LIST] Where can get RGB signal's spec?, Jack W.C. Lin
  150. » [SI-LIST] regarding noise in LVDS, jan man
  151. » [SI-LIST] FW: RS232 and RS422, Moustapha Abdi Hassan
  152. » [SI-LIST] transformer model, zanglinyuan
  153. » [SI-LIST] Test Loading Issues on Quad XTK, lting168
  154. » [SI-LIST] Re: Where can get RGB signal's spec?, Stuart Benner
  155. » [SI-LIST] Joined, VIKAS SHUKLA
  156. » [SI-LIST] Re: Test Loading Issues on Quad XTK, Abe Riazi
  157. » [SI-LIST] Gold plating reference(s), Fasig, Jonathan L.
  158. » [SI-LIST] Shape factors for sheet resistance based estimations, Jerry Martinson
  159. » [SI-LIST] DDR SDRAM Help Request, Paul Levin
  160. » [SI-LIST] Re: DDR SDRAM Help Request, Mangipudi, Prasad
  161. » [SI-LIST] Re: DDR SDRAM Hints, Paul Levin
  162. » [SI-LIST] Differential Signal at driver and intermediate points in xtk, VIKAS SHUKLA
  163. » [SI-LIST] Embedded capacitors, Steve Rogers
  164. » [SI-LIST] Embedded inductors, Steve Rogers
  165. » [SI-LIST] Re: Differential Signal at driver andintermediatepoints in xtk, Abe Riazi
  166. » [SI-LIST] Re: SDRAM bus termination, San Miguel, Shane
  167. » [SI-LIST] RMCEMC May Bonus Meeting, Grasso, Charles