Posts for si-list, 03-2003

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  1. » [SI-LIST] Re: 8b/10b program using MATLAB, Rotem Gazit
  2. » [SI-LIST] Request some information about renting SPECCTRAQuest Products ., Farzad Ebrahimi
  3. » [SI-LIST] Re: how to simulate with S parameters, Hassan O. Ali
  4. » [SI-LIST] Agenda (revised) , European IBIS Summit DATe 2003/Munich, Ralf Bruening
  5. » [SI-LIST] SI Guru, Cleland-Horn, Teresa
  6. » [SI-LIST] Canbus EMC/SI questions?, Javier del Valle
  7. » [SI-LIST] Decoupling a IC, Juan Manuel
  8. » [SI-LIST] Meeting Announcement: Silicon Valley Chapter - IPC Designers Council (March 11), Bob McCreight
  9. » [SI-LIST] 2.5GB/s data rate connector, Bob Patel
  10. » [SI-LIST] Re: 2.5GB/s data rate connector, Bergey, Dana
  11. » [SI-LIST] Plated through hole capacitance, Fitzgerald, Kevin
  12. » [SI-LIST] Hot Swapping for -5V, hariharan
  13. » [SI-LIST] NRZ signaling, sunil-chandra . kasanyal
  14. » [SI-LIST] Re: NRZ signaling, herbert_lage
  15. » [SI-LIST] Re: Hspice diff sim, Bi Han
  16. » [SI-LIST] measurement error, Doug Smith
  17. » [SI-LIST] Unlock the power of your backplane, LVDS tutorial, Eitan k
  18. » [SI-LIST] Differential signaling history, Zhou, Xingling (Mick)
  19. » [SI-LIST] Re: Differential signaling history, Ingraham, Andrew
  20. » [SI-LIST] Modeling a MUX/DEMUX?, Aspnes, Brian D
  21. » [SI-LIST] Skin Effect Calculation, Pat Diao
  22. » [SI-LIST] JEDEX Workshops on IBIS, Lynne Green
  23. » [SI-LIST] Re: Controlled Impedance Coupon Design, Ken Willis
  24. » [SI-LIST] Re: Loss Tangent of Solder Mask, Fasig, Jonathan L.
  25. » [SI-LIST] Re: simulating Mos in series, Parthasarathy Sampath
  26. » [SI-LIST] how to calculate board area & stack, mbestha
  27. » [SI-LIST] Modelling of Microwave Testing Microprobe (Cascade), Bi Han
  28. » [SI-LIST] is there any hspice to pspice convertor ?, Nimish Aggarwal
  29. » [SI-LIST] Instruments / Methods for measuring a cable's characteristic impedance, Peter Baxter
  30. » [SI-LIST] Inductance variation., GEORGE VARGHESE
  31. » [SI-LIST] Re: Inductance variation., Gaurav Agrawal
  32. » [SI-LIST] Re: is there any hspice to pspice convertor ?, Clewell, Craig
  33. » [SI-LIST] Re: how to calculate board area & stack, Paul Taddonio
  34. » [SI-LIST] Re: Instruments / Methods for measuring a cable'schara cteristic impedance, James_R_Jones
  35. » [SI-LIST] Re: Instruments / Methods for measuring a cable's characteristic impedance, Paul Levin
  36. » [SI-LIST] Re: question about IBIS's V-T curve Scaling ?, Muranyi, Arpad
  37. » [SI-LIST] Needed Manager "SI", Zeiger and Associates LLC
  38. » [SI-LIST] Re: Coupling THROUGH a plane?, Boris Yost
  39. » [SI-LIST] Re: Needed Manager "SI", Ray Anderson
  40. » [SI-LIST] Couple increased or decreased? (transmission line on silicon die), Bi Han
  41. » [SI-LIST] Crossing thick traces, Alex Horvath
  42. » [SI-LIST] Re: Length matching of source synchronous busses., Sparkman, Aubrey
  43. » [SI-LIST] IEEE Presentation download, Charles Grasso
  44. » [SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die), Raymond . Leung
  45. » [SI-LIST] (No Subject), GEORGE VARGHESE
  46. » [SI-LIST] High speed diff. lines connector, Edi Fraiman
  47. » [SI-LIST] Availability of IBIS models, Gaurav Agrawal
  48. » [SI-LIST] contact ESD, Russel Hughes
  49. » [SI-LIST] Sigrity seeks Applications Engineer, Teo Yatman
  50. » [SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die), D G
  51. » [SI-LIST] Bazooka balun verification., GEORGE VARGHESE
  52. » [SI-LIST] Analog/Digital Gnd, Parthasarathy Sampath
  53. » [SI-LIST] Re: Analog/Digital Gnd, James_R_Jones
  54. » [SI-LIST] Single-ended S-para plot of 2 microstrip traces, sam . sim
  55. » [SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces, Loyer, Jeff
  56. » [SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die), Raymond . Leung
  57. » [SI-LIST] Series termination, Edi Fraiman
  58. » [SI-LIST] Re: Series termination, Hofmann, Mark
  59. » [SI-LIST] Re: Zo vs Zin, Clewell, Craig
  60. » [SI-LIST] A presentation and more, Issa, Elie
  61. » [SI-LIST] Please Urgent, mmirfan
  62. » [SI-LIST] Re: Please Urgent, Bill Beale
  63. » [SI-LIST] Available SI engineering position, Simon Assouad
  64. » [SI-LIST] Re: A presentation and more, Faisal Baloch
  65. » [SI-LIST] Re: [IS-LIST] Please Urgent, Robert Kezer
  66. » [SI-LIST] Setting up Spectraquest to report capacitance for package design, Suk Hui Teh
  67. » [SI-LIST] NEED PCB PRODUCED WITH BLIND & BURIED VIAS ?, Steve Rogers
  68. » [SI-LIST] DDR Module A13 Pin Location, Jay Daugherty
  69. » [SI-LIST] Power Consumption of a bus, Lucas Bossetti
  70. » [SI-LIST] Re: Power Consumption of a bus, John Lin (???)
  71. » [SI-LIST] Connectors and PECL terminations, hariharan
  72. » [SI-LIST] Buried Vias and microvias, Juan Manuel
  73. » [SI-LIST] Loss in HSPICE W Element, Timothy Coyle
  74. » [SI-LIST] Problem with Ni plated transmission line, Daniel Kuchta
  75. » [SI-LIST] Measuring 0.13micron CMOS devices, srinivasan
  76. » [SI-LIST] Fw: Problem with Ni plated transmission line, Daniel Kuchta
  77. » [SI-LIST] Re: Measuring 0.13micron CMOS devices, San Miguel, Shane
  78. » [SI-LIST] Re: NEED PCB PRODUCED WITH BLIND & BURIED VIAS ?, SMITH, Andy (STV)
  79. » [SI-LIST] Re: Fw: Problem with Ni plated transmission line, Aubrey_Sparkman
  80. » [SI-LIST] Fw: Re: Fw: Problem with Ni plated transmission line, Daniel Kuchta
  81. » [SI-LIST] Re: Problem with Ni plated transmission line, Beal, Weston
  82. » [SI-LIST] Re: Buried Vias and microvias, Abe Riazi
  83. » [SI-LIST] Re: Fw: Re: Fw: Problem with Ni plated transmission line, Issa, Elie
  84. » [SI-LIST] Carlsbad, CA High Speed Design for PCB Designers: Routing and Terminating High Speed, Lori Lesnick
  85. » [SI-LIST] Measuring 1G+ signals, Alex Horvath
  86. » [SI-LIST] Re: Loss in HSPICE W Element, Alex Horvath
  87. » [SI-LIST] [SI-LIST]Re: Problem with Ni plated transmission line, Issa, Elie
  88. » [SI-LIST] Re: Signal Integrity and Zeiger, Grasso, Charles
  89. » [SI-LIST] S, ABCD and T parameters, Ray Anderson
  90. » [SI-LIST] SI conference/workshop in Germany?, Michael Khusid
  91. » [SI-LIST] Re: SI conference/workshop in Germany?, Muranyi, Arpad
  92. » [SI-LIST] Signal Integrity Contract, Janos Gaspar
  93. » [SI-LIST] low noise oscillators, C Deibele
  94. » [SI-LIST] Two requests, Doug Brooks
  95. » [SI-LIST] Re: Two requests, Swanson, Dan
  96. » [SI-LIST] One question left!!!!!, Doug Brooks
  97. » [SI-LIST] which is load and source treated, mbestha
  98. » [SI-LIST] Re: One question left!!!!!, Ross_Amans
  99. » [SI-LIST] Power plane thickness tolerance, Kon, Hon Lee
  100. » [SI-LIST] Trace width and current capacity, Harjeet Singh Randhawa
  101. » [SI-LIST] Flat Flex Cable Impedance, Christopher . Crowley
  102. » [SI-LIST] Re: Flat Flex Cable Impedance, Julian Ferry
  103. » [SI-LIST] Question on Impedance Control, Pat Diao
  104. » [SI-LIST] Re: Question on Impedance Control, Bill Beale
  105. » [SI-LIST] SI - VHDL, susanli_ucla
  106. » [SI-LIST] Doping effects., GEORGE VARGHESE
  107. » [SI-LIST] Looking for RF job in Canada, Steve Rogers
  108. » [SI-LIST] Re: Doping effects., GEORGE VARGHESE
  109. » [SI-LIST] current rating of wirebonds, Jan Vercammen
  110. » [SI-LIST] which is the Best routing Topology, Sudheer B S
  111. » [SI-LIST] Flat Flex Cable Impedance - Measurement, Peter Baxter
  112. » [SI-LIST] Ground setting in ADS of Agilent, Zhou Jinchang
  113. » [SI-LIST] How to model Output buffer with feedback in IBIS?, Yehuda Yizraeli
  114. » [SI-LIST] How to locate Lambda-Refine Mesh in HFSS?, Shi, Wenjunx
  115. » [SI-LIST] how to model connectors, mbestha
  116. » [SI-LIST] Printed Resistors, Steve Rogers
  117. » [SI-LIST] Reflections for dummies, San Miguel, Shane
  118. » [SI-LIST] hspice model for Giga Ethernet Tx/Rx, Guasti Giovanni
  119. » [SI-LIST] PCI Edge connector, Sankar karuppannan
  120. » [SI-LIST] SI/EMC Job Openings, 설병수
  121. » [SI-LIST] How to Zigzag trace!, peter zhu
  122. » [SI-LIST] Fwd: Comparison between Raphael and Hspice, Sudha Thiru
  123. » [SI-LIST] ask for comments on high frequency filter design, Wei Zhang
  124. » [SI-LIST] Job Opportunity, jeremy hillcrest
  125. » [SI-LIST] ePlanner(Scratchpad)/XTK from Innoveda, Aspnes, Brian D
  126. » [SI-LIST] Re: Coax vs. Microstrip, ray_waugh
  127. » [SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda, Alan Hilton-Nickel
  128. » [SI-LIST] Re: ask for comments on high frequency filter design, Steve Rogers
  129. » [SI-LIST] How to add parellel terminator in IBIS, Pang Ning (Peter)
  130. » [SI-LIST] ACHIEVABLE TOLERANCE OF PCB TRACE WIDTH ?, Steve Rogers
  131. » [SI-LIST] Re: Job Opportunity, Russel Hughes
  132. » [SI-LIST] Re: How to add parellel terminator in IBIS, Ingraham, Andrew
  133. » [SI-LIST] FW: How to add parellel terminator in IBIS, Jon Powell
  134. » (no subject), Suresh.K
  135. » [SI-LIST] Re: (no subject), San Miguel, Shane
  136. » [SI-LIST] Re: FW: How to add parellel terminator in IBIS, Muranyi, Arpad
  137. » [SI-LIST] HPSICE error, Bob Patel
  138. » [SI-LIST] PC Parallel port to 3V3, Ian Lewis
  139. » [SI-LIST] Ground clearance at connector vias, Fabrizio Zanella
  140. » [SI-LIST] laplace errors, Alicia Corrales Chanca
  141. » [SI-LIST] Re: Ground clearance at connector vias, Scott McMorrow
  142. » [SI-LIST] Re: PC Parallel port to 3V3, Christopher . Crowley
  143. » [SI-LIST] Re: HPSICE error, Ingraham, Andrew
  144. » [SI-LIST] Re: Temperature variable in SI simulation, Ingraham, Andrew
  145. » [SI-LIST] Re: laplace errors, Ingraham, Andrew
  146. » [SI-LIST] Hspice vs Raphael, Sudha Thiru
  147. » [SI-LIST] stitched via shielding, Denomme, Paul S.
  148. » [SI-LIST] Re: stitched via shielding, ray_waugh
  149. » [SI-LIST] Question about power delivery to silicon in a BGA package, Tegan Campbell
  150. » [SI-LIST] FW: Ground clearance at connector vias, Lawrence Williams
  151. » [SI-LIST] Re: Question about power delivery to silicon in a BGA package, Larry Barnes
  152. » [SI-LIST] EMI/EMC Engineer Job Opportunity, Westbrook, Scott
  153. » [SI-LIST] crosstalk-FastCap, manthos labropoulos
  154. » [SI-LIST] Re: : TDR extender cable, 1m, Tektronix PN 012-1220-00 for my 11801B scope., Doug Hopperstad
  155. » [SI-LIST] Need some Info on Inductance.., Abhijit Mahajan
  156. » [SI-LIST] SPI 4-2 question(s), Vadim Heyfitch
  157. » [SI-LIST] Re: Need some Info on Inductance.., Ray Anderson
  158. » [SI-LIST] Capacitor spice models which include dielectric losses, Harvey, Wilbur
  159. » [SI-LIST] PLL spectrum..., Tim Lu
  160. » [SI-LIST] PCB manufactures control impedance report!, Avi Hayun
  161. » [SI-LIST] Star-rcxt: About parameter priority of mapping file, Bi Han
  162. » [SI-LIST] Skew and Jitter, SI Eng
  163. » [SI-LIST] HyperLynx Lunch and Learn, Z_Hashemi
  164. » [SI-LIST] RC termination, Nimish Aggarwal
  165. » [SI-LIST] a problem about PLL bypass, lu Haizhao
  166. » [SI-LIST] Re: a problem about PLL bypass, Yehuda Yizraeli
  167. » [SI-LIST] Re: RC termination, Harjeet Singh Randhawa
  168. » [SI-LIST] Re: Capacitor spice models which include dielectric losses, Bart Bouma
  169. » [SI-LIST] SPI 2003 hotel reservation deadline, Carla Giachino
  170. » [SI-LIST] 1 analogic to 1 digital, Alicia Corrales Chanca
  171. » [SI-LIST] question regarding IBIS, ray_waugh
  172. » [SI-LIST] Re: Skew and Jitter, James_R_Jones
  173. » [SI-LIST] What software to design multilayer PCB, zhou lin