Posts for si-list, 03-2002

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  1. » [SI-LIST] Spice model for power subsystem., David Braendler
  2. » [SI-LIST] How does temperature and voltage change effect the output signal of the chip ?, Moore Mo (modaochun)
  3. » [SI-LIST] High Speed Serial Links Using LV Differential Receivers, Ron . J . Morneault
  4. » [SI-LIST] Re: Effect of USB attachment's current drawn through motherboard bypass network, John Barnes
  5. » [SI-LIST] Importance of Package Height, Steinkogler, Gary
  6. » [SI-LIST] Re: Even mode, common mode, and mode conversion, Doug Mckean
  7. » [SI-LIST] Re: Spice model for power subsystem., Juergen Flamm
  8. » [SI-LIST] Signal Integrity Engineer position open at Chelsio Communications, Lisa Williamson
  9. » [SI-LIST] Re: LC values for IBIS generation: mutual, self, or both?, Neeraj Pendse
  10. » [SI-LIST] Re: Optimal Power/ground lauout for a 2-layer PCB, Neeraj Pendse
  11. » [SI-LIST] Re: Inductance of Various Capacitor Paxkages, Neeraj Pendse
  12. » [SI-LIST] FREE-FEM, C Deibele
  13. » [SI-LIST] Re: Importance of Package Height, Brent DeWitt
  14. » [SI-LIST] GMII timings, Ramesh . Reddy
  15. » [SI-LIST] FFT/iFFT tool (for FREE), Tadashi Arai
  16. » [SI-LIST] Re: FREE-FEM, Dan Swanson
  17. » [SI-LIST] LVDS output impedance and teminations, Fritz, Karl E.
  18. » [SI-LIST] Re: Inverting PWL Current sources in HPSice, Ken Beach
  19. » [SI-LIST] E-M SOLVERS - HOW DO THEY WORK?, Steve Rogers
  20. » [SI-LIST] Split planes, Roberto Carretta
  21. » [SI-LIST] Re: Split planes, Ron Mancuso
  22. » [SI-LIST] Even mode and common mode, Doug Brooks
  23. » [SI-LIST] Re: Even mode and common mode, C Deibele
  24. » [SI-LIST] OUtput impedance measurement, Himanshu Arora
  25. » [SI-LIST] Start-up opening, Ed Priest
  26. » [SI-LIST] Has any one taken the Todd Hubing UMR video course on EMC....., Michael_Greim
  27. » [SI-LIST] VIA L and C values., Umesha
  28. » [SI-LIST] Re: VIA L and C values., Baranauskas, Dave
  29. » [SI-LIST] SI for a LVDS system, Mvvijay
  30. » [SI-LIST] help, Waleed Abdel-Hameed
  31. » [SI-LIST] Even mode and common mode- SI and EMC worlds, Eric Bogatin
  32. » [SI-LIST] X2Y 'zero' inductance caps, S Tatlow
  33. » [SI-LIST] lee richey course etc, Robison Michael R CNIN
  34. » [SI-LIST] Re: lee richey course etc, Michael_Greim
  35. » [SI-LIST] Specifying Clock to Out delay in IBIS Files, Abhijit Mahajan
  36. » [SI-LIST] C_comp in IBIS, Pritchard, Jason
  37. » [SI-LIST] Re: (no subject), Mark Alexander
  38. » [SI-LIST] AC coupling capacitors, Bob Patel
  39. » [SI-LIST] XTK analysis-help, Sivakumar S. - CTD, Chennai.
  40. » [SI-LIST] help , about boardside coupling impendence calc, qzheng
  41. » [SI-LIST] Spiral inductor L and Q measurement with VNA, Rafael Martinez
  42. » [SI-LIST] Re: Spiral inductor L and Q measurement with VNA, Dan Swanson
  43. » [SI-LIST] Series MOSFET IBIS models in SigXplorer, Hassan Ali
  44. » [SI-LIST] Re: Has any one taken the Todd Hubing UMR video course on EMC....., Peterson, George W
  45. » [SI-LIST] Re: Series MOSFET IBIS models in SigXplorer, Hassan Ali
  46. » [SI-LIST] Re: Using S-parameter files in HSPICE, Ted Mido
  47. » [SI-LIST] Re: Hspice encryption, Tracy Barclay
  48. » [SI-LIST] Re: C_comp in IBIS, Brad Griffin
  49. » [SI-LIST] Loss requirements in Infiniband spec..., ruston, matt
  50. » [SI-LIST] capacitive coupling to cables, Douglas C. Smith
  51. » [SI-LIST] SSTL2 characterisation, rajat . chauhan
  52. » [SI-LIST] Loss requirements in Infiniband spec. (si-list Digest V2 #70), Jay Diepenbrock
  53. » (no subject), Goutham . S
  54. » [SI-LIST] Model File, Himanshu Arora
  55. » [SI-LIST] 576MHz board design, Robison Michael R CNIN
  56. » [SI-LIST] Crosstalk, Ched-Chang Chai
  57. » [SI-LIST] clearance, Waleed Abdel-Hameed
  58. » [SI-LIST] 576MHz board design... again, Robison Michael R CNIN
  59. » [SI-LIST] trace configuration ??, Robison Michael R CNIN
  60. » [SI-LIST] Looking for someone I can bounce some ansoft questions off of off line....., Michael_Greim
  61. » [SI-LIST] Help On High Speed Interconnections, Giovanni Galiero
  62. » [SI-LIST] EMI Test Lab, Seol, Byongsu
  63. » [SI-LIST] SpectraQuest Question., fname lname
  64. » [SI-LIST] SPECCTRAQuest: DC level shift with series caps, Hassan O. Ali
  65. » [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps, Sanchez, Louis
  66. » [SI-LIST] SSO Analysis, scuba snail
  67. » [SI-LIST] Re: SpectraQuest Question., Moran, Brian P
  68. » [SI-LIST] Generating PRBS, Vadim Heyfitch
  69. » [SI-LIST] Re: Generating PRBS, Ray Anderson
  70. » [SI-LIST] microstrip and stripline FREE-FEM examples, C Deibele
  71. » [SI-LIST] SQ Question., fname lname
  72. » [SI-LIST] Re: SQ Question., Paglia, Frank M
  73. » [SI-LIST] Signal Integrity Venues, EADS,RICK (A-ColSprings,ex1)
  74. » [SI-LIST] FWD: Re: Re: SPECCTRAQuest: DC level shift with series caps, Hassan Ali
  75. » [SI-LIST] Decoupling Capacitors, Gil Gafni
  76. » [SI-LIST] PECL to ECL at 1GHz+, Bradley S Henson
  77. » [SI-LIST] Specctraquest Model ?, Ken Beach
  78. » [SI-LIST] Fourier Series, trapeziod, Doug Brooks
  79. » [SI-LIST] Re: Embedded Passives, Smith, Norm W
  80. » [SI-LIST] Re: Specctraquest Model ?, John Horner
  81. » [SI-LIST] Non monotonic EDGE on Clocks, Alokby, Ahmed
  82. » [SI-LIST] Re: Fourier Series, trapeziod, HaroldLSJ
  83. » [SI-LIST] Need for SI Service Bureaus?, Shawn Arnold
  84. » [SI-LIST] Re: Need for SI Service Bureaus?, Philip Germann
  85. » [SI-LIST] Power Supply Layout, Vrla, Cliff
  86. » [SI-LIST] Determining Edge rate, Tabatchnick, Justin
  87. » [SI-LIST] Series termination value, SEOW,ERWIN-SP (HP-Singapore,ex6)
  88. » [SI-LIST] Connector for LVDS, Steve Wolcott
  89. » [SI-LIST] Re: Connector for LVDS, Michael_Greim
  90. » [SI-LIST] Re: Series termination value, JNH
  91. » [SI-LIST] Few analog power supplies, where to short it., Yehuda Yizraeli
  92. » [SI-LIST] SI tool for a particular layer stackup, Craciun, Liviu-Dumitru
  93. » [SI-LIST] see the attached PDF-File - SI tool for a particular layer stackup, Craciun, Liviu-Dumitru
  94. » [SI-LIST] ASIC PKG for PCI-X, Smith, Norm W
  95. » [SI-LIST] Re: Turn on oscillation power analysis, Michael Nudelman
  96. » [SI-LIST] simulation in SCRATCHPAD, k EPD
  97. » [SI-LIST] Job opening, Ozgur Misman
  98. » [SI-LIST] inter-power-converter coupling, Zabinski, Patrick J.
  99. » [SI-LIST] Re: IBIS Model Quality (or lack thereof), Waseem Tariq
  100. » [SI-LIST] Re: IBIS Model Quality (or lack thereof)- Cleansing service, Joe Socha
  101. » [SI-LIST] logic analyzer probes on LVDS, evillaf
  102. » [SI-LIST] Fwd: IBIS Model Quality (or lack thereof), Dave Macemon
  103. » [SI-LIST] Looking for Teradyne SI contact information......., Michael_Greim
  104. » [SI-LIST] Interpretation of XTK results, Joe Young
  105. » [SI-LIST] TDR's and ESD Protection, JOHN SAWDY
  106. » [SI-LIST] Re: logic analyzer probes on LVDS, Muhammad Sagarwala
  107. » [SI-LIST] Frequency spectrum of SONET data, Bob Patel
  108. » [SI-LIST] Re: Frequency spectrum of SONET data, Paglia, Frank M
  109. » [SI-LIST] Re: TDR's and ESD Protection, Loyer, Jeff W
  110. » [SI-LIST] High Speed Digital design education?, Inmyung Song
  111. » [SI-LIST] Re: High Speed Digital design education?, Devrim Fidanci
  112. » [SI-LIST] XTK error, Sivakumar S. - CTD, Chennai.
  113. » [SI-LIST] Why does lamination fail to prevent eddy currents at high frequencies?, Steve Rogers
  114. » [SI-LIST] Re: Question on split termination, Dr. Howard Johnson
  115. » [SI-LIST] Re: XTK error, Marc Humphreys
  116. » [SI-LIST] S-parameter to SPICE, Hassan Ali
  117. » [SI-LIST] backplane connector, Dr. Howard Johnson
  118. » [SI-LIST] Re: S-parameter to SPICE, Clewell, Craig
  119. » [SI-LIST] Message submitted to 'si-list', Ray Anderson
  120. » [SI-LIST] Re: backplane connector, Julian Ferry
  121. » [SI-LIST] Stitching Capacitors, Split-planes & Return Currents ?, Simba Julian
  122. » [SI-LIST] IBIS MODEL QUESTION, =?big5?b?U3RhbmxleS5DaGl1KKr0q6uyTSk=?=
  123. » [SI-LIST] IBIS Model of the CMOS PECL ?????, 김치원
  124. » [SI-LIST] Re: Why does lamination fail to prevent eddy currents at high frequencies?, Steve Rogers
  125. » [SI-LIST] Re: Nagel's Thesis, Roberto Ciaranfi
  126. » [SI-LIST] What should be checked on ASIC, Bob Patel
  127. » [SI-LIST] Re: RDRAM termination, Baranauskas, Dave
  128. » [SI-LIST] Re: Stitching Capacitors, Split-planes & Return Currents ?, Patrick_Carrier
  129. » [SI-LIST] Re: Why does lamination fail to prevent eddy currents at high frequencies?, Ray Anderson
  130. » [SI-LIST] Re: IBIS MODEL QUESTION, Ingraham, Andrew
  131. » [SI-LIST] test, Vadim Heyfitch
  132. » [SI-LIST] ATA 100 bus simulation, =?big5?b?U3RhbmxleS5DaGl1KKr0q6uyTSk=?=
  133. » [SI-LIST] Re: ISF2XTK error-Urgent-Urgent, Wilco Hamhuis