Posts for si-list, 02-2006

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  1. » [SI-LIST] Differential impedance signals?????, kishore bachu
  2. » [SI-LIST] .tr0 file viewer, Naren Thesia
  3. » [SI-LIST] European IBIS Summit at DATe 2006 - Third Call for Paper/Call for Participation, Ralf Bruening
  4. » [SI-LIST] Reflected Wave Switching - Silly Question., Kedar P Apte
  5. » [SI-LIST] simulating mobile phone effects on circuits, Doug Smith
  6. » [SI-LIST] PHY PCS, Ravindra Johari
  7. » [SI-LIST] Re: PHY PCS, Edi Fraiman
  8. » [SI-LIST] edge coupled coated microstrip differential impedance, jerry_hu
  9. » [SI-LIST] Re: edge coupled coated microstrip differential impedance, Grasso, Charles
  10. » [SI-LIST] Session of interest to SI engineers at DesignCon 2006, Pratt, Gary
  11. » [SI-LIST] help me, jagaveer25
  12. » [SI-LIST] Re: help me, zhangkun 29902
  13. » [SI-LIST] Re: edge coupled coated microstrip differentialimpedance, Lee Ritchey
  14. » [SI-LIST] Devlopment Eng. R.F. Filter Connectors, bruce harvie
  15. » [SI-LIST] File Extension .fig, Jim Antonellis
  16. » [SI-LIST] Re: File Extension .fig, Ray Anderson
  17. » [SI-LIST] Good book, prasadsa
  18. » [SI-LIST] Analog/mixed signal Contract Engineer position, Priest, Edward
  19. » [SI-LIST] Re: Good book, Doug Martens
  20. » [SI-LIST] Ground/Power electrical modeling battery powered devices, Eoin Mc Gibney
  21. » [SI-LIST] unsubscribe, Rane Hana
  22. » [SI-LIST] Immunity to nearby wireless devices and EE undergrad programs, Doug Smith
  23. » [SI-LIST] Ethernet Multiplexers/Switches, Kedar P Apte
  24. » [SI-LIST] HSPICE - adding jitter to ethernet serial link, Ali Burney
  25. » [SI-LIST] Re: HSPICE - adding jitter to ethernet serial link, Ed Sayre III
  26. » [SI-LIST] Skewed Silicon Parameters, james_r_jones
  27. » [SI-LIST] Reflections, Babid A
  28. » [SI-LIST] Re: Reflections, Mike Greim
  29. » [SI-LIST] Interesting announcement regarding IBIS 4.1, Pratt, Gary
  30. » [SI-LIST] Re: 3D tool: CST / HFSS, LI QIANG-R58304
  31. » [SI-LIST] AC termination, #CHUANG KENG HUA#
  32. » [SI-LIST] Signal Integrity Engineering position at Intel Corporation, Grossman, Brett
  33. » [SI-LIST] Xilinx simulation model validation, Buchs, Kevin J.
  34. » [SI-LIST] currnet through wire bond, Kamran Azizi
  35. » [SI-LIST] Microprocessor Platform Impedance. Characterization using VTT Tools, Heinrich.Smith
  36. » [SI-LIST] [OFF-TOPIC] Signal Integrity Simplified book, Rui Pimenta
  37. » [SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book, Clewell, Craig
  38. » [SI-LIST] Re: currnet through wire bond, Christopher.Jakubiec
  39. » [SI-LIST] Capacitor Arrays for clock AC coupling, David Greig
  40. » [SI-LIST] Fwd: EMCS-SCV Chapter Meeting, Tuesday February 14, 2006, Ahmad Fallah
  41. » [SI-LIST] Differential Impedance of PCB Vias, Hirshtal Itzhak
  42. » [SI-LIST] Signal Integrity Simplified book, Eric Bogatin
  43. » [SI-LIST] Analog, "low-noise", "high frequency", board-level designer needed!, Kevin Pierpoint
  44. » [SI-LIST] Re: Package SI vs PCB SI, Hassan O. Ali
  45. » [SI-LIST] Re: Package SI vs. PCB SI, Haller, Robert
  46. » [SI-LIST] QLOGIC Ref. Designs, Kamran Azizi
  47. » [SI-LIST] Re: Differential Impedance of PCB Vias, Hirshtal Itzhak
  48. » [SI-LIST] Ethernet standards coding and data frequency, Jean_Pierre . Bouthemy
  49. » [SI-LIST] controlling test variables during troubleshooting, Doug Smith
  50. » [SI-LIST] Re: DesignCon 2006 material on power distribution network design methodologies posted, Istvan Novak - Board Design Technology
  51. » [SI-LIST] Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents, Alex Horvath
  52. » [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents, Aubrey_Sparkman
  53. » [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents, Alex Horvath
  54. » [SI-LIST] FW: Re: currnet through wire bond, jeff.latourrette
  55. » [SI-LIST] SI Employment Opportunity at Altera: Posting, Larry Smith
  56. » [SI-LIST] Looking for mini x12 board to cable system......., Mike Greim
  57. » [SI-LIST] Electrical wiring questions, Mike S.
  58. » [SI-LIST] Re: currnet through wire bond: correction, dgun
  59. » [SI-LIST] Re: Electrical wiring questions, dgun
  60. » [SI-LIST] Re: Digest Number 1730, Faraydon Pakbaz
  61. » [SI-LIST] S-parameter to Circuit Model extraction?, 델타소년
  62. » [SI-LIST] help request: 3D model library, Ing. Giancarlo Guida
  63. » [SI-LIST] Re: S-parameter to Circuit Model extraction?, ChangMyung RYU
  64. » [SI-LIST] SATA II Electrical Specification, Cortex.Chen
  65. » [SI-LIST] Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic, Jai Shanker
  66. » [SI-LIST] optimization of curve-fit data, Zabinski, Patrick J.
  67. » [SI-LIST] DDR2 design, Ivor Bowden
  68. » [SI-LIST] Re: DDR2 design, Chris Cheng
  69. » [SI-LIST] Ground Pour in Signal Layers, Pradeep RSA
  70. » [SI-LIST] Re: Ground Pour in Signal Layers, Yuming Tao
  71. » [SI-LIST] ICM 1.1 approved as an ANSI standard!, Mirmak, Michael
  72. » [SI-LIST] Looking for 3D fullwave EM modeling tools, Mohammad Ali
  73. » [SI-LIST] Re: Looking for 3D fullwave EM modeling tools, Grasso, Charles
  74. » [SI-LIST] Why do we use transformer for DC blocking in ethernet connection ?, glenchen
  75. » [SI-LIST] What is correctly placement of Transformer? Locate Near IC or RJ45 CONN? Why?, ªü¥È
  76. » [SI-LIST] cable discharge, devices, and standards, Doug Smith
  77. » [SI-LIST] Macromodeling software available from Politecnico di Torino, sivi.cla@xxxxxxxxx
  78. » [SI-LIST] Re: What is correctly placement of Transformer? Locate Near IC or RJ45 CONN? Why?, Curt McNamara
  79. » [SI-LIST] Re: Type of Driver, Dr. Edward P. Sayre
  80. » [SI-LIST] Integrated vs. discrete magnetics for Ethernet, Chauhan, Prakash
  81. » [SI-LIST] European IBIS Summit at DATe 2006 - Final Call for Paper/Call for Participation, Ralf Bruening
  82. » [SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet, Chris Padilla (cpad)
  83. » [SI-LIST] Re: Why do we use transformer for DC blocking in ethernet connection ?, Tang, George
  84. » [SI-LIST] How to convert Hspice model, Joel Brown
  85. » [SI-LIST] Re: How to convert Hspice model, Hargin, Bill
  86. » [SI-LIST] FW: RE: DDR2 design, Dhiraj Kiran