Posts for si-list, 02-2005

  1. Home
  2. si-list
  3. Archive
  4. 02-2005

Browse: Last Month: 01-2005    Main Archive Page    Next Month: 03-2005

By Date / By Date Reverse / By Threads

  1. » [SI-LIST] - Difference between High Current Low Voltage and Low Current High Voltage circuits, rajneesh.raveendran
  2. » [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES, john
  3. » [SI-LIST] a simple question, ahmad_s03
  4. » [SI-LIST] PCB high Speed Design books, Gopalakrishnan Sethuraj
  5. » [SI-LIST] Deadline Extension SPI 2005, Andre Grabinski
  6. » [SI-LIST] Re: capacitor impedance in time domain, Steve Corey
  7. » [SI-LIST] Re: - Difference between High Current Low Voltage and Low Current High Voltage circuits, Thiago Wellington Joazeiro Almeida
  8. » [SI-LIST] Re: Coupled & Lossy Line Model Validation Structure, Nicklas
  9. » [SI-LIST] RMCEMC January presentation download available, Grasso, Charles
  10. » [SI-LIST] Allegro PCB-SI "Model Integrity" for IBIS Development, Rohan Hubli
  11. » [SI-LIST] Re: Allegro PCB-SI "Model Integrity" for IBIS Development, lgreen
  12. » [SI-LIST] Post Designcon thread, Chris Cheng
  13. » [SI-LIST] Fan-out in TTL and CMOS, Ummalaneni, Venu Babu (Venu)
  14. » [SI-LIST] Re: Post Designcon thread, Peterson, James F (FL51)
  15. » [SI-LIST] DDR-1 termination (short point-to-point), Anders Frederiksen
  16. » [SI-LIST] Re: DDR-1 termination (short point-to-point), De Paepe, Kristiaan
  17. » [SI-LIST] Re: Fan-out in TTL and CMOS, Lee Ritchey
  18. » [SI-LIST] Is there other SI tool that similar to ICX?, an . le
  19. » [SI-LIST] Re: Fan-out in TTL and CMOS--> There are some interesting high speed parts available in ECL, Salkow, Steven
  20. » [SI-LIST] Query CMOS FPGA interface, Himanshu Arora
  21. » [SI-LIST] more data on plane breaks, Doug Smith
  22. » [SI-LIST] Reference plane resonance, Joe Paul
  23. » [SI-LIST] inductance of differential stripline, Mark Burford
  24. » [SI-LIST] Re: Is there other SI tool that similar to ICX?, Zanella, Fabrizio
  25. » [SI-LIST] DesignCon Papers, Scott McMorrow
  26. » [SI-LIST] How to Measure Inductance of Pads, Vias, and Planes, dsfarwell1
  27. » [SI-LIST] Feb-2005 IEEE-EMCS Santa Clara Valley chapter meeting, Ahmad Fallah
  28. » [SI-LIST] Re: inductance of differential stripline, Joe Paul
  29. » [SI-LIST] about golden standard, walter steffe
  30. » [SI-LIST] Re: DesignCon Papers, Peterson, James F (FL51)
  31. » [SI-LIST] Near End TDR Measurement/Simulation, package_char
  32. » [SI-LIST] S-Parameter manipulations, papa_doc
  33. » [SI-LIST] Simple H-Spice Question, gsletch
  34. » [SI-LIST] Re: How to Measure Inductance of Pads, Vias, and Planes: Can ESL be defined as a property of the capacitor?, Pommerenke, David
  35. » [SI-LIST] Re: S parameter manipulations, Craig Clewell
  36. » [SI-LIST] Re: Cascading T-Lines, Craig Clewell
  37. » [SI-LIST] Re: about golden standard, Dan Piscotty
  38. » [SI-LIST] Re: S-Parameter manipulations, Beal, Weston
  39. » [SI-LIST] routing of Ethernet pairs, unasdoma
  40. » [SI-LIST] inductance of coupled shielded odd mode stripline, Mark Burford
  41. » [SI-LIST] Re: routing of Ethernet pairs, Joe Paul
  42. » [SI-LIST] Re: SI-related Cartoon, Elya B. Joffe
  43. » [SI-LIST] SPICE flattening, Yaron Kretchmer
  44. » [SI-LIST] Re: SPICE flattening, Yaron Kretchmer
  45. » [SI-LIST] Formula page and guides on SI, Pavel Stessin
  46. » [SI-LIST] Re: Formula page and guides on SI, Curt McNamara
  47. » [SI-LIST] Presentations from IBIS Summit at DesignCon 2005 now on-line!, Mirmak, Michael
  48. » [SI-LIST] SI analysis input parameters, nagaraj
  49. » [SI-LIST] S-parameter passivity, johndp
  50. » [SI-LIST] Re: SI analysis input parameters, David Kaiser
  51. » [SI-LIST] Hspice vs. Eldo w hspice compatibility mode, Eric Steimle
  52. » [SI-LIST] RMCEMC Career Ops page Update, Grasso, Charles
  53. » [SI-LIST] Switch On & Switch Off Clicks due to Amplifier noise, Adeel Malik
  54. » [SI-LIST] Re: Switch On & Switch Off Clicks due to Amplifier noise, steve weir
  55. » [SI-LIST] checking consistency between behavioural and .lib view od HARDIPs, Venkateswara Rao. K
  56. » [SI-LIST] FW: Re: Switch On & Switch Off Clicks due to Amplifier noise, Adeel Malik
  57. » [SI-LIST] Re: S-parameter passivity, Ray Anderson
  58. » [SI-LIST] RMCEMC Career Ops Update - URL included, Grasso, Charles
  59. » [SI-LIST] 50 Gbps interconnect paper, Scott McMorrow
  60. » [SI-LIST] designof a fault tolerant clock, syed ahmed
  61. » [SI-LIST] Re: Hspice vs. Eldo w hspice compatibility mode, Ambrish Varma
  62. » [SI-LIST] New College Graduate SI Opportunity, Westbrook, Scott
  63. » [SI-LIST] posted: DesignCon TecForum TF7 on Inductance of Bypass Capacitors, Istvan Novak
  64. » [SI-LIST] FLOATING NODE IN PSPICE, praveen_vrec_123
  65. » [SI-LIST] Re: FLOATING NODE IN PSPICE, Craig Clewell
  66. » [SI-LIST] SPICE Flattener, Plane Breaks, Benchmarking, burke_ipc
  67. » [SI-LIST] Are Lead Free fully backwards compatible?, Zilber Gil
  68. » [SI-LIST] single end and bused trace question, ma mu
  69. » [SI-LIST] Stackups with Microvias, Chris McGrath
  70. » [SI-LIST] Basic DDRII question, Tegan Campbell
  71. » [SI-LIST] Re: Stackups with Microvias, rsefton
  72. » [SI-LIST] Re: Intel Motherboard with DDR2, Moran, Brian P
  73. » [SI-LIST] Single ended clock from differential clock source, Pfeifer, Alan
  74. » [SI-LIST] European IBIS Summit @ DATe 2005 - Third Call for Participation, Ralf Bruening
  75. » [SI-LIST] support, praveen_vrec_123
  76. » [SI-LIST] Re: support, Curt McNamara
  77. » [SI-LIST] Skin Effect, Au, and Cu, richard moffat
  78. » [SI-LIST] Re: Skin Effect, Au, and Cu, Aubrey_Sparkman
  79. » [SI-LIST] Converting SPICE rlgc files into ADS, Henrique Miranda
  80. » [SI-LIST] Re: Skin Effect, Au, and Cu-->More details..., richard moffat
  81. » [SI-LIST] Current Seminars on High-Speed Issues, Americomrh
  82. » [SI-LIST] Re: si-list Digest V5 #82, Clayton Wrobel
  83. » [SI-LIST] DDR2 DIMM question, Aleksandar Djokic
  84. » [SI-LIST] Antwort: Re: Skin Effect, Au, and Cu, Matthias Bergmann
  85. » [SI-LIST] using spice to calculate driver output impedance, eric steimle
  86. » [SI-LIST] ICM Draft Ver. 1.1 documents now available for review, Mirmak, Michael
  87. » [SI-LIST] Electrically conductive Epoxy, feicaguo
  88. » [SI-LIST] Driver Output Impedance am I doing this correctly?, eric steimle
  89. » [SI-LIST] Re: using spice to calculate driver output impedance, Salkow, Steven
  90. » [SI-LIST] How to get the load capacitance of input buffer by means of HSPICE model, Zhangkun
  91. » [SI-LIST] Re: Looking for information on AMS Modeling, Abdulrahman Rafiq
  92. » [SI-LIST] LVDS Simulation?, \xBC\xDB\xC0θ\xED
  93. » [SI-LIST] R: LVDS Simulation?, Guasti Giovanni
  94. » [SI-LIST] Re: R: LVDS Simulation?, steve weir
  95. » [SI-LIST] Necessity of Ground signal for RS485 transmission at 500 ft cable length, Adeel Malik
  96. » [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length, steve weir
  97. » [SI-LIST] Dielectric nature of Substrate, Manish Bhakuni
  98. » [SI-LIST] Good physical description of skin effect, Mark Burford
  99. » [SI-LIST] Re: Converting SPICE rlgc files into ADS, Grossman, Brett
  100. » [SI-LIST] Re: si-list Digest V5 #86, Daniel Chow
  101. » [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length, Curt McNamara
  102. » [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length, steve weir
  103. » [SI-LIST] Re: Necessity of Ground signal for RS485 transmission at 500 ft cable length, steve weir
  104. » [SI-LIST] S2IBIS3 V1.0 released., Ambrish Varma
  105. » [SI-LIST] IBIS and SI talks at Mentor' User2User Conference, lgreen
  106. » [SI-LIST] DDR simulation, Zhangkun
  107. » [SI-LIST] Hi this is Manish, Manish Bhakuni
  108. » [SI-LIST] creating an IBIS model..., zhangfeng
  109. » [SI-LIST] Re: DDR simulation, Moran, Brian P
  110. » [SI-LIST] Re: Electrically conductive Epoxy, msharpes