Posts for si-list, 01-2013

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  1. » [SI-LIST] 答复: Single-point grounding and multi-point grounding, Shao, Peng
  2. » [SI-LIST] 答复: DDR3 Crosstalk, Shao, Peng
  3. » [SI-LIST] Asymmetric differential stripline impedance, Hithesh
  4. » [SI-LIST] PDN material required, Karthik P
  5. » [SI-LIST] IBIS Summit at DesignCon 2013 - Third Call for Participation and Presentations, Mirmak, Michael
  6. » [SI-LIST] how to include PCIE test fixture into SI simulation, goodluckjiayuan
  7. » [SI-LIST] shunt voltage reference, Sudarshan H c
  8. » [SI-LIST] Bogatin talk in Huntsville Jan 10, Eric Bogatin
  9. » [SI-LIST] Fiber Weave Effect, Dudi Tash
  10. » [SI-LIST] Re: Fiber Weave Effect, Dudi Tash
  11. » [SI-LIST] Sr. SI Engineer (10G+, Backplane Architect) needed at Huawei in Santa Clara, CA;, Mark Apton
  12. » [SI-LIST] DesignCon 2013 - mEEt and gEEk, Jim Nadolny
  13. » [SI-LIST] Stackup for insertion loss control ownership, Loyer, Jeff
  14. » [SI-LIST] PPM measurement for reference clock, jun li
  15. » [SI-LIST] SI Engineer, Gina Weber
  16. » [SI-LIST] AW: Stackup for insertion loss control ownership--Resend, Havermann, Gert
  17. » [SI-LIST] Crystal Clock Random Jitter, vinod ah
  18. » [SI-LIST] Reference layers for high speed diff pairs, Ilan Wolff
  19. » [SI-LIST] FW:, Philip Wetmore
  20. » [SI-LIST] Hello check this out(Properties), Muhammad Nazir
  21. » [SI-LIST] Dynamic phase compensation in SERDES layout, Xiaoguang Tsai
  22. » [SI-LIST] Testing question about oscilloscope, Zhangkun (Zkun)
  23. » [SI-LIST] usb eye pattern tuning, Li Hui
  24. » [SI-LIST] Re: usb eye pattern tuning, Li Hui
  25. » [SI-LIST] 答复: Re: Dynamic phase compensation in SERDES layout, 蔡晓光
  26. » [SI-LIST] 答复: Dynamic phase compensation in SERDES layout, 蔡晓光
  27. » [SI-LIST] Opening for SI Engineer at Intel, Garrison, Gene
  28. » [SI-LIST] Diff pair Impedance question, Hithesh
  29. » [SI-LIST] CDR with SJ > 1UI, vinod ah
  30. » [SI-LIST] DDR3 termination modes during READ and WRITE operation?, Mik Nazaryan
  31. » [SI-LIST] IBIS Summit at DesignCon 2013 - Final Call for Participation and Presentations, Mirmak, Michael
  32. » [SI-LIST] XAUI interface, Balamanikandan K
  33. » [SI-LIST] Differential mode impedance of common mode filter, 李晖
  34. » [SI-LIST] equal length requirement for SDRAM signals, 李磊
  35. » [SI-LIST] Looking for the full time assignment as a Signal Integrity Engineer, Shiva Jilla
  36. » [SI-LIST] Behavioral modeling tutorial at DesignCon- Ibis/Matlab/veriloga and mixed signal extensions, Helene Thibieroz
  37. » [SI-LIST] Invitation to "Ask the Expert" Panel on Wed 1 pm at DesignCon, Eric Bogatin
  38. » [SI-LIST] Ground Connection for Current Probe, vinod ah
  39. » [SI-LIST] Re: Ground Connection for Current Probe, Dandy, Jonathan S
  40. » [SI-LIST] [Job Opportunity] Signal/Power Integrity Applications Engineer, Hazlina Ramly
  41. » [SI-LIST] SI Sweep Simulation ?, Mik Nazaryan
  42. » [SI-LIST] DDR2/3 and tQH/tQHS, Conrad Herse
  43. » [SI-LIST] Re: AW: Re: Reference layers for high speed diff p, Sen Velmurugan
  44. » [SI-LIST] HSPICE SIG event during DesignCon, Helene Thibieroz
  45. » [SI-LIST] SI and EMI Courses, Americomrh
  46. » [SI-LIST] Random Jitter Value varies with Data pattern, vinod ah
  47. » [SI-LIST] How can we differentiate the SPICE models ?, Balamanikandan K
  48. » [SI-LIST] DDR3 Multi Rank Working ODT, shankar san
  49. » [SI-LIST] contact & cost for VNA testing with microprobes, axel stein
  50. » [SI-LIST] Final reminder... Arvind Reddy has added you on SkillPages, SkillPages Team
  51. » [SI-LIST] Re: contact & cost for VNA testing with microprobes, jjcarrillo2002