Posts for si-list, 01-2002

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  1. » [SI-LIST] Re: SI Engineer Qualification, Greim, Michael
  2. » [SI-LIST] Re: Reflection and EMI, Ken Cantrell
  3. » [SI-LIST] Re: Equation, Doug McKean
  4. » [SI-LIST] Re: SA12E Vil and Vih, D. C. Sessions
  5. » [SI-LIST] Papers Available, Lynne Green
  6. » [SI-LIST] cable induced circuit damage and corruption, Douglas C. Smith
  7. » [SI-LIST] 4 corner test, =?big5?b?Um9nZXIuV3UgKKdkrVqqTCk=?=
  8. » [SI-LIST] Flux, Rich Peyton
  9. » [SI-LIST] Re: Flux, Bill Dempsey
  10. » [SI-LIST] Patterns for testing 100Base-T PHY layer, Bob Patel
  11. » [SI-LIST] Buried Resistor, BRIGHT ZHOU
  12. » [SI-LIST] Fwd: Re: LVPECL -to-LVDS translator, Ed Miguel
  13. » [SI-LIST] Re: Fwd: Re: LVPECL -to-LVDS translator, ptn-support
  14. » [SI-LIST] job postings, Douglas C. Smith
  15. » [SI-LIST] MBS2IS, Inmyung Song
  16. » [SI-LIST] Use of Tenting Phenomena during Solder Masking, Adeel Malik
  17. » [SI-LIST] IBIS European Summit Meeting Announcment 3/8/02, Ross, Bob
  18. » [SI-LIST] Etch back - plating tail effect, Rebelo, Ashley (Ash)
  19. » [SI-LIST] Re: Use of Tenting Phenomena during Solder Masking, Sandor Daranyi
  20. » [SI-LIST] Re: Etch back - plating tail effect, Ozgur Misman
  21. » [SI-LIST] Source impedance?, David Kaiser
  22. » [SI-LIST] Re: Source impedance?, Muranyi, Arpad
  23. » [SI-LIST] PCB Fabrication Details, Adeel Malik
  24. » [SI-LIST] AW: PCB Fabrication Details, Craciun, Liviu-Dumitru
  25. » [SI-LIST] Re: PCB Fabrication Details, Zabinski, Patrick J.
  26. » [SI-LIST] Total load capacitance, Bob Patel
  27. » [SI-LIST] IBIS Driver Models, Simulators and CComp, Todd Westerhoff
  28. » [SI-LIST] Re: IBIS Driver Models, Simulators and CComp, Muranyi, Arpad
  29. » [SI-LIST] Ground plane voids under Tip/Ring, Bob Patel
  30. » [SI-LIST] SSTL and the series resistor, Allan Davidson
  31. » [SI-LIST] SV: Total load capacitance, Anders Ekholm (ERA)
  32. » [SI-LIST] Differential S-parameters, Zabinski, Patrick J.
  33. » [SI-LIST] Re: Ground plane voids under Tip/Ring, pwelling
  34. » [SI-LIST] Re: Differential S-parameters, samir_aboulhouda
  35. » [SI-LIST] Re: SV: Total load capacitance, Ingraham, Andrew
  36. » [SI-LIST] Impedance & crosstalk calculation, Bob Patel
  37. » [SI-LIST] BUS LVDS Spec?, Bradley S Henson
  38. » [SI-LIST] Re: BUS LVDS Spec?, Cui, Wilson
  39. » [SI-LIST] GigaTest Events: January, Gary Otonari
  40. » [SI-LIST] Re: hspice question - urgent, Adam . Tambone
  41. » [SI-LIST] E1/T1/E3/T3 requirements, Bob Patel
  42. » [SI-LIST] Re: E1/T1/E3/T3 requirements, Sandor Daranyi
  43. » [SI-LIST] Question about SSTL Termination, arsenault, brian
  44. » [SI-LIST] Re: Question about SSTL Termination, Aubrey_Sparkman
  45. » [SI-LIST] Impedance Discontinuity @ SMA connector, Suresh Sivasubramaniam
  46. » [SI-LIST] Re: Impedance Discontinuity @ SMA connector, pwelling
  47. » [SI-LIST] Running mks2i, Khalid Ansari
  48. » [SI-LIST] Package Frequency?, Pat Diao
  49. » [SI-LIST] a query about HSTL I/O, Sachin Kadu
  50. » [SI-LIST] Re: Package Frequency?, Pat Diao
  51. » [SI-LIST] Labview Drivers for HP 71501 Jitter Analyzer / BERT, Ray Anderson
  52. » [SI-LIST] Ground bounce issue in FPGA?, Chris Bobek
  53. » [SI-LIST] Re: Ground bounce issue in FPGA?, Charles Anderson
  54. » [SI-LIST] Re: Signal integrity -- training in XTK simulation software, Greim, Michael
  55. » [SI-LIST] IEEE CPMT inaugural meeting in Portland, OR area, Grossman, Brett
  56. » [SI-LIST] Re: IEEE CPMT inaugural meeting in Portland, OR area, Grossman, Brett
  57. » [SI-LIST] Why 50 ohms, mani kantan
  58. » [SI-LIST] Re: Why 50 ohms, Patrick_Carrier
  59. » [SI-LIST] Common Clock and Source Synchronous Timing Margins, Abe Riazi
  60. » [SI-LIST] About HSTL and LVDS I/Os, Sachin Kadu
  61. » [SI-LIST] FW: Re: Why 50 ohms, G Korony
  62. » [SI-LIST] Why 50 Ohms - Howard Johnson explains, Charles Grasso
  63. » [SI-LIST] PV/PT Tables IBIS, Pritchard, Jason
  64. » [SI-LIST] Re: PV/PT Tables IBIS, Muranyi, Arpad
  65. » [SI-LIST] Re: 100 ohm differential GHz trace width and gap, Doug Hopperstad
  66. » [SI-LIST] Simulating IBIS models using XTK, Khalid Ansari
  67. » [SI-LIST] Try to find the e-copy of manual, Yuping Wu
  68. » [SI-LIST] RLGC matrix, Bob Patel
  69. » [SI-LIST] Re: FW: Re: Why 50 ohms (urban legend), Ivor Bowden
  70. » [SI-LIST] Book, Bob Patel
  71. » [SI-LIST] Re: Book, Paglia, Frank M
  72. » [SI-LIST] Reference for differential Gigabit traces, Alex March
  73. » [SI-LIST] AC Specs and SI in an MCP, Aaron Frank
  74. » [SI-LIST] European IBIS Summmit - Second Announcement, Ross, Bob
  75. » [SI-LIST] Re: Common Clock and Source Synchronous Timing Margins, Abe Riazi
  76. » [SI-LIST] Re: RLGC matrix, Erhan Kaya
  77. » [SI-LIST] Capacitor Measurements to 10 GHz, Tony Anthony
  78. » [SI-LIST] SSTL-2 differential receivers, Simon Assouad
  79. » [SI-LIST] Hspice B element, Khalid Ansari
  80. » [SI-LIST] Effect of vias on Ground performance, fullname
  81. » [SI-LIST] Re: Effect of vias on Ground performance, Zhou, Xingling (Mick)
  82. » [SI-LIST] Re: Hspice B element, Ingraham, Andrew
  83. » [SI-LIST] Re: Routing a 10-bit bus on tandem grid, Doug Hopperstad
  84. » [SI-LIST] Re: SI Position Open READ THIS!!!!, Mike Ventham
  85. » [SI-LIST] Re: rise time performance, Jason D Leung
  86. » [SI-LIST] [SI-LIST]: Pull-up resistor value, anand kuriakose
  87. » [SI-LIST] local and global ground, Perry Qu
  88. » [SI-LIST] Re: local and global ground, Ingraham, Andrew
  89. » [SI-LIST] CLK Input not 3.3V tolerant, Yannick Gagnon
  90. » [SI-LIST] Re: CLK Input not 3.3V tolerant, James_R_Jones
  91. » [SI-LIST] Re: HSDD: Re: SI Position Open READ THIS!!!!, Kai, Francis
  92. » [SI-LIST] Re: Common Clock and Source SynchronousTimingMargins, abe riazi
  93. » [SI-LIST] Re: Vintage Engineers, Michael_Greim
  94. » [SI-LIST] power spectral density of random signal with finite rise/fall time, Jan Vercammen
  95. » [SI-LIST] Buffer Drive Strength, Ken Patterson
  96. » [SI-LIST] Re: Buffer Drive Strength, Muranyi, Arpad
  97. » [SI-LIST] Re: Flight time measurements and post-route analysis, Michael_Greim
  98. » [SI-LIST] Non-monotonic, Ched-Chang Chai
  99. » [SI-LIST] AC coupling placement, Ben Rothchild
  100. » [SI-LIST] Re: Non-monotonic, Ingraham, Andrew
  101. » [SI-LIST] PC to Osilloscope communication, Rich Peyton
  102. » [SI-LIST] additional characters, Vadim Heyfitch
  103. » [SI-LIST] -48V packaging references, Shawn Arnold
  104. » [SI-LIST] Re: AC coupling placement, Randol Mark-ryvw50
  105. » [SI-LIST] Re: New Math?, Bill Dempsey
  106. » [SI-LIST] Re: Still looking for input ...., Beal, Weston
  107. » [SI-LIST] Re: PC to Osilloscope communication, James_R_Jones
  108. » [SI-LIST] [Fwd: Re: Re: AC coupling placement], Hassan O. Ali
  109. » [SI-LIST] Re: additional characters, Lund, Steve