[SI-LIST] via inductance


Hi SI gurus,

Here is a situation I need your help.

On a package substrate, for some critical traces, we need to increase the
trace width to reduce self inductance.  The trace runs on 2 layers on the
substrate connected by a via.  As the trace width is increased, the via
inductance in more apparent.  

So the idea is to use two vias instead of one to connect the trace between
the two layers.  The two vias are placed very close to each other so that
the inductance can be reduced.

My concern is this structure (signal being split and combined) may cause SI
problems in terms of delay, noise, etc.  Could anyone with experience on
this give me a highlight?






Thanks,
Pat 



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