[SI-LIST] uper to How high the frequency to scan is sufficient for target impedanceof Power distribution system

HI:
   For a highspeed digital system PCB, we should control its PDS Impedance 
not to exceed its target Impedance from low frequency uper to high 
frequency, but how higher the upper frequency is good enough, and how 
lower the frequency ? Deducing from the Pulse width of the PCB 
simultaneous switch noise or from the signal rise/fall edge and its pulse 
width ? Can anyone give me some clear equation! 
regards 
meng yubao

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