[SI-LIST] Re: uper to How high the frequency to scan is sufficient for target impedance of Power distribution system

Hi Meng,

I have read some papers that use 'risetime/0.35' for the upper bound
frequency. However I'm not sure where this thing comes from. Perhaps
others can comment on this too. The lower bound basically is from DC.

Regards,
 
Chuan

> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx 
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of 
> meng.yubao@xxxxxxxxxx
> Sent: Monday, April 26, 2004 2:52 AM
> To: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
> Subject: [SI-LIST] uper to How high the frequency to scan is 
> sufficient for target impedance of Power distribution system
> 
> 
> HI:
>    For a highspeed digital system PCB, we should control its 
> PDS Impedance 
> not to exceed its target Impedance from low frequency uper to high 
> frequency, but how higher the upper frequency is good enough, and how 
> lower the frequency ? Deducing from the Pulse width of the PCB 
> simultaneous switch noise or from the signal rise/fall edge 
> and its pulse 
> width ? Can anyone give me some clear equation! 
> regards 
> meng yubao
> 
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