[SI-LIST] unbalanced setup/hold for DDR3 read

  • From: "Qu, Pingyu (Perry)" <perry.qu@xxxxxxxxxxxxxxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 15 Apr 2010 13:54:19 -0500


I made a small spreadsheet to help my understanding on DDR3 read timing for 
DQ/DQs. Data are extracted from JEDEC spec:

DRAM speed      period (ps)     bit time (ps) tDQSQ(ps) tQH(ps) setup (ps) hold 
800           2500            1250               200    950       425          
1066          1875            937.5              150    712.5     318.75        
1333          1500            750                125    570       250         
1600          1250            625                100    475       212.5 162.5

tQH = 0.38*Tck (avg) according to the spec. Setup/hold refers to the time 
window between DQ and DQs when they arrive at controller after a 90 degree 
phase shift (1/4 clock cycle), and calculated as:

Setup = 0.25*Tck - tDQSQ
Hold = tQH - 0.25*Tck

This is purely static timing with no SI effect taken into account. From above, 
we can see there is significant unbalance between setup and hold requirement. 
If we take into account clock jitter and duty cycle distortion from controller 
clock output, it will be worse for the hold side, as they directly eats into 
hold margin. How does one balance the setup and hold so that we don't end up 
with lots of setup margin but no margin or negative margin for hold ? Wonder 
where this magic 0.38 number comes from ?


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