[SI-LIST] tsmc clamping diodes

Does anyone have a good strategy for including clamping diode and esd effects 
in pre-silicon simulation of IO buffers for signal integrity. We have issues 
with tsmc's clamping diodes and esd structures modeling. Tester data is how 
many people generate accurate IBIS models and characterize the buffer 
performance, but post-silicon is too late to catch some SI issues.

Thanks for any input.

Ryan Bethel 

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