[SI-LIST] trace impedance difference in same signal group of Intel guide
- From: fei xue <harrison_cls@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 5 May 2010 15:12:22 +0800 (CST)
Hello all,
May I raise a question to all of you, as you know, Intel does more constraints
restrictions than any other semiconductor vendor especially in MCH platform
design guide (PDG). For example, in DDR2 control group signal constraints (CKE,
CS and ODT signals) of Intel Bigby 3210 MCH chipset, the characteristic trace
impedance of the DDR2 control group signals from MCH to Channel A dimms is
37Ohm+/-15%, however the characteristic trace impedance from MCH to Channel B
dimms is 28Ohm+/-10%. The traces of Channel B dimms are longer than Channel A
dimms. My question are,
1, why is the trace characteristic trace impedance of Channel A dimms different
from impedance of Channel B dimms.
2, I checked the IBIS model, the output buffer model of Channel A dimms is the
same as model of Channel B dimms, they are 38.9Ohm (I got this from IBIS VI
curves), so it is not the reason of buffer output impedance.
3, I do not think the trace impedance's difference is because of trace distance
difference between Channnel A and Channel B, 37Ohm and 28Ohm are big gaps.
4, PCB manufactory gave us feedback that they can not control trace impedance
within 28Ohm+/-10%, what they can do is controlling impedance within
28Ohm+/-5Ohm, how to evaluate this impact? can we confirm with manufactory that
controlling impedance within 28Ohm+/-5Ohm is ok or not.
I appreciate if you have any hints on this.
Harrison
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