[SI-LIST] tDQSCK

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Hi,=20

I have question about Micron DDR parameter tDQSCK=3DAccess window of DQS
from CK/CK#.=20
According Micron data sheet this time is jitter and not skew.=20

=20
Please see the diagram from Micron data sheet : the DQS signal could be
wider or thinner because max. and min. of tDQSCK.

But according to JEDEC JESD79E  tDQSCK  is skew from CK/CK#  and DQS
could not be wider or thinner please see below diagram from JEDEC.

=20
The problem is when I prepare timing diagrams with TimingDesigner tool
if I assume than tDQSCK  is jitter from CK/CK#  and DQS could be wider
or thinner than I get time violation.

If I assume than tDQSCK  is skew from CK/CK#  and DQS could not be wider
or thinner than timing is OK.=20




Best regards,
Edi Fraiman







     - - - - - Appended by Scientific Atlanta, a Cisco company - - - - -=20
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