[SI-LIST] Re: suggestions for routing fpbga of 1152 pins

  • From: Tayyab Jamil <tayyab@xxxxxxxxxxxxxx>
  • To: azam_si_engr@xxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Thu, 13 May 2004 10:06:08 +0500

You can use 18/10 mil (pad/hole) via with 4/4 mil (track/clearance) routing
to escape the BGA. Row count in the package will determine the minimum
number of rows required to escape the BGA.

Tayyab


-----Original Message-----
From: Muhammad azam [mailto:azam_si_engr@xxxxxxxxx]
Sent: Thursday, May 13, 2004 9:47 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] suggestions for routing fpbga of 1152 pins


Dear all,
I want to design a card consists of 1152pins,an FpBGA,it is .8mmpitch bga.
Anyone plz may suggest about the specifications of routing.
Thanks
azam
wuby <r92101@xxxxxxxxxxxxxxxxxx> wrote: 
Dear all:
How to simulate the kvco using spice?

Is there any other tool to simulate it?

And how !?

Thank you a lot!



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