[SI-LIST] spyhole, keyhole, peephole

Tom,

This is a technique we use frequently, as it's fairly easy with an 
FPGA.  All that's needed is for two outputs of the FPGA to be configured 
as strong IO drivers, and driven to a 1 and a 0.  This allows a few 
useful measurements to be made.

Measuring the driven 1 against the driven 0 will tell you the amount of 
rail collapse at the die.  Measuring the driven 0 against a local ground 
connection on the PCB will tell you the amount of ground bounce of the 
die relative to PCB ground.

Note that in the case of an FPGA, this technique only works for IO 
supplies.  Core logic (FPGA fabric) supplies are separated from IO 
supplies both at the package and die level, so it's not possible to get 
good accuracy of you try using this technique to measure rail collapse 
of the core supply.  However, in many devices (including Xilinx FPGAs), 
the ground node is common to all supplies.  This makes it possible to 
measure the degree of ground bounce of the core indirectly through a 
driven 0 as above.  You have to be careful when interpreting that result 
though.

This technique can be used anywhere you have an IO driving a relatively 
constant 1 or 0.  This could be an enable signal or an address pin that 
only toggles very seldom if ever.  Just be sure to experiment a bit with 
the particular device of concern -- output driver impedance and package 
characteristics will always cloud your measurement to some degree.  
Usually you have to take a number of these measurements before you get a 
feel for how to interpret them.

At the 2002 EPEP conference, one paper (the title and author escape me 
and it's not possible to search the hardcopy proceedings) referred to 
this technique as a "spyhole."  I've heard other names and would be 
interested to hear if there are any preferred terms for this.

-mark



Tom Biggs wrote:

>I've heard this trick:
>If you are lucky (or can configure it) so there are two output pins on
>the IC where one is driven high, and the other driven low, then you can
>use these pins as probes into the internal power/ground planes. The
>probes will be through turned-on FETs, so I'm not sure what affect this
>has on the accuracy for your needs.
>
>    -tom
>
>-----Original Message-----
>From: Craig Twardy [mailto:ctwardy@xxxxxxxxxxxxxxxxxx]=20
>Sent: Monday, January 26, 2004 4:40 PM
>To: Chris Cheng; 'Larry.Smith@xxxxxxx'
>Cc: 'silist'
>Subject: [SI-LIST] Re: One last question for Chris & Larry re: Power/D
>ecoupling
>
>
>Hi Chris;
>Is there a trick to getting the pins that tap core power and gnd? I have
>asked for this before and was given all sorts of reasons Why it cannot,
>could not and will not be done.
>
>Craig
>
>-----Original Message-----
>From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]=20
>Sent: January 23, 2004 8:50 PM
>To: 'Larry.Smith@xxxxxxx'; Twardy, Craig [CAR:QF10:EXCH]
>Cc: 'silist'
>Subject: RE: [SI-LIST] Re: One last question for Chris & Larry re:
>Power/D ecoupling
>
>
>Here's a neat trick you can try. Most well designed modern processors
>have some kind of energy star, power saving power down mode that can
>literally go from deep sleep to full throttle in just a few clock
>cycles. At >1GHz or <1ns cycle time, the processor itself is one hack of
>a fancy function generator with a few ns timing resolution provided you
>can have the correct power testing program that can control the amount
>of computation (hence
>power) it executes. Couple that will a flexible PLL on die and a good
>tester, you can search and test your package power all day until you hit
>the resonance. It is just a matter of resources (product engineers and
>tester time). Most of the well designed high power Si chip should have
>secret pins that tap directly into the core power and gnd grids for
>measurements. In fact, there were proposals to directly use them to
>control the DC/DC regulator feedbacks.
>
>-----Original Message-----
>From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
>Sent: Thursday, January 22, 2004 10:52 AM
>To: ctwardy@xxxxxxxxxxxxxxxxxx
>Cc: 'silist'
>Subject: [SI-LIST] Re: One last question for Chris & Larry re: Power/D
>ecoupling
>
>
>Craig - It is difficult to know the power supply voltage at the silicon
>with accuracy at clock frequencies.  Sense probes can be wired into the
>chip but there are always questions about where on the chip to place
>them, how to route them out and how to measure them when you get out of
>the package. =20
>
>We have had real good results at the PCB level and at the top of the
>package by using a 50 Ohm coax probe soldered directly to power and
>ground. Measurements from an active probe are usually a little
>different.  The coax probe has very high bandwidth and the 'unprotected'
>loop where it is attached is very small.  You can certainly measure
>something on wires that probe into the silicon but I am not sure that
>you can believe the results.
>
>There is usually a relationship between the DC voltage and the maximum
>frequency that a processor will run.  Alex Waizman from Intel has done
>some good work in this area.  Most of us believe that noise on top of
>the DC voltage will decrease Fmax, but this relationship is probably
>frequency dependent and difficult to quantify.
>
>It may be possible to inject noise on low power systems, but for 100W
>processors, noise injection is difficult at best.
>
>This is a difficult area which is ripe for technical development.  I'd
>be interested in comments from others on the list for this topic.
>
>regards,
>Larry Smith
>Sun Microsystems
>
>Craig Twardy wrote:
>
>
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