[SI-LIST] spice question

Is there any feature in Hspice not to go through the error check, etc. when it 
is running the simulations agian through .alter statement?  I believe the 
.alter statments should not take the same time as the original one? any help?
   
  Kami
   
   
                
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From: "Mikhail Matusov" <matusov@xxxxxxxxxxxx>
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Subject: [SI-LIST] Re: DAC clock 
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Marimuthu,

> Can you suggest
> some clock sources to provide the input clock to this DAC

AD9510 is one example.

> and what is =
> the use
> of dedicated clock out pins in this DAC? Should we use this clock out =
> pins?

It is usually used to drive the input data interface. Watch the spurious
produced by this clock....

> Currently we are using VCO190-1200MHz with PLL as a input clock source. =
> Can
> anybody tell the fan-out of VCO and how to calculate that?=20

Most of the VCOs are designed to drive a 50 Ohm load. When used as clock
sources they are usually followed by some sort of a driver, PECL being the
most common.

=======================
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: +1 (613) 271-0044 ext.231
Fax: +1 (613) 271-3007
http://www.squarepeg.ca



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